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* x86: mp: Add more comments to the moduleSimon Glass2020-07-202-3/+102
* x86: mtrr: Add support for writing to MTRRs on any CPUSimon Glass2020-07-202-0/+102
* x86: mtrr: Update MTRRs on all CPUsSimon Glass2020-07-201-0/+57
* x86: Don't enable SMP in SPLSimon Glass2020-07-202-2/+2
* x86: mtrr: Use MP calls to list the MTRRsSimon Glass2020-07-202-0/+41
* x86: mp: Add iterators for CPUsSimon Glass2020-07-202-0/+105
* x86: mp: Park CPUs before running the OSSimon Glass2020-07-203-0/+38
* x86: mp: Allow running functions on multiple CPUsSimon Glass2020-07-202-6/+134
* x86: Set the SMP flag when MP init is completeSimon Glass2020-07-201-0/+1
* x86: mp: Support APs waiting for instructionsSimon Glass2020-07-204-8/+134
* x86: cpu: Remove unnecessary #ifdefsSimon Glass2020-07-202-29/+26
* x86: mp_init: Adjust bsp_init() to return more informationSimon Glass2020-07-201-13/+23
* x86: mp_init: Set up the CPU numbers at the startSimon Glass2020-07-201-12/+9
* x86: mp_init: Drop the num_cpus static variableSimon Glass2020-07-201-7/+15
* x86: mp_init: Switch parameter names in start_aps()Simon Glass2020-07-201-6/+19
* x86: mp_init: Avoid declarations in header filesSimon Glass2020-07-202-23/+20
* x86: Move MP code into mp_initSimon Glass2020-07-203-47/+16
* x86: mp_init: Switch to livetreeSimon Glass2020-07-201-2/+1
* mips: octeon: Add minimal Octeon 3 EBB7304 EVK supportStefan Roese2020-07-183-0/+111
* mips: octeon: use mips_mach_early_init() to copy to L2 cacheStefan Roese2020-07-182-0/+51
* mips: octeon: dts: Add Octeon 3 cn73xx base dtsi fileStefan Roese2020-07-181-0/+64
* mips: octeon: Initial minimal support for the Marvell Octeon SoCAaron Williams2020-07-1812-0/+312
* mips: Add CONFIG_MIPS_MACH_EARLY_INIT for very early mach init codeStefan Roese2020-07-182-0/+14
* mips: sync asm/mipsregs.h with Linux 5.7Daniel Schwierzeck2020-07-185-196/+1103
* mips: sync asm/addrspace.h with Linux 5.7Daniel Schwierzeck2020-07-181-12/+2
* mips: sync asm/asm.h with Linux 5.7Daniel Schwierzeck2020-07-181-120/+10
* mips: remove deprecated UNCACHED_SDRAM() macroDaniel Schwierzeck2020-07-182-15/+2
* mips: add config options for generic cache setup codeDaniel Schwierzeck2020-07-182-1/+29
* mips: refactor disabling of cachesDaniel Schwierzeck2020-07-182-5/+10
* mips: add KSEG1 wrapper for change_k0_ccaDaniel Schwierzeck2020-07-181-14/+18
* mips: start.S: remove dead codeDaniel Schwierzeck2020-07-181-9/+0
* mips: cache: Make invalidate_dcache_range() weak to enable overwriteStefan Roese2020-07-181-1/+1
* mips: cache: Make flush_cache() weak to enable overwriteStefan Roese2020-07-181-1/+1
* mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CMStefan Roese2020-07-182-2/+12
* mips: reloc: Change R_MIPS_NONE to catch pre-reloc BSS usageStefan Roese2020-07-182-4/+5
* mips: traps: Set WG bit in EBase register on OcteonStefan Roese2020-07-182-0/+5
* mips: time: Only compile the weak get_tbclk() when neededStefan Roese2020-07-181-0/+2
* treewide: convert bd_t to struct bd_info manuallyMasahiro Yamada2020-07-176-6/+6
* treewide: convert bd_t to struct bd_info by coccinelleMasahiro Yamada2020-07-1763-113/+117
* Convert CONFIG_ARMV7_PSCI_1_0 and CONFIG_ARMV7_PSCI_0_2 to KconfigPatrick Delaunay2020-07-171-0/+14
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini2020-07-1740-173/+1199
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| * acpi: Enable ACPI table generation by default on x86Simon Glass2020-07-171-0/+1
| * x86: Rename board_final_cleanup() to board_final_init()Simon Glass2020-07-175-9/+9
| * x86: acpi: Correct the version of the MADTSimon Glass2020-07-171-1/+1
| * x86: Drop setup_pcat_compatibility()Simon Glass2020-07-172-12/+0
| * x86: Update the comment about booting for FSP2Simon Glass2020-07-171-0/+1
| * x86: Store the coreboot table address in global_dataSimon Glass2020-07-173-2/+14
| * x86: apl: Adjust FSP-M code to avoid hard-coded addressSimon Glass2020-07-171-1/+2
| * x86: apl: Set the correct boot mode in the FSP-M codeSimon Glass2020-07-171-1/+2
| * x86: Add debugging to table writingSimon Glass2020-07-171-10/+28