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* sandbox: Drop debug message in os_spl_to_uboot()Simon Glass2021-03-221-1/+0
| | | | | | | | | This is not needed in normal operation. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* sandbox: i2c: Rename driver names to work with of-platdataSimon Glass2021-03-221-2/+2
| | | | | | | Some of these do not follow the rules. Make sure the driver name matches the compatible string in all cases. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Make sandbox,emul more conventionalSimon Glass2021-03-221-1/+5
| | | | | | | | At present this property is a phandle but does not have a #xxx-cells property to match it. Add one so that is works the same as gpio and clock phandles. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: enable cros-ec-keyb in test.dtbHeinrich Schuchardt2021-03-221-0/+1
| | | | | | | | | | | Currently keyboard input fails in the GUI window opened by ./u-boot -T -l Add the missing include to test.dts. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* board: mt7629: enable compression of u-boot to reduce the size of final imageWeijie Gao2021-03-202-19/+0
| | | | | | | This patch makes use of the decompression mechanism implemented for mt7628 previously to reduce the total image size. Binman will be also removed. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* dts: mt7629: enable JTAG pins by defaultWeijie Gao2021-03-202-0/+16
| | | | | | | | | The EPHY LEDs belongs to the built-in FE switch of MT7629, which is barely used. These LED pins on reference boards are used as JTAG socket. So it's a good idea to change the default state to JTAG, and this will make it convenience for debugging. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* board: Add MT8183 pumpkin board supportFabien Parent2021-03-203-0/+101
| | | | | | Add the MT8183 pumpkin board support. Signed-off-by: Fabien Parent <fparent@baylibre.com>
* ARM: mediatek: Add MT8183 supportFabien Parent2021-03-205-0/+367
| | | | | | Add the MT8183 SoC support. Signed-off-by: Fabien Parent <fparent@baylibre.com>
* board: mediatek: rename pumpkin board into mt8516Fabien Parent2021-03-201-1/+1
| | | | | | | | | More than one pumpkin board has been made with different MediaTek SoCs. Rename the pumpkin board to follow the naming convention of all other MediaTek boards and also to not be confusing when other pumpkin boards will be added in follow-up commits. Signed-off-by: Fabien Parent <fparent@baylibre.com>
* board: silinux: Enable recovery SPL for EK874 boardLad Prabhakar2021-03-161-1/+1
| | | | | | | Enable building SPL for EK874 board which is based on R8A774C0 SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
* arm: rmobile: Add Silicon Linux EK874 board supportLad Prabhakar2021-03-167-0/+625
| | | | | | | | | | | | | | | The EK874 development kit from Silicon Linux is made of CAT874 (the main board) and CAT875 (the sub board that goes on top of CAT874). This patch adds the required board support to boot Si-Linux EK874 board based on R8A774C0 SoC. DTS files apart from r8a774c0-ek874-u-boot.dts and r8a774c0-u-boot.dtsi have been imported from Linux kernel 5.11 commit f40ddce88593 ("Linux 5.11"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
* pinctrl: renesas: Add support for R8A774C0Lad Prabhakar2021-03-161-0/+1
| | | | | | | | | | | Renesas RZ/G2E (a.k.a. r8a774c0) is pin compatible with R-Car E3 (a.k.a. r8a77990), however it doesn't have several automotive specific peripherals. This patch hooks R8A774C0 SoC with the pfc driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
* arm: dts: r8a774c0: Resync R8A774C0 SoC DTSI with Linux 5.11Lad Prabhakar2021-03-161-4/+23
| | | | | | | Resync the R8A774C0 SoC DTSI with Linux kernel 5.11 commit f40ddce88593 ("Linux 5.11"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
* arm: rmobile: Add HopeRun HiHope RZ/G2H board supportBiju Das2021-03-164-0/+88
| | | | | | | | | | | | | The HiHope RZ/G2H board from HopeRun consists of main board (HopeRun HiHope RZ/G2H main board) and sub board(HopeRun HiHope RZ/G2H sub board). The HiHope RZ/G2H sub board sits below the HiHope RZ/G2H main board. This patch adds the required board support to boot HopeRun HiHope RZ/G2H board. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
* arm: rmobile: Add HopeRun HiHope RZ/G2N board supportBiju Das2021-03-164-0/+82
| | | | | | | | | | | | | The HiHope RZ/G2N board from HopeRun consists of main board (HopeRun HiHope RZ/G2N main board) and sub board(HopeRun HiHope RZ/G2N sub board). The HiHope RZ/G2N sub board sits below the HiHope RZ/G2N main board. This patch adds the required board support to boot HopeRun HiHope RZ/G2N board. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
* arm: rmobile: Add HopeRun HiHope RZ/G2M board supportBiju Das2021-03-162-0/+15
| | | | | | | | | | | | | The HiHope RZ/G2M board from HopeRun consists of main board (HopeRun HiHope RZ/G2M main board) and sub board(HopeRun HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits below the HiHope RZ/G2M main board. This patch adds the required board support to boot HopeRun HiHope RZ/G2M board. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
* arm: dts: rmobile: r8a774e1: Synchronize DTs with Linux 5.11Biju Das2021-03-162-0/+61
| | | | | | | Synchronize r8a774e1 device trees with Linux 5.11, commit f40ddce88593482919 ("Linux 5.11"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
* arm: dts: rmobile: r8a774b1: Synchronize DTs with Linux 5.11Biju Das2021-03-162-0/+62
| | | | | | | Synchronize r8a774b1 device trees with Linux 5.11, commit f40ddce88593482919 ("Linux 5.11") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
* Merge tag 'v2021.04-rc4' into nextTom Rini2021-03-1573-199/+6191
|\ | | | | | | Prepare v2021.04-rc4
| * Merge tag 'u-boot-stm32-20210312' of ↵Tom Rini2021-03-1510-59/+101
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-stm - Add WATCHDOG_RESET() in MTD framework and STM32 QSPI driver - stm32mp1_trusted_defconfig rely on SCMI support - Remove the nand MTD configuration for NOR boot in stm32mp1 board - STM32programmer update - Bsec: manage clock when present in device tree - stm32mp15: move bootdelay configuration in defconfig - Update for stm32 dsi and dw_mipi_dsi - STM32 MCU's cleanup - Fix compilation issue depending on SYS_DCACHE_OFF and SYS_ICACHE_OFF flags - Update stm32mp1 doc
| | * arm: stm32mp: Fix compilation issue when SYS_DCACHE_OFF and/or ↵Patrice Chotard2021-03-121-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SYS_DCACHE_SYS are enabled Fix following compilation issue when SYS_DCACHE_OFF and/or SYS_DCACHE_SYS are enabled : arch/arm/mach-stm32mp/cpu.c: In function ‘early_enable_caches’: arch/arm/mach-stm32mp/cpu.c:223:10: error: ‘volatile struct arch_global_data’ has no member named ‘tlb_size’ 223 | gd->arch.tlb_size = PGTABLE_SIZE; | ^ arch/arm/mach-stm32mp/cpu.c:224:10: error: ‘volatile struct arch_global_data’ has no member named ‘tlb_addr’ 224 | gd->arch.tlb_addr = (unsigned long)&early_tlb; | ^ Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| | * stm32mp: bsec: manage clock when present in device treePatrick Delaunay2021-03-111-0/+10
| | | | | | | | | | | | | | | | | | | | | Enable the clocks during bsec probe when they are present in device tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| | * stm32mp: stm32prog: replace alias by serial device sequence numberPatrick Delaunay2021-03-112-30/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The command "stm32prog serial <dev>" can directly use the device sequence number of serial uclass as this sequence number is egual to alias when it exist; this assumption simplify the code and avoid access to gd->fdt_blob and the device tree parsing. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| | * stm32mp: stm32prog: reactivate console and display serial errorPatrick Delaunay2021-03-111-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | When serial instance is not found in device tree, the console should be enabled and the error should be indicated. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| | * stm32mp: stm32prog: Add CONFIG_CMD_STM32PROG_SERIAL and _USBPatrick Delaunay2021-03-116-12/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CONFIG_CMD_STM32PROG_SERIAL and CONFIG_CMD_STM32PROG_USB to independently select the support of UART or USB communication for STM32CubeProgrammer. For serial boot over UART, user can deactivate CONFIG_CMD_STM32PROG_SERIAL to use U-Boot console of binary loaded by UART (for board bring-up for example). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| | * stm32mp: stm32prog: Add Kconfig file for stm32prog commandPatrick Delaunay2021-03-112-17/+19
| | | | | | | | | | | | | | | | | | | | | Move CONFIG_CMD_STM32PROG in a specific Kconfig file for stm32prog command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| | * ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driverEtienne Carriere2021-03-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define in the RCC clock provider node which root clocks the driver depends on. These are root oscillators, which may be present or not, upon FDT content. This update binding is introduced in Linux kernel device tree by patch "ARM: dts: stm32: move clocks/resets to SCMI resources for stm32mp15" This patch is a preliminary step for SCMI support of stm32mp15 boards with trusted boot chain, based on TF-A or OP-TEE. Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| * | arm: mvebu: a38x: Remove dead code ARMADA_39XPali Rohár2021-03-124-106/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Config option ARMADA_39X is never set so remove all dead code hidden under ifdef CONFIG_ARMADA_39X blocks. Also remove useless checks for CONFIG_ARMADA_38X define as this macro is always defined for a38x code path. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
| * | x86: Select advanced Intel code only if allowedSimon Glass2021-03-092-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present most of the Intel-specific code is built on all devices, even those which don't have software support for the features provided there. This means that any board can enable CONFIG_INTEL_ACPIGEN even if it does not have the required features. Add a new INTEL_SOC option to control this access. This must be selected by SoCs that can support the required features. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed a typo in arch/x86/Kconfig] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Move INTEL_ACPIGEN to arch/x86Simon Glass2021-03-091-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option is better placed in the x86 code since it is not generic enough to be in the core code. Move it. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed a typo in arch/x86/Kconfig] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Fix member check in intel_gnvsSimon Glass2021-03-091-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_CHROMEOS is not enabled this currently does not build. Fix it. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: sizeof-array-div error in lpc_common_early_initHeinrich Schuchardt2021-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Building qemu-x86_64_defconfig with GCC 11.0 fails with: arch/x86/cpu/intel_common/lpc.c: In function ‘lpc_common_early_init’: arch/x86/cpu/intel_common/lpc.c:56:40: error: expression does not compute the number of elements in this array; element type is ‘struct reg_info’, not ‘u32’ {aka ‘unsigned int’} [-Werror=sizeof-array-div] 56 | sizeof(values) / sizeof(u32)); | ^ arch/x86/cpu/intel_common/lpc.c:56:40: note: add parentheses around the second ‘sizeof’ to silence this warning arch/x86/cpu/intel_common/lpc.c:50:11: note: array ‘values’ declared here 50 | } values[4], *ptr; | ^~~~~~ Add parentheses to silence warning. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | arm: socfpga: dts: soc64: Update filename in binman node of FIT image with ↵Siew Chin Lim2021-03-081-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | VAB support FIT image of Vendor Authentication Coot (VAB) contains signed images. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
| * | arm: socfpga: cmd: Support 'vab' commandSiew Chin Lim2021-03-082-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | Support 'vab' command to perform vendor authentication. Command format: vab addr len Authorize 'len' bytes starting at 'addr' via vendor public key Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
| * | arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)Siew Chin Lim2021-03-086-4/+308
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Vendor Authorized Boot is a security feature for authenticating the images such as U-Boot, ARM trusted Firmware, Linux kernel, device tree blob and etc loaded from FIT. After those images are loaded from FIT, the VAB certificate and signature block appended at the end of each image are sent to Secure Device Manager (SDM) for authentication. U-Boot will validate the SHA384 of the image against the SHA384 hash stored in the VAB certificate before sending the image to SDM for authentication. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64Siew Chin Lim2021-03-084-7/+10
| | | | | | | | | | | | | | | | | | Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
| * | ppc: qemu: Move board directory from board/freescale to board/emulationBin Meng2021-03-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | board/emulation is the place for other QEMU targets like x86, arm, riscv. Let's move the qemu-ppce500 board codes there. List me as a co-maintainer for this board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | gpio: mpc8xxx: Support controller register physical address beyond 32-bitBin Meng2021-03-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | dev_read_addr_size_index() returns fdt_addr_t which might be a 64-bit physical address. This might be true for some 85xx SoCs whose CCSBAR is mapped beyond 4 GiB. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | ppc: mpc85xx: Add 'gpibe' register to 'struct ccsr_gpio'Bin Meng2021-03-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Without this, the DM GPIO driver for MPC8xxx does not compile for MPC85xx SoCs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | ppc: io.h: Use addrmap_ translation APIs only in post-relocation phaseBin Meng2021-03-051-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In phys_to_virt() and virt_to_phys(), if CONFIG_ADDR_MAP is defined, they use addrmap_ translation APIs to do the address translation. However these APIs only work in post-relocation phase. Update the code logic to fall back to use the default one when in pre-relocation phase. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | ppc: mpc85xx: Wrap LAW related codes with CONFIG_FSL_LAWBin Meng2021-03-052-0/+4
| | | | | | | | | | | | | | | | | | | | | LAW related codes should be wrapped with CONFIG_FSL_LAW. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | configs: fsl: move via specific defines to KconfigRajesh Bhagat2021-03-051-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moves below via specific defines to Kconfig: CONFIG_FSL_VIA Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | configs: fsl: move bootrom specific defines to KconfigRajesh Bhagat2021-03-052-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moves below bootrom specific defines to Kconfig: CONFIG_SYS_FSL_BOOTROM_BASE CONFIG_SYS_FSL_BOOTROM_SIZE Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | Merge tag 'u-boot-imx-20210303' of ↵Tom Rini2021-03-0334-11/+5644
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX for 2021.04 ---------------- - new boards: - i.MX8MN Beacon EmbeddedWorks (2GB) - Gateworks Venice imx8mm - convert to DM: - imx53-qsb, mx53loco, mx51evk, mx23-evk - Fixes : - Network : FEC ethernet quirks - DH dh-imx6 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6597
| | * | board: gateworks: imx8mm: Add Gateworks Venice board supportTim Harvey2021-03-037-0/+382
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for Gateworks Venice product family based on the i.MX 8M Mini SoC Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * | arm: dts: imx8mm: add Gateworks i.MX8 Mini Dev kitsTim Harvey2021-03-038-0/+1415
| | | | | | | | | | | | | | | | | | | | | | | | Add Gateworks i.MX 8M Mini Development kits from Linux-5.12-rc1 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| | * | ARM: imx: Include u-boot.img in u-boot-with-spl.imx if OF_SEPARATE=yMarek Vasut2021-03-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The u-boot-with-spl.imx is a concatenation of SPL and u-boot.uim. The u-boot.uim is u-boot.bin wrapped in uImage. In case OF_SEPARATE is enabled, the u-boot.bin does not contain control DT for U-Boot, and so u-boot.uim does not contain the DT, and so u-boot-with-spl.imx does not contain the DT, and a system where u-boot-with-spl.imx is written to offset 1024B to the start of storage no longer boots, as it is missing DT. In case OF_SEPARATE is enabled, u-boot.img contains both u-boot.bin and the necessary DTs. Therefore, use u-boot.img instead of u-boot.uim to generate u-boot-with-spl.imx when OF_SEPARATE is enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Christoph Niedermaier <cniedermaier@dh-electronics.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
| | * | ARM: imx: Do not hard-code MX8M MMU table DRAM entry offsetMarek Vasut2021-03-011-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of hard-coding the offset of DRAM entries in MMU table all over the code, auto-detect the offset. This removes error-prone code which would break e.g. in case the MMU table is modified. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
| | * | ARM: dts: imx8mq-evk: Remove u-boot,off-on-delay-us propertyFabio Estevam2021-03-011-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 247bbeb74c18 ("ARM: dts: imx8m: increase off-on delay on the SD Vcc regulator") caused the imx8mq-evk board to not be able to store the environment variables in the SD card. Remove the u-boot,off-on-delay-us property to fix the regression. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
| | * | arm: dts: imx8mp-evk: Add FEC PHY reset timingYe Li2021-03-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add phy-reset-duration and phy-reset-post-delay to FEC node for PHY reset, otherwise the PHY does not work correctly. Signed-off-by: Ye Li <ye.li@nxp.com>
generated by cgit (git 2.34.1) at 2024-09-24 23:16:06 +0000