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* arm64: zynqmp: Add support for generic QSPI bootMichal Simek2017-12-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is enabling support for SPL QSPI boot. First of all it is necessary to generate atf-spi.ub which is different format than atf-uboot.ub (this can be made as legacy image too) ADDR=`arm-xilinx-linux-gnueabi-readelf -a bl31.elf | grep "Entry point address" | cut -d ':' -f 2 | sed -e 's/^[ \t]*//'` aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin ./tools/mkimage -f auto -A arm64 -T firmware -C none -O u-boot -a $ADDR -e $ADDR -n "atf1" -E -b arch/arm/dts/zynqmp-zcu102.dtb -d bl31.bin atf-uboot.ub ./tools/mkimage -A arm64 -T firmware -C none -O u-boot -a $ADDR -e $ADDR -n "atf-for-qspi" -E -d bl31.bin atf-spi.ub This patch is using this QSPI layout with offsets: 0 boot.bin 512k atf-ub 640k u-boot.bin 1280k u-boot.img Which corresponding by writing these images(read from MMC) mmcinfo sf probe load mmc 0 10000000 boot.bin sf erase 0 +$filesize sf write 10000000 0 $filesize load mmc 0 10000000 atf-spi.ub sf erase 0x80000 +$filesize sf write 10000000 0x80000 $filesize load mmc 0 10000000 u-boot.bin sf erase 0xa0000 +$filesize sf write 10000000 0xa0000 $filesize load mmc 0 10000000 u-boot.img sf erase 0x140000 +$filesize sf write 10000000 0x140000 $filesize For testing u-boot running in EL3 you can break atf-spi.ub like this: sf probe sf erase 0x80000 +4 Then u-boot.img is executed. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add reference to pmu firmware nodeMichal Simek2017-12-141-1/+1
| | | | | | | This reference is needed for pinctrl driver where some signals can be routed directly to platform management unit (PMU). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: pxa: Remove unused ifdefsTuomas Tynkkynen2017-12-121-29/+0
| | | | | | | | These ifdefs are protecting #include statements for files that have never existed. AFAICT this hardware.h has been copied from the kernel and the ifdefs have never served a role in U-Boot, so delete them. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
* ata: Migrate CONFIG_MVSATA_IDE to KconfigTuomas Tynkkynen2017-12-121-1/+0
| | | | Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
* ata: Migrate CONFIG_LIBATA to KconfigTuomas Tynkkynen2017-12-121-1/+0
| | | | | | | | This symbol enables some library code used by various SATA drivers, so make this a non-user-visible symbol select'ed by the respective drivers, and let moveconfig handle the rest. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
* ata: Migrate CONFIG_SCSI_AHCI to KconfigTuomas Tynkkynen2017-12-1211-1/+13
| | | | | | And use 'imply' liberally. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
* ata: Migrate CONFIG_FSL_SATA to KconfigTuomas Tynkkynen2017-12-122-0/+14
| | | | | | | Use 'imply' here liberally to avoid the combinatorial explosion of defconfig changes in the PowerPC boards. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
* ata: Migrate CONFIG_SATA_SIL to KconfigTuomas Tynkkynen2017-12-121-0/+6
| | | | | | | Use 'imply' here liberally to avoid the combinatorial explosion of defconfig changes in the PowerPC boards. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
* Merge git://git.denx.de/u-boot-uniphierTom Rini2017-12-112-5/+11
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| * ARM: uniphier: use FIELD_PREP for PLL settingsMasahiro Yamada2017-12-121-6/+8
| | | | | | | | | | | | | | | | It is tedious to define both mask and bit-shift. <linux/bitfield.h> provides a convenient way to get access to register fields with a single shifted mask. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: compute SSCPLL values more preciselyMasahiro Yamada2017-12-121-2/+4
| | | | | | | | | | | | | | Use DIV_ROUND_CLOSEST(). To make the JK value even more precise, I used a bigger coefficient, then divide it by 512. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: fix SSCPLL init code for LD11 SoCDai Okamura2017-12-121-0/+1
| | | | | | | | | | | | | | | | | | Commit 682e09ff9f35 ("ARM: uniphier: add PLL init code for LD20 SoC") missed to write the computed value to the SSCPLLCTRL2 register. Fixes: 682e09ff9f35 ("ARM: uniphier: add PLL init code for LD20 SoC") Signed-off-by: Dai Okamura <okamura.dai@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: compile pll-base-ld20.c for PXs3Masahiro Yamada2017-12-121-0/+1
| | | | | | | | | | | | | | | | | | Fix the link error for the combination of CONFIG_ARCH_UNIPHIER_LD11=n CONFIG_ARCH_UNIPHIER_LD20=n CONFIG_ARCH_UNIPHIER_PXS3=y Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARC: cache: explicitly initialize "*_exists" variablesEugeniy Paltsev2017-12-111-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dcache_exists, icache_exists, slc_exists and ioc_exists global variables in "arch/arc/lib/cache.c" remain uninitialized if SoC doesn't have corresponding HW. This happens because we use the next constructions for their definition and initialization: -------------------------->>--------------------- int ioc_exists __section(".data"); if (/* condition */) ioc_exists = 1; -------------------------->>--------------------- That's quite a non-trivial issue as one may think of it. The point is we intentionally put those variables in ".data" section so they might survive relocation (remember we initilaize them very early before relocation and continue to use after reloaction). While being non-initialized and not explicitly put in .data section they would end-up in ".bss" section which by definition is filled with zeroes. But since we place those variables in .data section we need to care about their proper initialization ourselves. Also while at it we change their type to "bool" as more appropriate. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | ARC: add defines of some cache and xCCM AUX registersEugeniy Paltsev2017-12-111-0/+6
| | | | | | | | | | Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | ARC: add macro to get CPU idEugeniy Paltsev2017-12-111-0/+3
| | | | | | | | | | | | | | | | | | | | ARCNUM [15:8] field in ARC_AUX_IDENTITY register allows us to uniquely identify each core in a multi-core system. I.e. with help of this macro each core may get its index in SMP system. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | ARC: add asm/gpio.h to fix compilation error with CONFIG_CMD_GPIOEugeniy Paltsev2017-12-101-0/+1
|/ | | | | | | | | | | | With CONFIG_CMD_GPIO compilation reports error: -------------------------->8--------------------- common/cmd_gpio.c:13:22: fatal error: asm/gpio.h: No such file or directory #include <asm/gpio.h> ^ -------------------------->8--------------------- Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-12-074-7/+83
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| * armv8: LS1088A_QSPI: SECURE_BOOT: Images validationUdit Agarwal2017-12-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Validates PPA, MC, DPC, Bootscript, DPL and Kernel images in ESBC phase using esbc_validate command. Enable validation of boot.scr script prior to its execution dependent on "secureboot" flag in environment Add header address for PPA to be validated during ESBC phase for LS1088A platform based on LAyerscape Chasis 3. Moves sec_init prior to ppa_init as for validation of PPA sec must be initialised before the PPA is initialised. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: Workaround for USB erratua on LS1012ARan Wang2017-12-062-7/+24
| | | | | | | | | | | | | | | | This is suplement for patch which handle below errata: A-009007, A-009008, A-008997, A-009798 Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Add support of disabling core prefetchPrabhakar Kushwaha2017-12-062-0/+58
| | | | | | | | | | | | | | | | | | | | Instruction prefetch feature is by default enabled during core release. This patch add support of disabling instruction prefetch by setting core mask in PPA. Here each core mask bit represents a core and prefetch is disabled at the time of core release. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8: fix gd after relocationYork Sun2017-12-071-2/+3
| | | | | | | | | | | | | | | | | | | | Commit 21f4486faa5d ("armv8: update gd after relocate") sets x18 without checking the return value of spl_relocate_stack_gd(). Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: York Sun <york.sun@nxp.com> CC: Kever Yang <kever.yang@rock-chips.com> CC: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | Revert "sandbox: remove os_putc() and os_puts()"Simon Glass2017-12-071-0/+11
|/ | | | | | | | | | | | | While sandbox works OK without the special-case code, it does result in console output being stored in the pre-console buffer while sandbox starts up. If there is a crash or a problem then there is no indication of what is going on. For ease of debugging it seems better to revert this change. This reverts commit 47b98ad0f6779485d0f0c14f337c3eece273eb54. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-uniphierTom Rini2017-12-043-7/+4
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| * mtd: nand: Rename nand.h into rawnand.hMasahiro Yamada2017-12-042-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This header was renamed to rawnand.h in Linux. The following is the corresponding commit in Linux. commit d4092d76a4a4e57b65910899948a83cc8646c5a5 Author: Boris Brezillon <boris.brezillon@free-electrons.com> Date: Fri Aug 4 17:29:10 2017 +0200 mtd: nand: Rename nand.h into rawnand.h We are planning to share more code between different NAND based devices (SPI NAND, OneNAND and raw NANDs), but before doing that we need to move the existing include/linux/mtd/nand.h file into include/linux/mtd/rawnand.h so we can later create a nand.h header containing all common structure and function prototypes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: clean up board_initMasahiro Yamada2017-12-041-5/+2
| | | | | | | | | | | | | | | | Remove unnecessary DECLARE_GLOBAL_DATA_PTR and header includes. <common.h> has been replaced with <linux/errno.h> and <linux/printk.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | arm: Make gcc 6.0 or later a hard requirement now.Tom Rini2017-12-041-2/+2
| | | | | | | | | | | | | | Move the warning to an error as we have been promising would happen in this release. Signed-off-by: Tom Rini <trini@konsulko.com>
* | armv8: mmu: fix page table mappingPeng Fan2017-12-042-1/+5
| | | | | | | | | | | | | | | | | | To page mapping the lowest 2 bits needs to be 0x3. If not fix this, the final lowest 3 bits for page mapping is 0x1 which is marked as reserved. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm64 :show_regs: show the address before relocationPeng Fan2017-12-041-2/+8
| | | | | | | | | | | | | | | | | | | | After relocation, when error happends, it is hard to track ELR and LR with asm file objdumped from elf file. So subtract the gd->reloc_off the reflect the compliation address. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ARM: arch-meson: build memory banks using reported memory from registersNeil Armstrong2017-12-043-8/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As discussed at [1], the Amlogic Meson GX SoCs can embed a BL31 firmware and a secondary BL32 firmware. Since mid-2017, the reserved memory address of the BL31 firmware was moved and grown for security reasons. But mainline U-Boot and Linux has the old address and size fixed. These SoCs have a register interface to get the two firmware reserved memory start and sizes. This patch adds a dynamic reservation of the memory zones in the device tree bootmem reserved memory zone used by the kernel in early boot. To be complete, the memory zones are also added to the EFI reserved zones. Depends on patchset "Add support for Amlogic GXL Based SBCs" at [2]. [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-October/004860.html [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005410.html Changes since v1: - switched the #if to if(IS_ENABLED()) to compile all code paths - renamed function to meson_board_add_reserved_memory() - added a mem.h header with comment - updated all boards ft_board_setup() Changes since RFC v2: - reduced preprocessor load - kept Odroid-C2 static memory mapping as exception Changes since RFC v1: - switch to fdt rsv mem table and efi reserve memory - replaced in_le32 by readl() Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [trini: Fix warning on khadas-vim over missing <asm/arch/mem.h> Signed-off-by: Tom Rini <trini@konsulko.com>
* | arm: Add Khadas VIM support based on Meson GXL familyNeil Armstrong2017-12-043-1/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds platform code for the Khadas VIM board based on a Meson GXL (S905X) SoC with the Meson GXL configuration. This initial submission supports UART, MMC/SDCard and Ethernet with the Internal RMII PHY. The meson-gxl-s905x-khadas-vim.dts is synchronised from the linux 4.13 stable tree as of 4.13.8. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | arm: Add LibreTech CC support based on Meson GXL familyNeil Armstrong2017-12-043-1/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds platform code for the Libre Computer CC "Le Potato" board based on a Meson GXL (S905X) SoC with the Meson GXL configuration. This initial submission supports UART, MMC/SDCard and Ethernet with the Internal RMII PHY. The meson-gxl-s905x-libretech-cc.dts is synchronised from the linux 4.13 stable tree as of 4.13.8. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | ARM: arch-meson: add ethernet common init functionNeil Armstrong2017-12-043-1/+79
| | | | | | | | | | | | | | | | Introduce a generic common Ethernet Hardware init function common to all Amlogic GX SoCs with support for the Internal PHY enable for GXL SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | armv8: shrink exception table codeAndre Przywara2017-12-041-73/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the moment our exception entry code needs 34 instructions, so we can't use put it directly into the table entry, which offers "only" 32 instructions there. Right now we just put an unconditional branch there, then use a macro to place the 34 instructions *per entry* after that. That effectivly doubles the size of our exception table, which is quite a waste, given that we use it mostly for debugging purposes. Since the register saving part is actually identical, let's just convert that macro into a function, and "bl" into it directly from the exception slot, of course after having saved at least the original LR. This saves us about 950 bytes of code, which is quite a relief for some tight SPLs, in particular the 64-bit Allwinner ones. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | add support for Raspberry Pi Zero WDmitry Korunov2017-12-042-0/+42
| | | | | | | | Signed-off-by: Dmitry Korunov <dessel.k@gmail.com>
* | omap2: set the ethaddr as well as the usbethaddr env var to ensure static MACPeter Robinson2017-12-021-0/+3
|/ | | | | | | | | | The kernel gets the ethernet MAC from the ethaddr variable, the omap boards for devices with USB based eth adapters just set the usbethaddr which doesn't appear to get passed to the kernel. The same Raspberry Pi code sets both ethaddr and usbethaddr so lets do that so linux (tested 4.13 and 4.14) get a static rather than a random MAC address, while not regressing users of usbethaddr. Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
* rockchip: clk: rk3128: fix DCLK_VOP_DIV_CON_MASKPhilipp Tomsich2017-12-021-1/+1
| | | | | | | | The DCLK_VOP_DIV_CON_MASK should cover only bits 8 through 15. Fix this to remove an "integer-overflow on shifted constant" warning. Fixes: 9246d9e ("rockchip: rk3128: add clock driver") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: clk: rk3128: fix NANDC_PLL_SEL_MASKPhilipp Tomsich2017-12-021-1/+1
| | | | | | | | The PLL selector field for NANDC is only 2 bits wide. This fixes an 'int-overflow on shift' warning. Fixes: 9246d9e ("rockchip: rk3128: add clock driver") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: dts: rk3399-puma: add /config/sysreset-gpio propertyPhilipp Tomsich2017-11-301-0/+5
| | | | | | | | | | | | | | On the RK3399-Q7, we want to trigger a full platform reset (so the various software stacks supported don't have to deal with the same complexities over and over again) in case that anything other than a power-on reset occurred. To do so, this defines the /config/sysreset-gpio property and has it point to a GPIO that will perform a power-on reset of the entire platform. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
* rockchip: dts: rk3399-puma: add a 'tsd, usb-port-power' stringlist for USB1Philipp Tomsich2017-11-301-0/+1
| | | | | | | | | | | | | | | | USB1 is connected to the on-module USB 3.0 hub and power to the hub (actually it's a reset signal, modeled as a fixed regulator, that will be released) should be enabled only during the first probing of the device to avoid the hub from entering its low-power mode (where it tries to attach on a fixed interval, but we always miss the timeslot when U-Boot has the controller listening). This adds a 'tsd,usb-port-power' stringlist to enable the infrastructure in the board-specific usb_hub_reset_devices to find and control the fixed regulator associated with control of the USB hub. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
* rockchip: rk3036: sdram: correct setting for pll integer modeKever Yang2017-11-301-1/+1
| | | | | | | | | According to rk3036 TRM, should be set to '1' for the pll integer mode, while the '0' means the frac mode. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3036: update clock driver for ddrKever Yang2017-11-301-9/+6
| | | | | | | | | | After the MASK MACRO update, we need to update the driver at the same time. This is a fix to: 37943aa rockchip: rk3036: clean mask definition for cru reg Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3036: fix pll config for correct frequencyKever Yang2017-11-301-2/+3
| | | | | | | | | | There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy, so we need to double to pll output and then ddr can work in correct frequency. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3128: add evb-rk3128 supportKever Yang2017-11-301-0/+24
| | | | | | | | | | | | | | evb-rk3128 is an evb from Rockchip based on rk3128 SoC: - 2 USB2.0 Host port; - 1 HDMI port; - 2 10/100M eth port; - 2GB ddr; - 16GB eMMC; - UART to USB debug port; Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3128: add pinctrl driverKever Yang2017-11-301-0/+551
| | | | | | | | Add rk3128 pinctrl driver and grf/iomux structure definition. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3128: add clock driverKever Yang2017-11-303-0/+245
| | | | | | | | Add rk3128 clock driver and cru structure definition. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3128: add soc basic supportKever Yang2017-11-307-0/+180
| | | | | | | | | | RK3128 is a SoC from Rockchip with quad-core Cortex-A7 CPU and mali400 GPU. Support Nand flash, eMMC, SD card, USB 2.0 host and device, HDMI/LVDS/MIPI display. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* rockchip: rk3128: add device tree fileKever Yang2017-11-303-0/+900
| | | | | | | | | | | | | | Add dts binding header for rk3128, files origin from kernel. Series-Changes: 2 - fix i2c address - add saradc and usb phy node - emmc using fifo mode for there is no dma support in rk3128 emmc - add some clock id in cru.h Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-shTom Rini2017-11-3019-12522/+168
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| * ARM: rmobile: Rework the ULCB CPLD driverMarek Vasut2017-11-301-0/+9
| | | | | | | | | | | | | | | | Rework the ULCB CPLD driver and make it into a sysreset driver, since that is what the ULCB CPLD driver is mostly for. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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