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* x86: Enable multi-core init for Minnowboard MAXSimon Glass2015-04-301-0/+20
* x86: Add a CPU driver for baytrailSimon Glass2015-04-305-6/+227
* x86: Allow CPUs to be set up after relocationSimon Glass2015-04-303-0/+54
* x86: Add functions to set and clear bits on MSRsSimon Glass2015-04-301-0/+28
* x86: Add multi-processor initSimon Glass2015-04-3011-7/+934
* x86: Provide access to the IDTSimon Glass2015-04-292-0/+7
* x86: Store the GDT pointer in global_dataSimon Glass2015-04-292-0/+2
* x86: Add an mfence macroSimon Glass2015-04-291-0/+5
* x86: Add defines for fixed MTRRsSimon Glass2015-04-291-0/+14
* x86: Add atomic operationsSimon Glass2015-04-291-0/+115
* x86: Add support for the Simple Firmware Interface (SFI)Simon Glass2015-04-295-0/+311
* x86: Disable -WerrorSimon Glass2015-04-291-1/+1
* x86: Remove unwanted MMC debuggingSimon Glass2015-04-291-1/+0
* x86: fsp: Use reset_cpu()Simon Glass2015-04-291-7/+0
* x86: quark: Use reset_cpu()Simon Glass2015-04-291-1/+1
* x86: ivybridge: Use reset_cpu()Simon Glass2015-04-293-15/+6
* x86: Implement reset_cpu() correctly for modern CPUsSimon Glass2015-04-292-13/+28
* x86: link: Add PCH driver to support SPI FlashSimon Glass2015-04-292-1/+12
* x86: minnowmax: use the correct NOR in the configurationGabriel Huau2015-04-291-1/+1
* x86: Correct the typo in write_tables()Bin Meng2015-04-291-1/+1
* x86: Kconfig: Move DM_SPI & DM_SPI_FLASH to arch/KconfigBin Meng2015-04-291-6/+0
* x86: Kconfig: MARK_GRAPHICS_MEM_WRCOMB cosmeticsBin Meng2015-04-291-4/+4
* x86: Kconfig: Move platform options forwardBin Meng2015-04-291-10/+9
* x86: Kconfig: Divide the target selection to vendor/modelBin Meng2015-04-291-79/+13
* x86: quark: Turn on legacy segments decodeBin Meng2015-04-292-0/+19
* x86: Check PIRQ routing table sanity in the F segmentBin Meng2015-04-291-5/+13
* x86: minnowmax: add GPIO banks in the device treeGabriel Huau2015-04-291-0/+42
* x86: baytrail: fix the GPIOBASE addressGabriel Huau2015-04-291-1/+1
* x86: queensbay: Implement PIRQ routingBin Meng2015-04-297-4/+440
* x86: Support platform PIRQ routingBin Meng2015-04-294-0/+300
* x86: Write configuration tables in last_stage_init()Bin Meng2015-04-294-0/+90
* x86: Add a function to assign IRQ numbers to PCI deviceBin Meng2015-04-292-0/+35
* x86: Install a default e820 table in the __weak install_e820_map()Bin Meng2015-04-291-7/+22
* x86: Clean up arch/x86/include/asm/e820.hBin Meng2015-04-291-131/+2
* x86: Add alias for SPI node in the board dtsBin Meng2015-04-293-2/+11
* x86: Set serial port IRQ for SMSC LPC47MBin Meng2015-04-291-0/+3
* x86: queensbay: Avoid using PCH prefixBin Meng2015-04-292-4/+3
* x86: Remove the old VGA driverBin Meng2015-04-292-206/+0
* sandbox: Move CONFIG_SYS_VSNPRINTF to KconfigSimon Glass2015-04-181-0/+3
* Kconfig: Move CONFIG_BOOTSTAGE to KconfigSimon Glass2015-04-182-1/+10
* dm: select CONFIG_DM* optionsMasahiro Yamada2015-04-181-12/+0
* x86: chromebook_link: dts: Add PCH and LPC devicesSimon Glass2015-04-183-33/+52
* dm: x86: Add a uclass for an Low Pin Count (LPC) deviceSimon Glass2015-04-182-0/+29
* dm: x86: Add a uclass for a Platform Controller HubSimon Glass2015-04-183-9/+29
* dm: x86: spi: Convert ICH SPI driver to driver modelSimon Glass2015-04-185-20/+25
* dm: x86: pci: Convert chromebook_link to use driver model for pciSimon Glass2015-04-186-67/+59
* dm: x86: pci: Convert coreboot to use driver model for pciSimon Glass2015-04-182-47/+23
* dm: x86: pci: Add a PCI driver for driver modelSimon Glass2015-04-183-0/+50
* x86: Split up arch_cpu_init()Simon Glass2015-04-161-0/+8
* x86: Add a x86_ prefix to the x86-specific PCI functionsSimon Glass2015-04-1620-187/+191
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