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* x86: apl: Avoid accessing the PCI bus before it is probedSimon Glass2020-01-072-11/+29
| | | | | | | | The PCI bus is not actually probed by the time the ofdata_to_platdata() method is called since that happens in the uclass's post_probe() method. Update the PMC and P2SB drivers to access the bus in its probe() method. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add chromebook_coralSimon Glass2019-12-152-0/+832
| | | | | | | | | Add support for coral which is a range of Apollo Lake-based Chromebook released in 2017. This also includes reef released in 2016, since it is based on the same SoC. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add FSP supportSimon Glass2019-12-153-0/+877
| | | | | | | | The memory and silicon init parts of the FSP need support code to work. Add this for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add FSP structuresSimon Glass2019-12-154-0/+440
| | | | | | | | These are mostly specific to a particular SoC. Add the definitions for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add Kconfig and MakefileSimon Glass2019-12-153-0/+98
| | | | | | | Add basic plumbing to allow Apollo Lake support to be used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add P2SB driverSimon Glass2019-12-152-0/+167
| | | | | | | | Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add SPL/TPL initSimon Glass2019-12-152-0/+272
| | | | | | | | Add code to init the system both in TPL and SPL. Each phase has its own procedure. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add a CPU driverSimon Glass2019-12-155-0/+81
| | | | | | | Add a bare-bones CPU driver so that CPUs can be probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add SPL loadersSimon Glass2019-12-152-0/+180
| | | | | | | | Add loaders for SPL and TPL so that the next stage can be loaded from memory-mapped SPI or, failing that, the Fast SPI driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add PUNIT driverSimon Glass2019-12-152-0/+97
| | | | | | | | Add a driver for the Apollo Lake P-unit (power unit). It is modelled as a syscon driver since it only needs to be probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add PCH driverSimon Glass2019-12-153-0/+46
| | | | | | | | Add a driver for the Apollo Lake Platform Controller Hub. It does not have any functionality and is just a placeholder for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add LPC driverSimon Glass2019-12-153-0/+205
| | | | | | | | | This driver the LPC and provides a few functions to set up LPC features. These should probably use ioctls() or perhaps, better, have specific uclass methods. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add ITSS driverSimon Glass2019-12-153-0/+258
| | | | | | | | | This driver models some sort of interrupt thingy but there are so many abreviations that I cannot find out what it stands for. Possibly something to do with interrupts. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add hostbridge driverSimon Glass2019-12-152-0/+180
| | | | | | | | This driver models the hostbridge as a northbridge. It simply sets up the graphics BAR. It supports of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add systemagent driverSimon Glass2019-12-153-0/+62
| | | | | | | | This driver handles communication with the systemagent which needs to be told when U-Boot has completed its init. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add pinctrl driverSimon Glass2019-12-151-0/+485
| | | | | | | | Add a driver for the Apollo Lake pinctrl. This mostly makes use of the common Intel pinctrl support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add UART driverSimon Glass2019-12-153-0/+154
| | | | | | | | | Add a driver for the Apollo Lake UART. It uses the standard ns16550 device but also sets up the input clock with LPSS and supports configuration via of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add PMC driverSimon Glass2019-12-153-0/+240
| | | | | | | | Add a driver for the Apollo Lake SoC. It supports the basic operations and can use device tree or of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add basic IO addressesSimon Glass2019-12-151-0/+29
| | | | | | | | Add some fixed IO and mmap addresses for use in the device tree and with some early-init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move qemu CPU fixup function into its own fileSimon Glass2019-12-153-68/+79
| | | | | | | | | | | This function is specific to qemu so it seems best to keep it separate from the generic code. Move it out to a new file and update the condition to use if() instead of #ifdef Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a generic Intel pinctrl driverSimon Glass2019-12-152-0/+679
| | | | | | | | | | | | | | | Recent Intel SoCs share a pinctrl mechanism with many common elements. Add an implementation of this core functionality, allowing SoC-specific drivers to avoid adding common code. As well as a pinctrl driver this provides a GPIO driver based on the same code. Once other SoCs use this driver we may consider moving more properties to the device tree (e.g. the community info and pad definitions). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add low-power subsystem (lpss) supportSimon Glass2019-12-153-0/+81
| | | | | | | | | This subsystem is present on various Intel SoCs. Add very basic support for taking an lpss device out of reset. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Make MSR_PKG_POWER_SKU commonSimon Glass2019-12-153-3/+8
| | | | | | | | This is used on several boards so add it to the common file. Also add a useful power-limit value while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Separate out U-Boot and device tree in ROM imageSimon Glass2019-12-151-3/+11
| | | | | | | | | | | | | | | | | | At present binman does not support updating a device tree that is part of U-Boot (i.e u-boot.bin). Separate the entries into two so that we can get updated entry information. This makes binman_entry_find() work correctly. Do the same for SPL tool. In both cases, group the two parts into a section so that SPL symbols get the correct total size. It may be possible for binman to handle this automatically at some point, by ignoring u-boot.bin and always creating it from u-boot-nodtb.bin and u-boot.dtb Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Don't repeat microcode in U-Boot if not neededSimon Glass2019-12-151-0/+7
| | | | | | | | | At present if SPL sets up the microcode then it is still included in U-Boot as well. This is wasteful as microcode is large. Adjust the logic in the image to prevent this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add an fdtmap and image-headerSimon Glass2019-12-151-0/+5
| | | | | | | | | Add these entries to the ROM so that we can list the contents of an image with 'binman ls'. The image-header is not essential but does speed up access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add an option to control the position of SPLSimon Glass2019-12-152-2/+7
| | | | | | | | | | | For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different location from where SPL must be placed in ROM. In other words, although SPL runs before SDRAM is set up, it is not execute-in-place (XIP). Add a Kconfig option for the ROM position. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add an option to control the position of U-BootSimon Glass2019-12-152-15/+8
| | | | | | | | | | | | The existing work-around for positioning U-Boot in the ROM when it actually runs from RAM still exists and there is not obvious way to change this. Add a proper Kconfig option to handle this case. This also adds a new bool property to indicate whether CONFIG_SYS_TEXT_BASE exists. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update .dtsi file for FSP2Simon Glass2019-12-151-1/+31
| | | | | | | | | | Include the IFWI section and the FSP-M binary. The FSP-T binary is not currently used, as CAR is set up manually. Also drop the FSP binary as this relates only to FSP1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Disable microcode section for FSP2Simon Glass2019-12-152-0/+11
| | | | | | | | | At present we don't support loading microcode with FSP2. The correct way to do this is by adding it to the FIT. For now, disable including microcode in the image. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add support for newer CAR schemesSimon Glass2019-12-155-7/+564
| | | | | | | | | | | Newer Intel SoCs have different ways of setting up cache-as-ram (CAR). Add support for these along with suitable configuration options. To make the code cleaner, adjust a few definitions in processor.h so that they can be used from assembler. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add an option to include a FITSimon Glass2019-12-152-0/+14
| | | | | | | | | | | Many Intel SoCs require a FIT in order to boot properly. Add an option to include this and enable it by default. This term can be confused with FIT (Flat Image Tree) in U-Boot so the CONFIG option has to include 'X86'. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Don't include the BIOS emulator in TPLSimon Glass2019-12-151-0/+2
| | | | | | | | We don't generally have enough space to run this, so don't build it into TPL. This helps reduce the size of TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Make the notify API call commonSimon Glass2019-12-152-18/+27
| | | | | | | | The fsp_notify() API is the same for FSP1 and FSP2. Move it into a new common API file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Allow remembering the location of FSP-SSimon Glass2019-12-151-0/+3
| | | | | | | | FSP-S is used by the notify call after it has been used for silicon init. To avoid having to load it again, add a field to store the location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Set up an MTRR for the graphics frame bufferSimon Glass2019-12-151-0/+4
| | | | | | | | | | | The FSP-S may do this but at least for coral it does not. Set this up so that graphics is not deathly slow. It isn't clear whether the FSP is expected to set up MTRR. It is not mentioned in the APL FSP document. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Add FSP2 base supportSimon Glass2019-12-1510-2/+784
| | | | | | | | | | | | | Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Correct wrong header inlude in fsp_support.cSimon Glass2019-12-151-1/+1
| | | | | | | | This generic FSP file should include the generic FSP support header, not the FSP1 version. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Make graphics support common to FSP1/2Simon Glass2019-12-153-2/+4
| | | | | | | | Both versions of FSP can use the same graphics support, so move it into the common directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow interrupt to happen onceSimon Glass2019-12-153-9/+11
| | | | | | | | At present the interrupt table is included in all phases of U-Boot. Allow it to be omitted, e.g. in TPL, to reduce size. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Set up the MTRR for SDRAMSimon Glass2019-12-151-0/+5
| | | | | | | Set up MTRRs for the FSP SDRAM regions to improve performance. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Set the DRAM banks to reflect real locationSimon Glass2019-12-151-1/+29
| | | | | | | | | | | | | At present with fsp a single DRAM bank is added which extends to the whole size of memory. However there is typically only 2GB of memory available below the 4GB boundary, and this is what is used by U-Boot while running in 32-bit mode. Scan the tables to set the banks correct. The first bank is set to memory below 4GB, and the rest of memory is put into subsequent banks. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move fsp_prepare_mrc_cache() to fsp1 directorySimon Glass2019-12-153-27/+20
| | | | | | | | | This function needs to be different for FSP2, so move the existing function into the fsp1 directory. Since it is only called from one file, drop it from the header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Don't export mrccache_update()Simon Glass2019-12-152-17/+14
| | | | | | | This function is only used within the implementation so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add mrccache support for a 'variable' cacheSimon Glass2019-12-152-1/+3
| | | | | | | Add support for a second cache type, for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update mrccache to support multiple cachesSimon Glass2019-12-158-48/+106
| | | | | | | | | | | With Apollo Lake we need to support a normal cache, which almost never changes and a much smaller 'variable' cache which changes every time. Update the code to add a cache type, use an array for the caches and use a for loop to iterate over the caches. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Tidy up error handling in mrccache_save()Simon Glass2019-12-151-12/+7
| | | | | | | | | | | This function is a bit confusing at present due to the error handling. Update it to remove the goto, returning errors as they happen. While we are here, use hex for the data size since this is the norm in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a new global_data member for the cache recordSimon Glass2019-12-152-6/+7
| | | | | | | | | | | At present we reuse the mrc_output char * to also point to the cache record after it has been set up. This is confusing and doesn't save much data space. Add a new mrc_cache member instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Adjust mrccache_get_region() to support get_mmap()Simon Glass2019-12-151-4/+14
| | | | | | | | | It is now possible to obtain the memory map for a SPI controllers instead of having it hard-coded in the device tree. Update the code to support this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Adjust mrccache_get_region() to use livetreeSimon Glass2019-12-151-29/+26
| | | | | | | | | Change the algorithm to first find the flash device then read the properties using the livetree API. With this change the device is not probed so this needs to be done in mrccache_save(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2024-10-04 05:23:05 +0000