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* x86: coral: Allow init of debug UART in U-Boot properSimon Glass2021-03-271-0/+1
| | | | | | | | | | | At present the debug UART is only set up in SPL, on the assumption that the boot flow will always pass through there. When booting from coreboot, SPL is not used, so the debug UART is not available. Move the code into a common place so that it can be used in U-Boot proper also. Add the required init to start_from_spl.S as well. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop asm/global_data.h from common headerSimon Glass2021-02-021-0/+3
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* x86: coral: Support TPM and RTC in SPLSimon Glass2021-01-301-0/+3
| | | | | | | | Update the devicetree so that the TPM and RTC can be used in SPL. Also enable the pins used for getting the memory configuration settings while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Adjust how the UART gets its platform dataSimon Glass2021-01-051-1/+18
| | | | | | | | | | | | At present this driver calls malloc() to start a new platform data structure, fills it in and tells driver model to use it. We want to avoid malloc, particularly with the new version of of-platdata. Create a new struct which encompasses both the dtd struct and the ns16550 one, to avoid this. Unfortunately we must copy the data into the right place for the ns16550 driver. Add some comments about this. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Move priv/plat structs to headersSimon Glass2021-01-053-0/+62
| | | | | | | With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Add core init for the SoCSimon Glass2020-11-051-0/+14
| | | | | | | | Set up MSRs required for Apollo Lake. This enables Linux to use the timers correctly. Also write the fixed MSRs for this platform. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Generate required ACPI tablesSimon Glass2020-09-251-0/+18
| | | | | | | Add support for generating various ACPI tables for Apollo Lake. Add a few S3 definitions that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Allow reading hostbridge base addressesSimon Glass2020-09-251-0/+31
| | | | | | | Add a few functions to permit reading of various useful base addresses provided by the hostbridge. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Update iomap for ACPISimon Glass2020-09-251-0/+16
| | | | | | | Add some more definitions to the iomap. These will be used by ACPI-generation code as well as the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Add power-management definitionsSimon Glass2020-09-251-1/+39
| | | | | | | | | Add SCI and power-state definitions required by ACPI tables. Fix the license to match the original source file. Als update the guard on acpi_pmc.h to avoid an error when buiding ASL. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add wake sources for the acpi_gpe driverSimon Glass2020-09-252-0/+138
| | | | | | | | | | Some devices can wake the system from sleep, e.g opening the lid on a clamshell or moving a USB mouse. Add a wake to specify this for USB devices and add the settings for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a common global NVS structureSimon Glass2020-09-251-22/+1
| | | | | | | | | Add the definition of this structure common to Intel devices. It includes some optional Chrome OS pieces which are used when vboot is integrated. Drop the APL version as it is basically the same. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: acpi: apl: Add asl files for Apollo LakeSimon Glass2020-09-2518-0/+1261
| | | | | | Add Apollo Lake ASL files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
* arch: x86: apl: Update FSP parametersBernhard Messerklinger2020-08-032-2/+12
| | | | | | | | Add missing parameters to support full configuration of the latest FSP MR6 release. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: apl: fsp_bindings: Add support for u64 parametersBernhard Messerklinger2020-08-031-0/+1
| | | | | | | | Add FSP_UINT64 read support as preparation for FSP-M and FSP-S parameter update. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: apl: Add hex offsets for registers in FSP-SSimon Glass2020-06-021-0/+72
| | | | | | | | | | | When comparing hex dumps it is useful to see the offsets of the registers. Add them in where they correspond to a multiple of 16. Possibly it would be useful to have a a command to output the FSP values in human-readable form, making use of the fsp_bindings implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add hex offsets for registers in FSP-MSimon Glass2020-06-021-2/+15
| | | | | | | | | | | When comparing hex dumps it is useful to see the offsets of the registers. Add them in where they correspond to a multiple of 16. Possibly it would be useful to have a a command to output the FSP values in human-readable form, making use of the fsp_bindings implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Use devicetree for FSP-S configurationBernhard Messerklinger2020-05-272-0/+216
| | | | | | | | | | | | | | | A the moment the FSP-S configuration is a mix of hard coded values and devicetree properties. This patch makes FSP-S full configurable from devicetree by adding binding properties for all FSP-S parameters. Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral) Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Use devicetree for FSP-M configurationBernhard Messerklinger2020-05-272-0/+264
| | | | | | | | | | | | | | | | | | A the moment the FSP-M configuration is a mix of hard coded values and devicetree properties. This patch makes FSP-M full configurable from devicetree by adding binding properties for all FSP-M parameters. Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral) [sjg: Fix a build error for coral] Signed-off-by: Simon Glass <sjg@chromium.org> [bmeng: Add __maybe_unused to fsp_update_config_from_dtb()] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-182-0/+2
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Add Global NVS table headerSimon Glass2020-04-161-0/+36
| | | | | | | | Add the C version of this header. It includes a few Chrome OS bits which are disabled for a normal build. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolgang.wallner@br-automation.com>
* x86: Move itss.h from Apollo Lake to the generic x86 include directoryWolfgang Wallner2020-02-041-45/+0
| | | | | | | | | | | | | The code in this file is not specific to Apollo Lake. According to coreboot sources (where this code comes from), it is common to at least: * Apollo Lake * Cannon Lake * Ice Lake * Skylake Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add the term "Interrupt Timer Subsystem" to ITSS filesWolfgang Wallner2020-02-041-0/+2
| | | | | | | | | ITSS stands for "Interrupt Timer Subsystem", so add that term to the description of the relevant files. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add FSP structuresSimon Glass2019-12-154-0/+440
| | | | | | | | These are mostly specific to a particular SoC. Add the definitions for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add a CPU driverSimon Glass2019-12-151-0/+20
| | | | | | | Add a bare-bones CPU driver so that CPUs can be probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add PCH driverSimon Glass2019-12-151-0/+9
| | | | | | | | Add a driver for the Apollo Lake Platform Controller Hub. It does not have any functionality and is just a placeholder for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add LPC driverSimon Glass2019-12-151-0/+82
| | | | | | | | | This driver the LPC and provides a few functions to set up LPC features. These should probably use ioctls() or perhaps, better, have specific uclass methods. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add ITSS driverSimon Glass2019-12-151-0/+43
| | | | | | | | | This driver models some sort of interrupt thingy but there are so many abreviations that I cannot find out what it stands for. Possibly something to do with interrupts. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add systemagent driverSimon Glass2019-12-151-0/+37
| | | | | | | | This driver handles communication with the systemagent which needs to be told when U-Boot has completed its init. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add pinctrl driverSimon Glass2019-12-151-0/+485
| | | | | | | | Add a driver for the Apollo Lake pinctrl. This mostly makes use of the common Intel pinctrl support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add UART driverSimon Glass2019-12-151-0/+20
| | | | | | | | | Add a driver for the Apollo Lake UART. It uses the standard ns16550 device but also sets up the input clock with LPSS and supports configuration via of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add PMC driverSimon Glass2019-12-151-0/+19
| | | | | | | | Add a driver for the Apollo Lake SoC. It supports the basic operations and can use device tree or of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add basic IO addressesSimon Glass2019-12-151-0/+29
Add some fixed IO and mmap addresses for use in the device tree and with some early-init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2025-09-02 21:31:38 +0000