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* riscv: Add Microchip MPFS Icicle board supportPadmarao Begari2019-06-051-0/+4
| | | | | | | | | | | This patch adds Microchip MPFS Icicle board support. For now, NS16550 serial driver is only enabled. The Microchip MPFS Icicle defconfig by default builds U-Boot for M-Mode with SMP support. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner2019-05-182-4/+18
| | | | | | | | | | | | | While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com>
* CONFIG_SYS_[DI]CACHE_OFF: convert to KconfigTrevor Woerner2019-05-181-0/+12
| | | | | | | | | | | | | | | | | | | | CONFIG_SYS_[DI]CACHE_OFF had been partially converted to Kconfig parameters; only for the ARC architecture. This patch turns these two parameters into Kconfig items everywhere else they are found. All of the include/configs/* and defconfig changes in this patch are for arm machines only. The Kconfig changes for arc, nds32, riscv, and xtensa have been included since these symbols are found in code under arch/{arc,nds32,riscv,xtensa}, however, no currently-defined include/configs/* or defconfigs for these architectures exist which include these symbols. These results have been confirmed with tools/moveconfig.py. Acked-by: Alexey Brodkin <abrodkin@snopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Re-migrate for a few more boards] Signed-off-by: Tom Rini <trini@konsulko.com>
* RISCV: image: Add booti supportAtish Patra2019-05-092-0/+56
| | | | | | | | | | | | | | | | | | This patch adds booti support for RISC-V Linux kernel. The existing bootm method will also continue to work as it is. It depends on the following kernel patch which adds the header to the flat Image. Gzip compressed Image (Image.gz) support is not enabled with this patch. https://patchwork.kernel.org/patch/10925543/ Tested on HiFive Unleashed and QEMU. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Karsten Merker <merker@debian.org> Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
* riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ↵Rick Chen2019-05-092-0/+4
| | | | | | | | | | | | | | | enabled This patch will fix prior_stage_fdt_address write failure problem, when AE350 boots from flash. When AE350 boots from flash, prior_stage_fdt_address will be flash address, we shall avoid it to be written. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: Introduce CONFIG_XIP to support booting from flashRick Chen2019-05-096-0/+21
| | | | | | | | | | | | | When U-Boot boots from flash, during the boot process, hart_lottery and available_harts_lock variable addresses point to flash which is not writable. This causes boot failures on AE350. Introduce a config option CONFIG_XIP to support such configuration. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dts: switch spi-flash to jedec, spi-nor compatibleNeil Armstrong2019-04-122-2/+2
| | | | | | | | | | | | | | | | | | | | There is no reason not to use the Linux "jedec,spi-nor" binding in U-Boot dts files. This compatible has been added in sf_probe, let use it. This patch switches to jedec,spi-nor when spi-flash is used in the DTS and DTSI files, and removed spi-flash when jedec,spi-nor is already present. The x86 dts are switched in a separate commit since it depends on a change in fdtdec. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Evgeniy Paltsev <paltsev@synopsys.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Patrick Delaunay <Patrick.delaunay@st.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failureRick Chen2019-04-081-0/+2
| | | | | | | | | | | | | | It occurs since commit 27cb7300ffda ("Ensure device tree DTS is compiled"). More details can refer to 89c2b5c02049aea746b1edee0b4e1d8519dec2f4 ARM: fix arch/arm/dts/Makefile Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: dts: ae350 support SMPRick Chen2019-04-082-44/+118
| | | | | | | Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: ax25: Andes specific cache shall only support in M-modeRick Chen2019-04-081-0/+1
| | | | | | | | | | Limit the cache configuration only can be supported in M mode. It can not be manipulated in S mode. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: ax25: Add platform-specific Kconfig optionsRick Chen2019-04-081-0/+6
| | | | | | | | | | | Add ax25 RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Also disable ATCPIT100 SoC timer and replace by PLMT. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: Add a SYSCON driver for Andestech's PLMTRick Chen2019-04-085-0/+67
| | | | | | | | | | | | | | The platform-Level Machine Timer (PLMT) block holds memory-mapped mtime register associated with timer tick. This driver implements the riscv_get_time() which is required by the generic RISC-V timer driver. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: Add a SYSCON driver for Andestech's PLICRick Chen2019-04-085-2/+127
| | | | | | | | | | | | The Platform-Level Interrupt Controller (PLIC) block holds memory-mapped claim and pending registers associated with software interrupt. It is required for handling IPI. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: hang if relocation of secondary harts failsLukas Auer2019-04-081-1/+12
| | | | | | | | | | Print an error message and hang if smp_call_function() returns an error, indicating that relocation of the secondary harts has failed. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
* riscv: do not rely on hart ID passed by previous boot stageLukas Auer2019-04-081-0/+4
| | | | | | | | | | | | | | | | | | | RISC-V U-Boot expects the hart ID to be passed to it via register a0 by the previous boot stage. Machine mode firmware such as BBL and OpenSBI do this when starting their payload (U-Boot) in supervisor mode. If U-Boot is running in machine mode, this task must be handled by the boot ROM. Explicitly populate register a0 with the hart ID from the mhartid CSR to avoid possible problems on RISC-V processors with a boot ROM that does not handle this task. Suggested-by: Rick Chen <rick@andestech.com> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Rick Chen <rick@andestech.com>
* riscv: boot images passed to bootm on all hartsLukas Auer2019-04-081-1/+12
| | | | | | | Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: add support for multi-hart systemsLukas Auer2019-04-085-2/+147
| | | | | | | | | | | | | | | | | | On RISC-V, all harts boot independently. To be able to run on a multi-hart system, U-Boot must be extended with the functionality to manage all harts in the system. All harts entering U-Boot are registered in the available_harts mask stored in global data. A hart lottery system as used in the Linux kernel selects the hart U-Boot runs on. All other harts are halted. U-Boot can delegate functions to them using smp_call_function(). Every hart has a valid pointer to the global data structure and a 8KiB stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: save hart ID in register tp instead of s0Lukas Auer2019-04-081-2/+2
| | | | | | | | | | | | | The hart ID passed by the previous boot stage is currently stored in register s0. If we divert the control flow inside a function, which is required as part of multi-hart support, the function epilog may not be called, clobbering register s0. Save the hart ID in the unallocatable register tp instead to protect the hart ID. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
* riscv: delay initialization of caches and debug UARTLukas Auer2019-04-081-8/+8
| | | | | | | | | | | | Move the initialization of the caches and the debug UART until after board_init_f_init_reserve. This is in preparation for SMP support, where code prior to this point will be executed by all harts. This ensures that initialization will only be performed once on the main hart running U-Boot. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: implement IPI platform functions using SBILukas Auer2019-04-083-0/+31
| | | | | | | | | | | | | | | | The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: import the supervisor binary interface header fileLukas Auer2019-04-081-0/+94
| | | | | | | | | | | Import the supervisor binary interface (SBI) header file from Linux (arch/riscv/include/asm/sbi.h). The last change to it was in commit 6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI"). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
* riscv: add infrastructure for calling functions on other hartsLukas Auer2019-04-085-0/+197
| | | | | | | | | | | | | | | | | | | | | | | | Harts on RISC-V boot independently, U-Boot is responsible for managing them. Functions are called on other harts with smp_call_function(), which sends inter-processor interrupts (IPIs) to all other available harts. Available harts are those marked as available in the device tree and present in the available_harts mask stored in global data. The available_harts mask is used to register all harts that have entered U-Boot. Functions are specified with their address and two function arguments (argument 2 and 3). The first function argument is always the hart ID of the hart calling the function. On the other harts, the IPI interrupt handler handle_ipi() must be called on software interrupts to handle the request and call the specified function. Functions are stored in the ipi_data data structure. Every hart has its own data structure in global data. While this is not required at the moment (all harts are expected to boot Linux), this does allow future expansion, where other harts may be used for monitoring or other tasks. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrdAnup Patel2019-02-271-0/+1
| | | | | | | | | | | | This patch enables CONFIG_SYS_BOOT_RAMDISK_HIGH for RISC-V because bootm will update initrd location in DTB only if CONFIG_SYS_BOOT_RAMDISK_HIGH is enabled. If we don't enable this option then bootm assumes DTB already has initrd details which is not the case most of the time. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: Add SiFive FU540 board supportAnup Patel2019-02-271-0/+4
| | | | | | | | | | | | | | This patch adds SiFive FU540 board support. For now, only SiFive serial, SiFive PRCI, and Cadance MACB drivers are only enabled. The SiFive FU540 defconfig by default builds U-Boot for S-Mode because U-Boot on SiFive FU540 will run in S-Mode as payload of BBL or OpenSBI. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systemsAnup Patel2019-02-271-0/+20
| | | | | | | | | | | | | | | | | | | | | On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot DMA mapping APIs will generate DMA addresses beyond 4GB. This breaks DMA programming in 32bit DMA capable devices (such as Cadence MACB ethernet). For example, If DRAM is more then 2GB on QEMU sifive_u machine then Cadence MACB ethernet stops working for U-Boot because it is a 32bit DMA capable device. To handle 32bit DMA capable devices on 64bit systems, we provide custom implementation of board_get_usable_ram_top() which ensures that usable ram top is not more then 4GB. This in-turn ensures that U-Boot always runs within 4GB hence DMA addresses generated by DMA mapping APIs will be within 4GB too. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: Add place-holder asm/arch/clk.h for driver compilationAnup Patel2019-02-271-0/+14
| | | | | | | | | Some of the drivers (such as Cadence MACB ethernet driver) expect asm/arch/clk.h to be provided by arch support so we add place-holder asm/arch-generic/clk.h for RISC-V generic CPU. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: Add asm/dma-mapping.h for DMA mappingsAnup Patel2019-02-271-0/+38
| | | | | | | | | | | This patch adds asm/dma-mapping.h for Linux-like DMA mappings APIs required by some of the drivers (such as, Cadance MACB Ethernet driver). Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: Rename cpu/qemu to cpu/genericAnup Patel2019-02-275-2/+2
| | | | | | | | | | | | | | | | | | The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: qemu: define standalone load addressLukas Auer2019-01-151-1/+1
| | | | | | | | | | | | | We need to define the standalone load address to use standalone application on qemu-riscv. Define it and set it equal to CONFIG_SYS_LOAD_ADDR. To not overwrite it, change the assigned of CONFIG_STANDALONE_LOAD_ADDR in arch/riscv/config.mk to a conditional one. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: remove RISC-V standalone linker scriptLukas Auer2019-01-151-1/+0
| | | | | | | | | | Standalone applications do not require a separate linker script and can use the default linker script of the compiler instead. Remove the RISC-V standalone linker script. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: use invalidate/flush_*cache_range functions in cache.cLukas Auer2019-01-151-2/+2
| | | | | | | | | | | | | | | The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: move the AX25-specific implementation of flush_dcache_allLukas Auer2019-01-152-6/+26
| | | | | | | | | | | | | | | | | The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: clarify error message on undefined exceptionsLukas Auer2019-01-151-1/+2
| | | | | | | | | | Undefined exceptions are treated as reserved. This is not clearly communicated to the user. Adjust the error message to clarify that a reserved exception has occurred and add additional details. Fixes: e8b522b ("riscv: treat undefined exception codes as reserved") Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: bootm: Support booting VxWorksBin Meng2018-12-311-1/+7
| | | | | | | Register the 'bootm' function for booting VxWorks kernel for RISC-V architecture. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: Remove ae350.dtsBin Meng2018-12-181-229/+0
| | | | | | | | This is not used by any board. Remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: bootm: Change to use boot_hart from global dataBin Meng2018-12-181-1/+1
| | | | | | | | | | | | Avoid reading mhartid CSR directly, instead use the one we saved in the global data structure before. With this patch, BBL no longer needs to be hacked to provide the mhartid CSR emulation for S-mode U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: Save boot hart id to the global dataBin Meng2018-12-183-0/+24
| | | | | | | | | | At present the hart id passed via a0 in the U-Boot entry is saved to s0 at the beginning but does not preserve later. Save it to the global data structure so that it can be used later. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: Adjust the _exit_trap() position to come before handle_trap()Bin Meng2018-12-181-32/+30
| | | | | | | | With this change, we can avoid a forward declaration. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: Return to previous privilege level after trap handlingBin Meng2018-12-181-8/+0
| | | | | | | | | At present the trap handler returns to hardcoded M-mode/S-mode. Change to returning to previous privilege level instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: Fix context restore before returning from trap handlerBin Meng2018-12-181-1/+1
| | | | | | | | sp cannot be loaded before restoring other registers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: Move trap handler codes to mtrap.SBin Meng2018-12-183-90/+112
| | | | | | | | | Currently the M-mode trap handler codes are in start.S. For future extension, move them to a separate file mtrap.S. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: Do some basic architecture level cpu initializationBin Meng2018-12-181-1/+26
| | | | | | | | | In arch_cpu_init_dm() do some basic architecture level cpu initialization, like FPU enable, etc. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: Add indirect stringification to csr_xxx opsBin Meng2018-12-181-7/+9
| | | | | | | | | | With current csr_xxx ops, we cannot pass a macro to parameter 'csr', hence we need add another level to allow the parameter to be a macro itself, aka indirect stringification. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: Update supports_extension() to use desc from cpu driverBin Meng2018-12-181-0/+26
| | | | | | | | | | This updates supports_extension() implementation to use the desc string from the cpu driver whenever possible, which avoids the reading of misa CSR for S-mode U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: Add exception codes for xcause registerBin Meng2018-12-181-0/+15
| | | | | | | | This adds all exception codes in encoding.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: Add CSR numbersBin Meng2018-12-181-0/+221
| | | | | | | | | | The standard RISC-V ISA sets aside a 12-bit encoding space for up to 4096 CSRs. This adds all known CSR numbers as defined in the RISC-V Privileged Architecture Version 1.10. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: Remove non-DM version of print_cpuinfo()Bin Meng2018-12-181-37/+0
| | | | | | | | | With DM CPU driver, the non-DM version of print_cpuinfo() is no longer needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: Probe cpus during bootBin Meng2018-12-182-0/+27
| | | | | | | | This calls cpu_probe_all() to probe all available cpus. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: Enlarge the default SYS_MALLOC_F_LENBin Meng2018-12-181-0/+3
| | | | | | | | | Increase the heap size for the pre-relocation stage, so that CPU driver can be loaded. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: qemu: Add platform-specific Kconfig optionsBin Meng2018-12-182-0/+12
| | | | | | | | | Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
generated by cgit (git 2.34.1) at 2024-11-18 07:20:20 +0000