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* RISCV: image: Add booti supportAtish Patra2019-05-092-0/+56
* riscv: Introduce CONFIG_XIP to support booting from flashRick Chen2019-05-092-0/+4
* riscv: Add a SYSCON driver for Andestech's PLMTRick Chen2019-04-082-0/+54
* riscv: Add a SYSCON driver for Andestech's PLICRick Chen2019-04-082-0/+114
* riscv: boot images passed to bootm on all hartsLukas Auer2019-04-081-1/+12
* riscv: add support for multi-hart systemsLukas Auer2019-04-081-0/+1
* riscv: implement IPI platform functions using SBILukas Auer2019-04-082-0/+26
* riscv: add infrastructure for calling functions on other hartsLukas Auer2019-04-082-0/+119
* riscv: use invalidate/flush_*cache_range functions in cache.cLukas Auer2019-01-151-2/+2
* riscv: move the AX25-specific implementation of flush_dcache_allLukas Auer2019-01-151-6/+4
* riscv: clarify error message on undefined exceptionsLukas Auer2019-01-151-1/+2
* riscv: bootm: Support booting VxWorksBin Meng2018-12-311-1/+7
* riscv: bootm: Change to use boot_hart from global dataBin Meng2018-12-181-1/+1
* riscv: Save boot hart id to the global dataBin Meng2018-12-181-0/+19
* riscv: Adjust the _exit_trap() position to come before handle_trap()Bin Meng2018-12-181-32/+30
* riscv: Implement riscv_get_time() API using rdtime instructionAnup Patel2018-12-182-0/+39
* riscv: Add a SYSCON driver for SiFive's Core Local InterruptorBin Meng2018-12-182-0/+85
* riscv: Add kconfig option to run U-Boot in S-modeAnup Patel2018-12-051-9/+22
* riscv: efi: Generate Microsoft PE format compliant imagesBin Meng2018-12-021-6/+6
* riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen2018-11-261-9/+23
* riscv: align bootm implementation with that of other architecturesLukas Auer2018-11-261-27/+70
* riscv: implement the invalidate_icache_* functionsLukas Auer2018-11-261-0/+10
* riscv: hang on unhandled exceptionsLukas Auer2018-11-261-0/+2
* riscv: treat undefined exception codes as reservedLukas Auer2018-11-261-2/+6
* riscv: complete the list of exception codesLukas Auer2018-11-261-1/+12
* riscv: fix use of incorrectly sized variablesLukas Auer2018-11-261-5/+5
* riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64ILukas Auer2018-11-261-1/+1
* riscv: bootm: Add dm_remove_devices_flags() call to do_bootm_linux()Bin Meng2018-11-141-1/+10
* riscv: cosmetic: Reword do_reset() printf message.Rick Chen2018-10-031-1/+1
* riscv: Move do_reset() to a common placeBin Meng2018-10-032-0/+18
* riscv: bootm: Pass mhartid CSR value to kernelBin Meng2018-10-031-2/+3
* riscv: bootm: Correct the 1st kernel argument to hart idBin Meng2018-10-031-13/+5
* riscv: Remove setup.hBin Meng2018-10-031-1/+0
* riscv: Remove unused _relocate argumentsIvan Gorinov2018-07-191-2/+1
* SPDX: Convert single license tags to Linux Kernel styleRick Chen2018-05-295-4/+5
* riscv: Add board_quiesce_devices stubAlexander Graf2018-05-291-0/+4
* riscv: Add EFI application infrastructureAlexander Graf2018-05-295-0/+400
* riscv: Add setjmp/longjmp codeAlexander Graf2018-05-292-0/+67
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-075-11/+5
* Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini2018-04-271-2/+0
* riscv: bootm: Remove ATAGSRick Chen2018-03-301-177/+2
* riscv: bootm: Support to boot riscv-linuxRick Chen2018-03-301-4/+4
* riscv: checkpatch: Fix static const char * array declarationsRick Chen2018-03-301-1/+1
* riscv: checkpatch: Fix missing a blank line after declarationsRick Chen2018-03-301-2/+2
* riscv: nx25: lib: Add relative lib funcs to support RISC-VRick Chen2018-01-125-0/+407
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