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* dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass2020-12-131-1/+1
| | | | | | | Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
* riscv: sifive/fu540: spl: Rename soc_spl_init()Bin Meng2020-08-141-1/+1
| | | | | | | | | | spl_soc_init() seems to be a better name, as all SPL functions names start from the spl_ prefix. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
* sifive: reset: add DM based reset driver for SiFive SoC'sSagar Shrikant Kadam2020-08-041-0/+13
| | | | | | | | | | | | | | | | PRCI module within SiFive SoC's has register with which we can reset the sub-systems within the SoC. The resets to DDR and ethernet sub systems within FU540-C000 SoC are active low, and are hold low by default on power-up. Currently these are directly asserted within prci driver via register read/write. With the DM based reset driver support here, we bind the reset driver with clock (prci) driver and assert the reset signals of both sub-system's appropriately. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
* riscv: sifive: fu540: enable all cache ways from U-Boot properPragnesh Patel2020-07-031-0/+14
| | | | | | | | Add L2 cache node to enable all cache ways from U-Boot proper. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: sifive: fu540: add SPL configurationPragnesh Patel2020-06-041-0/+14
| | | | | | | | | | | | | | | Add a support for SPL which will boot from L2 LIM (0x0800_0000) and then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin) from MMC boot devices. SPL related code is leveraged from FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* riscv: cpu: fu540: Add support for cpu fu540Pragnesh Patel2020-06-042-0/+52
Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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