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* riscv: Move trap handler codes to mtrap.SBin Meng2018-12-181-1/+1
| | | | | | | | | Currently the M-mode trap handler codes are in start.S. For future extension, move them to a separate file mtrap.S. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* riscv: Make start.S available for all targetsBin Meng2018-10-031-0/+2
| | | | | | | | Currently start.S is inside arch/riscv/cpu/ax25/, but it can be common for all RISC-V targets. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: Add a helper routine to print CPU informationBin Meng2018-10-031-0/+5
This adds a helper routine to print CPU information. Currently it prints all the instruction set extensions that the processor core supports. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
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