summaryrefslogtreecommitdiffstats
path: root/arch/mips
Commit message (Expand)AuthorAgeFilesLines
* board_f: Rename initdram() to dram_init()Simon Glass2017-04-133-3/+3
* board_f: Drop return value from initdram()Simon Glass2017-04-052-4/+10
* board_f: Drop board_type parameter from initdram()Simon Glass2017-04-052-2/+2
* mips: Use common _AC macro now.Tom Rini2017-01-101-3/+0
* libfdt: replace ARCH_FIXUP_FDT with ARCH_FIXUP_FDT_MEMORYMasahiro Yamada2016-12-021-2/+0
* MIPS: Fix map_physmem for cached mappingsPaul Burton2016-11-301-1/+1
* MIPS: Use ram_top, not bi_memsize, in arch_lmb_reservePaul Burton2016-11-301-1/+1
* mips: Let cache.h be included from assembly sourceMarek Vasut2016-11-301-0/+2
* MIPS: add handling for generic and EJTAG exceptionsDaniel Schwierzeck2016-11-305-0/+344
* MIPS: reserve space for exception vectorsDaniel Schwierzeck2016-11-302-0/+20
* MIPS: add asm-offsets for struct pt_regsDaniel Schwierzeck2016-11-302-0/+66
* MIPS: add possibility to setup initial stack and global data in SRAMDaniel Schwierzeck2016-11-302-0/+18
* MIPS: factor out code for initial stack and global dataDaniel Schwierzeck2016-11-301-26/+30
* MIPS: fix iand optimize setup of CP0 registersDaniel Schwierzeck2016-11-302-24/+51
* MIPS: fix ROM exception vectorsDaniel Schwierzeck2016-11-301-10/+19
* MIPS: make inclusion of ROM exception vectors configurableDaniel Schwierzeck2016-11-304-3/+32
* Fix spelling of "resetting".Vagrant Cascadian2016-10-311-1/+2
* efi: Use asmlinkage for EFIAPISimon Glass2016-10-191-0/+0
* Remove arch/${ARCH}/include/asm/errno.hMasahiro Yamada2016-09-231-1/+0
* treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-231-1/+1
* MIPS: Hang if run on a secondary CPUPaul Burton2016-09-212-1/+27
* MIPS: Fix cache maintenance in relocate_code & simplifyPaul Burton2016-09-212-26/+21
* boston: Introduce support for the MIPS Boston development boardPaul Burton2016-09-213-0/+241
* MIPS: Ensure cache ops complete in mips_cache_resetPaul Burton2016-09-211-0/+2
* MIPS: Clear hazard between TagLo writes & cache opsPaul Burton2016-09-211-0/+1
* MIPS: Ensure Config.K0=2 applies before any memory accessesPaul Burton2016-09-211-0/+1
* MIPS: Malta: Enable CM & L2 supportPaul Burton2016-09-211-0/+2
* MIPS: Join the coherent domain when a CM is presentPaul Burton2016-09-212-0/+43
* MIPS: L2 cache supportPaul Burton2016-09-216-6/+291
* MIPS: Map CM Global Control RegistersPaul Burton2016-09-215-0/+88
* MIPS: Define register names for cache initPaul Burton2016-09-211-19/+23
* MIPS: If we don't need DDR for cache init, init cache firstPaul Burton2016-09-211-0/+9
* MIPS: Preserve Config implementation-defined bitsPaul Burton2016-09-212-2/+4
* MIPS: Enable use of the instruction cache earlierPaul Burton2016-09-212-8/+13
* MIPS: Probe cache line sizes once during bootPaul Burton2016-09-214-18/+45
* MIPS: ath79: Use mach_cpu_init instead of arch_cpu_initPaul Burton2016-09-211-1/+1
* mips: Add MIPSfpga platform supportZubair Lutfullah Kakakhel2016-09-211-0/+15
* mips: xilfpga: Add device tree filesZubair Lutfullah Kakakhel2016-09-213-0/+84
* net: mii: Use spatch to update miiphy_registerJoe Hershberger2016-08-151-8/+17
* libfdt: Introduce new ARCH_FIXUP_FDT optionMichal Simek2016-07-311-0/+2
* clk: convert API to match reset/mailbox styleStephen Warren2016-06-191-17/+28
* MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hexPaul Burton2016-06-101-1/+1
* MIPS: Fix invalidate_dcache_range to operate on L1 DcachePaul Burton2016-06-101-1/+1
* mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro defineWills Wang2016-05-312-1/+2
* mips: ath79: Add support for ungating USB and ethernet on qca953xWills Wang2016-05-311-0/+50
* mips: ath79: ap121: Enable ethernetWills Wang2016-05-312-2/+7
* mips: ath79: Rename get_bootstrap into ath79_get_bootstrapWills Wang2016-05-319-28/+15
* MIPS: Abstract cache op loops with a macroPaul Burton2016-05-311-41/+18
* MIPS: Split I & D cache line size configPaul Burton2016-05-314-20/+25
* MIPS: Move cache sizes to KconfigPaul Burton2016-05-313-4/+32
generated by cgit (git 2.34.1) at 2024-09-30 06:12:01 +0000