summaryrefslogtreecommitdiffstats
path: root/arch/mips/mach-mscc/include/mach/ddr.h
Commit message (Collapse)AuthorAgeFilesLines
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* mips: vcoreiii: Fix cache coherency issuesLars Povlsen2020-04-091-4/+0
| | | | | | | | | | | | | | | | | This patch fixes an stability issue seen on some vcoreiii targets, which was root caused to a cache inconsistency situation. The inconsistency was caused by having kuseg pointing to NOR area but used as a stack/gd/heap area during initialization, while only relatively late remapping the RAM area into kuseg position. The fix is to initialize the DDR right after the TLB setup, and then remapping it into position before gd/stack/heap usage. Reported-by: Ramin Seyed-Moussavi <ramin.moussavi@yacoub.de> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
* mips: mscc: serval: Fix resetHoratiu Vultur2019-05-031-25/+30
| | | | | | | | | In case the ddr training was failing, it couldn't reset, it was just hanging. Therefore reimplement it, so when ddr training is failing it would call _machine_restart, which power downs the DDR and does a force reset. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
* MSCC: Add support for Serval SoC family.Horatiu Vultur2019-01-231-9/+11
| | | | | | | | As Ocelot, Servalt, Luton and Jaguar2, this family of SoCs are found in Microsemi Switches solution. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MSCC: Add support for Servalt SoC family.Horatiu Vultur2019-01-231-8/+14
| | | | | | | | As Ocelot, Luton and Jaguar2, this family of SoCs are found in Microsemi Switches solution. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
* MSCC: Add support for Jaguar2 SOC familyHoratiu Vultur2019-01-161-7/+31
| | | | | | | As the Ocelot and Luton SoCs, this family of SoCs are found in Microsemi Switches solution. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
* MSCC: add support for Luton SoCsGregory CLEMENT2018-12-191-3/+109
| | | | | | | As the Ocelots SoCs, this family of SoCs are found in the Microsemi Switches solution. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
* MSCC: add support for Ocelot SoCsGregory CLEMENT2018-12-191-0/+708
This family of SoCs are found in the Microsemi Switches solution and have already a support in the linux kernel. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>