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	Commit message (Expand)	Author	Age	Files	Lines
*	MIPS: Ensure cache ops complete in mips_cache_reset	Paul Burton	2016-09-21	1	-0/+2
*	MIPS: Clear hazard between TagLo writes & cache ops	Paul Burton	2016-09-21	1	-0/+1
*	MIPS: Join the coherent domain when a CM is present	Paul Burton	2016-09-21	1	-0/+38
*	MIPS: L2 cache support	Paul Burton	2016-09-21	1	-5/+178
*	MIPS: Define register names for cache init	Paul Burton	2016-09-21	1	-19/+23
*	MIPS: Enable use of the instruction cache earlier	Paul Burton	2016-09-21	1	-0/+13
*	MIPS: Split I & D cache line size config	Paul Burton	2016-05-31	1	-2/+2
*	MIPS: Move cache sizes to Kconfig	Paul Burton	2016-05-31	1	-3/+3
*	MIPS: Use unchecked immediate addition/subtraction	Paul Burton	2016-05-21	1	-1/+1
*	MIPS: sync processor and register definitions with linux-4.4	Daniel Schwierzeck	2016-01-16	1	-8/+8
*	MIPS: clear TagLo select 2 during cache init	Paul Burton	2015-01-29	1	-2/+8
*	MIPS: allow systems to skip loads during cache init	Paul Burton	2015-01-29	1	-6/+13
*	MIPS: inline mips_init_[id]cache functions	Paul Burton	2015-01-29	1	-58/+28
*	MIPS: refactor cache loops to a macro	Paul Burton	2015-01-29	1	-17/+13
*	MIPS: refactor L1 cache config reads to a macro	Paul Burton	2015-01-29	1	-56/+41
*	MIPS: unify cache initialization code	Paul Burton	2015-01-29	1	-0/+277