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* arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit maskLey Foon Tan2018-08-151-3/+3
* ARM: socfpga: clk: Convert to clock frameworkMarek Vasut2018-08-132-218/+40
* ARM: socfpga: clk: Drop unused variables on Arria10Marek Vasut2018-08-131-17/+2
* ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 onlyMarek Vasut2018-08-131-0/+2
* ARM: socfpga: clk: Obtain handoff base clock via DMMarek Vasut2018-08-132-12/+27
* ARM: socfpga: Remove adhoc ethernet reset and configurationMarek Vasut2018-08-132-49/+5
* ARM: socfpga: Zap unused reset codeMarek Vasut2018-08-132-126/+0
* ARM: socfpga: Zap all the UART handling complexityMarek Vasut2018-08-135-149/+0
* ARM: socfpga: Enable DM I2C framework on A10Marek Vasut2018-08-131-0/+1
* ARM: socfpga: Enable DM reset framework on A10Marek Vasut2018-08-131-0/+2
* ARM: socfpga: Register the FPGA on A10 in SPL againMarek Vasut2018-08-131-0/+6
* arm: socfpga: gen5: combine some init code for SPL and U-BootSimon Goldschmidt2018-08-133-39/+22
* arm: socfpga: cyclone5: handle debug uartSimon Goldschmidt2018-08-131-0/+6
* arm: socfpga: spl_gen5: clean up malloc_base assignmentSimon Goldschmidt2018-08-131-3/+0
* arm: socfpga: fix SPL on gen5 after moving to DM serialSimon Goldschmidt2018-08-131-0/+7
* Kconfig: Sort bool, default, select and imply optionsMichal Simek2018-07-301-2/+2
* ARM: socfpga: Init missing security policies on A10Marek Vasut2018-07-251-0/+13
* ARM: socfpga: Assure correct CPACR configurationMarek Vasut2018-07-251-1/+3
* lib: fdtdec: Rename routine fdtdec_setup_memory_size()Siva Durga Prasad Paladugu2018-07-191-1/+1
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2018-07-1317-78/+1461
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| * arm: socfpga: Fixes: include <debug_uart.h>Ley Foon Tan2018-07-121-0/+1
| * arm: socfpga: Fix: Compile MCR instruction on ARM 32-bit onlyLey Foon Tan2018-07-121-0/+2
| * ARM: socfpga: Assure correct ACTLR configurationMarek Vasut2018-07-121-1/+12
| * ARM: socfpga: Pull DRAM size from DTMarek Vasut2018-07-121-1/+3
| * arm: socfpga: Add do_bridge_reset for Arria 10Ley Foon Tan2018-07-121-0/+9
| * arm: socfpga: stratix10: Enable Stratix10 SoC buildLey Foon Tan2018-07-121-0/+13
| * ddr: altera: stratix10: Add DDR support for Stratix10 SoCLey Foon Tan2018-07-122-6/+188
| * arm: socfpga: stratix10: Add timer support for Stratix10 SoCLey Foon Tan2018-07-122-1/+29
| * arm: socfpga: stratix10: Add SPL driver for Stratix10 SoCLey Foon Tan2018-07-123-0/+323
| * arm: socfpga: Restructure the SPL fileLey Foon Tan2018-07-123-52/+120
| * arm: socfpga: stratix10: Add MMU support for Stratix10 SoCLey Foon Tan2018-07-122-0/+72
| * arm: socfpga: stratix10: Add mailbox support for Stratix10 SoCLey Foon Tan2018-07-123-0/+525
| * arm: socfpga: stratix10: Add misc support for Stratix10 SoCLey Foon Tan2018-07-122-0/+134
| * arm: socfpga: misc: Move bridge command to misc commonLey Foon Tan2018-07-123-23/+37
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* board/aries: RemoveTom Rini2018-07-021-7/+0
* SPDX: Fixup SPDX tags in a few new filesTom Rini2018-05-201-2/+1
* arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switchLey Foon Tan2018-05-181-0/+4
* arm: socfpga: stratix10: Add pinmux support for Stratix10 SoCLey Foon Tan2018-05-185-1/+329
* arm: socfpga: stratix10: Add reset manager driver for Stratix10 SoCLey Foon Tan2018-05-185-0/+272
* arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoCLey Foon Tan2018-05-187-2/+691
* arm: socfpga: stratix10: Add watchdog and firewall base addressesLey Foon Tan2018-05-181-0/+11
* ARM: socfpga: Fix Documentation errors in scu_registersBen Kalo2018-05-181-2/+2
* ARM: socfpga: Adding SoCFPGA info for both SPL and U-BootTien Fong Chee2018-05-183-5/+10
* ARM: socfpga: Adding clock frequency info for U-BootTien Fong Chee2018-05-181-0/+7
* configs: Add DDR Kconfig support for Arria 10Tien Fong Chee2018-05-181-0/+1
* ARM: socfpga: Add DDR driver for Arria 10Tien Fong Chee2018-05-182-0/+4
* ARM: socfpga: Add DRAM bank size initialization functionTien Fong Chee2018-05-181-0/+7
* ARM: socfpga: Rename the gen5 sdram driver to more specific nameTien Fong Chee2018-05-182-429/+445
* ARM: socfpga: Repair A10 EMAC reset handlingMarek Vasut2018-05-184-66/+87
* ARM: socfpga: Sync A10 clock manager binding parserMarek Vasut2018-05-182-49/+111
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