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* common: Move get_ticks() function out of common.hSimon Glass2019-12-021-0/+1
* ARM: socfpga: Unreset NAND in SPL on Gen5Marek Vasut2019-11-251-0/+7
* ARM: socfpga: Add ArriaV ST/SX IDMarek Vasut2019-11-251-0/+2
* ARM: socfpga: Purge pending transactions upon enabling bridges on Gen5Marek Vasut2019-11-251-0/+3
* ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disableMarek Vasut2019-11-251-1/+1
* socfpga: fix include guard in misc.h (arch vs. global)Simon Goldschmidt2019-11-201-3/+3
* arm: socfpga: gen5: fix ERR_PTR_OFFSETSimon Goldschmidt2019-11-071-0/+3
* ARM: socfpga: vining_fpga: Rename VINING|FPGAMarek Vasut2019-10-091-5/+5
* spl: Convert CONFIG_SPL_SIZE_LIMIT to hexSimon Glass2019-10-081-1/+1
* spl: Allow tiny printf() to be controlled in SPL and TPLSimon Glass2019-10-081-2/+2
* arm: socfpga: gen5: don't zero bss in board_init_f()Simon Goldschmidt2019-08-151-2/+0
* env: Move env_set() to env.hSimon Glass2019-08-112-0/+2
* sysreset: add support for socfpga sysresetSimon Goldschmidt2019-07-212-42/+0
* arm: socfpga: rst: add register definition for cold resetSimon Goldschmidt2019-07-211-0/+1
* arm: socfpga: provide default SPL_SIZE_LIMIT for gen5Simon Goldschmidt2019-06-141-0/+8
* ARM: socfpga: Clear PL310 early in SPLMarek Vasut2019-05-241-0/+1
* ARM: socfpga: Pull PL310 clearing into common codeMarek Vasut2019-05-243-57/+55
* CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner2019-05-181-2/+2
* arm: socfpga: Re-add support for Aries MCV SoM and MCVEV[KP] boardWolfgang Grandegger2019-05-141-0/+7
* arm: sofcpga: s10: remove unused ad-hoc reset codeSimon Goldschmidt2019-05-142-12/+0
* arm: socfpga: remove re-added ad-hoc reset codeSimon Goldschmidt2019-05-143-11/+1
* spl: socfpga: Implement fpga bitstream loading with socfpga loadfsTien Fong Chee2019-05-102-1/+31
* ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loadingTien Fong Chee2019-05-101-2/+37
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2019-05-076-203/+30
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| * ARM: socfpga: stratix10: Probe FPGA status before bridge enableAng, Chee Hong2019-05-061-0/+12
| * ARM: socfpga: stratix10: Disable FPGA2SOC resetAng, Chee Hong2019-05-062-3/+6
| * arm: socfpga: Move Stratix 10 SDRAM driver to DMLey Foon Tan2019-05-062-198/+10
| * ddr: altera: Compile ALTERA SDRAM in SPL onlyLey Foon Tan2019-05-061-2/+2
* | ARM: socfpga: use the pl310 driver to configure the cacheDinh Nguyen2019-05-051-13/+3
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* ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()Marek Vasut2019-04-291-31/+0
* ARM: socfpga: Add support for selecting bridges in bridge commandMarek Vasut2019-04-295-10/+25
* ARM: socfpga: Fully unmap the FPGA bridges from L3 spaceMarek Vasut2019-04-291-1/+2
* ARM: socfpga: Disable bridges in SPL unless booting from FPGAMarek Vasut2019-04-291-5/+3
* ARM: socfpga: Factor out handoff register configurationMarek Vasut2019-04-292-2/+24
* arm: socfpga: mailbox: Fix off-by-one error on command length checkingLey Foon Tan2019-04-251-2/+2
* arm: socfpga: gen5: reduce SPL pre-reloc mallocSimon Goldschmidt2019-04-251-0/+3
* arm: socfpga: imply/default common config optionsSimon Goldschmidt2019-04-251-0/+20
* ddr: altera: Stratix10: Add ECC memory scrubbingLey Foon Tan2019-04-171-0/+9
* arm: socfpga: stratix10: Add cpu_has_been_warmreset()Ley Foon Tan2019-04-172-0/+12
* ddr: altera: stratix10: Move SDRAM size check to SDRAM driverLey Foon Tan2019-04-171-11/+0
* arm: socfpga: implement proper peripheral resetSimon Goldschmidt2019-04-172-18/+1
* arm: socfpga: move gen5 SDR driver to DMSimon Goldschmidt2019-04-172-24/+9
* ARM: socfpga: Disable D cache in SPLMarek Vasut2019-03-091-0/+2
* ARM: socfpga: fix data and tag latency values for pl310 cache controllerDinh Nguyen2019-03-091-2/+2
* ARM: socfpga: Clear PL310 early in SPLMarek Vasut2019-02-251-0/+58
* ARM: socfpga: Configure PL310 latenciesMarek Vasut2019-02-251-0/+3
* arm: socfpga: gen5: remove hacked ETH RST handlingSimon Goldschmidt2019-02-183-110/+1
* spl: Kconfig: Replace CONFIG_SPL_EXT_SUPPORT to CONFIG_SPL_FS_EXT4Tien Fong Chee2019-02-013-3/+3
* spl: Kconfig: Replace CONFIG_SPL_FAT_SUPPORT with CONFIG_SPL_FS_FATTien Fong Chee2019-02-013-3/+3
* arm: socfpga: stratix10: Enable Stratix10 FPGA ReconfigurationAng, Chee Hong2018-12-201-0/+1
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