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* arm: socfpga: smc: Add function to get usercodeSiew Chin Lim2021-04-081-0/+1
| | | | | | | Add function to send mailbox command via SMC to get usercode from SDM. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: Changed to store QSPI reference clock in kHzSiew Chin Lim2021-04-082-1/+19
| | | | | | | | | | | | | | Changed to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex. This patch is in preparation for Intel N5X SDRAM driver support. Reserved 4 bits for Intel N5X SDRAM driver, and there will be 28 bits to store QSPI reference clock. Due to limited bits, QSPI reference clock frequency is converted to kHz from Hz. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* arm: socfpga: Move Stratix10 and Agilex clock manager common codeSiew Chin Lim2021-04-084-4/+1
| | | | | | | | Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: Restructure Stratix10 and Agilex handoff codeSiew Chin Lim2021-04-082-5/+22
| | | | | | | | | | | | | | | | Restructure Stratix10 and Agilex handoff code to used by all SOC64 devices, in preparation to support handoff for Diamond Mesa. Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c which contains the generic function to parse the handoff data. Update system_manager_soc64.c to use generic handoff function in wrap_handoff_soc64.c. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: Rearrange sequence of macros in handoff_soc64.hSiew Chin Lim2021-04-081-10/+12
| | | | | | | | Rearrange sequence of macros in handoff_soc64.h without any functionality change. In preparation for Stratix10 and Agilex handoff function restructuring. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* arm: socfpga: Rename Stratix10 and Agilex handoff common macrosSiew Chin Lim2021-04-082-39/+39
| | | | | | | Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from S10_HANDOFF to SOC64_HANDOFF. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* Merge tag 'v2021.04-rc4' into nextTom Rini2021-03-154-4/+66
|\ | | | | | | Prepare v2021.04-rc4
| * arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)Siew Chin Lim2021-03-082-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Vendor Authorized Boot is a security feature for authenticating the images such as U-Boot, ARM trusted Firmware, Linux kernel, device tree blob and etc loaded from FIT. After those images are loaded from FIT, the VAB certificate and signature block appended at the end of each image are sent to Secure Device Manager (SDM) for authentication. U-Boot will validate the SHA384 of the image against the SHA384 hash stored in the VAB certificate before sending the image to SDM for authentication. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64Siew Chin Lim2021-03-082-4/+2
| | | | | | | | | | | | Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | reset: Remove addr parameter from reset_cpu()Harald Seiler2021-03-021-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: socfpga: Add secure register access helper functions for SoC 64bitsSiew Chin Lim2021-01-151-0/+19
| | | | | | | | | These secure register access functions allow U-Boot proper running at EL2 (non-secure) to access System Manager's secure registers by calling the ATF's PSCI runtime services (EL3/secure). Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits)Chee Hong Ang2021-01-151-0/+13
| | | | | | | | | | | | | invoke_smc() allow U-Boot proper running in non-secure mode (EL2) to invoke SMC call to ATF's PSCI runtime services such as System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc. smc_send_mailbox() is a send mailbox command helper function which invokes the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD) to send mailbox messages to Secure Device Manager (SDM). Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* arm: socfpga: fix Gen5 enable of EMAC via FPGARalph Siemsen2020-10-211-2/+2
| | | | | | | | | | | | | | An earlier conversion from struct to defines introduced two errors, both related to setup of EMAC routed via the FPGA. One of the offsets was incorrect, and the EMAC0/EMAC1 were swapped. The effect of this was rather odd: both ports could operate at gigabit, but one of them would fail to transmit when operating at 100Mbit. Fixes: db5741f7a85ec3ee79b64496172afaa7dc2cb225 ("arm: socfpga: Convert system manager from struct to defines") Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: mailbox: Update mailbox response codesLey Foon Tan2020-10-091-2/+36
| | | | | | | Sync latest mailbox response codes from SDM firmware. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* arm: socfpga: soc64: Document down boot_scratch_cold register usageChin Liang See2020-10-091-0/+8
| | | | | | | | | | | Document down the usage of boot_scratch_cold register to avoid overlapping of usage in the code for S10 & Agilex. The boot_scratch_cold register is generally used for passing critical system info between SPL, U-Boot and Linux. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: soc64: Show reset state in SPLChee Hong Ang2020-10-091-0/+1
| | | | | | | | | Print reset state (warm/cold) together with the source (watchdog/MPU) which has triggered the warm reset on S10 & Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: soc64: Add SDM triggered warm reset bit maskChee Hong Ang2020-10-091-2/+9
| | | | | | | | | Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat register when checking for HPS warm reset status. Refactor the warm reset mask macro for clarity purpose. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: soc64: Check FPGA Config status register before bridge resetChee Hong Ang2020-09-032-1/+10
| | | | | | | | | Instead of querying SDM for FPGA configuration status through mailbox messages, U-Boot now checks System Manager's FPGA Config status register for FPGA configuration status before resetting bridge. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* socfpga: Mark socfpga_fpga_add() as static inline in the non-FPGA caseTom Rini2020-07-011-1/+1
| | | | | | | | | | | Unless we mark the function as 'static inline' it may end up being non-inlined by the compiled and result in duplicate functions. Cc: Marek Vasut <marex@denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Vasut <marex@denx.de>
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-1811-0/+16
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* Use __ASSEMBLY__ as the assembly macrosSimon Glass2020-05-184-6/+6
| | | | | | | Some places use __ASSEMBLER__ instead which does not work since the Makefile does not define it. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offsetLey Foon Tan2020-04-271-1/+1
| | | | | | | Offset value for CLKMGR_S10_PERPLL_BYPASS should be 0xb0, fix it. Reported-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: Add onchip RAM size macroLey Foon Tan2020-03-312-0/+4
| | | | | | Add OCRAM size macro for Gen5 and Arria 10. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* ddr: altera: Add DDR2 support to Gen5 driverMarek Vasut2020-02-051-9/+37
| | | | | | | | | | Add DDR2 support to Gen5 DRAM driver. As the DDR2 macro names generated by Quartus are named differently than the DDR3 ones, use anon unions to store them in the same structures, without growing their size. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: socfpga: stratix10: Enable SMMU accessThor Thayer2020-01-071-0/+7
| | | | | | | | Enable TCU access through the Stratix10 CCU so that the SMMU can access the SDRAM. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: agilex: Add clock handoff offset for AgilexLey Foon Tan2020-01-071-2/+7
| | | | | | | Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: socfpga: agilex: Add clock wrapper functionsLey Foon Tan2020-01-072-0/+16
| | | | | | | | Add clock wrapper functions call to clock DM functions to get clock frequency and used in cm_print_clock_quick_summary(). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHzLey Foon Tan2020-01-071-3/+1
| | | | | | | | CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz. Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: socfpga: Move Stratix10 and Agilex clock manager common codeLey Foon Tan2020-01-072-13/+26
| | | | | | | Move Stratix10 and Agilex clock manager common code to new header file. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: socfpga: agilex: Add system manager supportLey Foon Tan2020-01-071-1/+2
| | | | | | | Add system manager support for Agilex. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: socfpga: Move Stratix10 and Agilex system manager common codeLey Foon Tan2020-01-073-125/+124
| | | | | | | | Move Stratix10 and Agilex system manager common code to system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: socfpga: agilex: Add reset manager supportLey Foon Tan2020-01-071-1/+2
| | | | | | | Add reset manager support for Agilex. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: socfpga: Move Stratix10 and Agilex reset manager common codeLey Foon Tan2020-01-073-96/+39
| | | | | | | | | | Move Stratix10 and Agilex reset manager common code to reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*. Remove unused RSTMGR_XXX defines. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: socfpga: Move firewall code to firewall fileLey Foon Tan2020-01-071-4/+6
| | | | | | | | | | | Move firewall related code to new firewall.c, to share code in Stratix 10 and Agilex. SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC to allow DMA transfer to OCRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: socfpga: agilex: Add base address for Intel Agilex SoCLey Foon Tan2020-01-071-0/+4
| | | | | | | | | | Add base address for Intel Agilex SoC. Reuse base_addr_s10.h for Agilex, only one base address is different from S10. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: socfpga: Convert clock manager from struct to definesLey Foon Tan2020-01-074-215/+147
| | | | | | | | | | | Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get clock manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: socfpga: Convert system manager from struct to definesLey Foon Tan2020-01-074-285/+118
| | | | | | | | | | | Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: socfpga: Convert reset manager from struct to definesLey Foon Tan2020-01-075-75/+26
| | | | | | | | | | | | | | Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get reset manager base address from DT node instead of using #define. spl_early_init() initializes the DT setup. So, move spl_early_init() to beginning of function and before get base address from DT. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* socfpga: fix include guard in misc.h (arch vs. global)Simon Goldschmidt2019-11-201-3/+3
| | | | | | | | | | The file arch/arm/mach-socfpga/include/mach/misc.h used the same include guard as the global include/misc.h. Fix this by giving the arch file an arch prefix. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: rst: add register definition for cold resetSimon Goldschmidt2019-07-211-0/+1
| | | | | | | | | | | This adds a define for the bit in rstmgr's ctrl regiser that issues a cold reset (we had a define for the warm reset bit only) in preparation for a proper sysrese driver. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Series changes: 2 - separate this patch to the register descriptions from the actual sysreset driver patch
* ARM: socfpga: Pull PL310 clearing into common codeMarek Vasut2019-05-241-0/+1
| | | | | | | | | | | | Pull the PL310 clearing code into common code, so it can be reused by Arria10. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* arm: sofcpga: s10: remove unused ad-hoc reset codeSimon Goldschmidt2019-05-141-1/+0
| | | | | | | | | The stratix 10 reset manager ad-hoc code in arch/arm contains an unused function 'reset_deassert_peripherals_handoff' that has been added from the beginning. As this is probably a result of copying the gen5 reset manager and this function has never been used, remove it. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: socfpga: remove re-added ad-hoc reset codeSimon Goldschmidt2019-05-141-1/+0
| | | | | | | | | | | | | | commit c5de2b7eae68 ("arm: socfpga: implement proper peripheral reset") has removed the call to 'reset_deassert_peripherals_handoff()' from socfpga gen5 SPL since the reset driver now handles resets. However, commit c1d4b464c8b8 ("ARM: socfpga: Disable bridges in SPL unless booting from FPGA") has re-added this ad-hoc reset code, so that all peripherals were now again enabled instead of letting the drivers enable them by request. While at it, remove this function for gen5 as it should not be used. Fixes: commit c1d4b464c8b8 ("ARM: socfpga: Disable bridges in SPL unless booting from FPGA") Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* spl: socfpga: Implement fpga bitstream loading with socfpga loadfsTien Fong Chee2019-05-101-0/+1
| | | | | | | | Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loadingTien Fong Chee2019-05-101-2/+37
| | | | | | | | | Add FPGA driver to support program FPGA with FPGA bitstream loading from filesystem. The driver are designed based on generic firmware loader framework. The driver can handle FPGA program operation from loading FPGA bitstream in flash to memory and then to program FPGA. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* ARM: socfpga: stratix10: Disable FPGA2SOC resetAng, Chee Hong2019-05-061-0/+2
| | | | | | | | | Software must never reset FPGA2SOC bridge. This bridge must only be reset by POR/COLD/WARM reset. Asserting the FPGA2SOC reset by software can cause the SoC to lock-up if there are traffics being drived into FPGA2SOC bridge. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
* arm: socfpga: Move Stratix 10 SDRAM driver to DMLey Foon Tan2019-05-061-192/+0
| | | | | | | | | | | | | | Convert Stratix 10 SDRAM driver to device model. Get rid of call to socfpga_per_reset() and use reset framework. SPL is changed from calling function in SDRAM driver directly to just probing UCLASS_RAM. Move sdram_s10.h from arch to driver/ddr/altera directory. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* ARM: socfpga: Add support for selecting bridges in bridge commandMarek Vasut2019-04-291-1/+1
| | | | | | | | | | | | | Add optional "mask" argument to the SoCFPGA bridge command, to select which bridges should be enabled/disabled. This allows the user to avoid enabling bridges which are not connected into the FPGA fabric. Default behavior is to enable/disable all bridges. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* ARM: socfpga: Factor out handoff register configurationMarek Vasut2019-04-291-0/+1
| | | | | | | | | | | | Factor out the code for programming preloader handoff register values, the ISWGRP Handoff 0 and 1. These registers later control which bridges are enabled by the "bridge" command on Gen5 devices. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* ddr: altera: Stratix10: Add ECC memory scrubbingLey Foon Tan2019-04-171-0/+9
| | | | | | | | | | | | | Scrub memory content if ECC is enabled and it is not from warm reset boot. Enable icache and dcache before scrub memory and use "DC ZVA" instruction to clear memory to zeros. This instruction writes a cache line at a time and it can prevent false ECC error trigger if write cache line partially. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
generated by cgit (git 2.34.1) at 2025-09-02 23:16:38 +0000