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* treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún2021-05-243-4/+4
| | | | | | | | | | | | | | | | | This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: am64x: Add support for selecting DT based on EEPROMLokesh Vutla2021-05-121-0/+26
| | | | | | | Enable support for selecting DTB within SPL based on EEPROM. This will help to use single defconfig for both EVM and SK Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* board: ti: am64x: Add support for reading eeprom dataLokesh Vutla2021-05-121-0/+3
| | | | | | | | | | I2C EEPROM data contains the board name and its revision. Add support for: - Reading EEPROM data and store a copy at end of SRAM - Updating env variable with relevant board info - Printing board info during boot. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* arm: mach-k3: am642: Add support for triggering ddr init from SPLDave Gerlach2021-05-121-0/+6
| | | | | | | | In SPL, DDR should be made available by the end of board_init_f() so that apis in board_init_r() can use ddr. Adding support for triggering DDR initialization from board_init_f(). Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* board: ti: am64x: Add board support for am64x evmDave Gerlach2021-05-121-0/+1
| | | | | | Add board specific initialization for am64x based boards. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* armv8: mach-k3: am642: Add custom MMU supportKeerthy2021-05-121-0/+41
| | | | | | | | | | | | Change the memory attributes for the DDR regions used by the remote processors on AM65x so that the cores can see and execute the proper code. A separate table based on the previous K3 SoCs is introduced since the number of remote processors and their DDR usage is different between the SoC families. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* arm: mach-k3: am642: Shut down R5 core after ATF startup on A53Suman Anna2021-05-121-0/+51
| | | | | | | | | | | | | | | | | | The AM642 SoCs use the Main R5FSS0 as a boot processor, and runs the R5 SPL that performs the initialization of the System Controller processor and starting the Arm Trusted Firmware (ATF) on the Arm Cortex A53 cluster. The Core0 serves as this boot processor and is parked in WFE after all the initialization. Core1 does not directly participate in the boot flow, and is simply parked in a WFI. Power down these R5 cores (and the associated RTI timer resources that were indirectly powered up) after starting up ATF on A53 by using the appropriate SYSFW API in release_resources_for_core_shutdown(). This allows these Main R5F cores to be further controlled from the A53 to run regular applications. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* arm: mach-k3: am642: Use mmc start and stop callbacksDave Gerlach2021-05-121-1/+33
| | | | | | | To avoid any glitches on MMC clock line, make use of pm per and post callbacks when loading sysfw. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* arm: mach-k3: am642: Load SYSFW binary and config from boot mediaDave Gerlach2021-05-121-0/+37
| | | | | | | | | | | | | Use the System Firmware (SYSFW) loader framework to load and start the SYSFW as part of the AM642 early initialization sequence. Also make use of existing logic to detect if ROM has already loaded sysfw and avoided attempting to reload and instead just prepare to use already running firmware. While at it also initialize the MAIN_UART1 pinmux as it is used by SYSFW to print diagnostic messages. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* arm: mach-k3: am642: Store boot info from ROMDave Gerlach2021-05-122-0/+23
| | | | | | | | | | For AM642, ROM supports loading system firmware directly from boot image. ROM passes information about the number of images that are loaded to bootloader at a specific address that is temporary. Add support for storing this information somewhere permanent before it gets corrupted. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* arm: mach-k3: am642: Unlock all applicable control MMR registersDave Gerlach2021-05-122-4/+22
| | | | | | | To access various control MMR functionality the registers need to be unlocked. Do that for all control MMR regions in the MAIN domain. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* arm: mach-k3: am642: Add support for boot device detectionKeerthy2021-05-125-0/+198
| | | | | | | | | | | | | AM642 allows for booting from primary or backup boot media. Both media can be chosen individually based on switch settings. ROM looks for a valid image in primary boot media, if not found then looks in backup boot media. In order to pass this boot media information to boot loader, ROM stores a value at a particular address. Add support for reading this information and determining the boot media correctly. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* arm: mach-k3: Add basic support for AM642 SoC definitionDave Gerlach2021-05-123-4/+39
| | | | | | | | | | | | | | | | | | | | | | | The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* reset: Remove addr parameter from reset_cpu()Harald Seiler2021-03-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* common: Drop asm/global_data.h from common headerSimon Glass2021-02-023-0/+3
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()Simon Glass2021-01-053-3/+3
| | | | | | | | In the spirit of using the same base name for all of these related macros, rename this to have the operation at the end. This is not widely used so the impact is fairly small. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Drop the unused arg in uclass_find_device_by_seq()Simon Glass2020-12-183-3/+3
| | | | | | | | Now that there is only one sequence number (rather than both requested and assigned ones) we can simplify this function. Also update its caller to simplify the logic. Signed-off-by: Simon Glass <sjg@chromium.org>
* armv8: K3: j7200: Add custom MMU supportSuman Anna2020-09-151-1/+58
| | | | | | | | | | | | | | The A72 U-Boot code can load and boot a number of the available R5FSS Cores on the J7200 SoC. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. The J7200 SoC has less number of remote processors compared to J721E, so use less memory for the remote processors. So, a separate table based on the current J721E table is added for J7200 SoCs, and selected using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol. Signed-off-by: Suman Anna <s-anna@ti.com>
* arm: mach-k3: Add HyperFlash boot mode supportVignesh Raghavendra2020-09-151-0/+1
| | | | | | | | HBMC controller on TI K3 SoC provides MMIO access to HyperFlash similar to legacy Parallel CFI NOR flashes. Therefore alias HyperFlash bootmode to NOR boot to enable SPL to load next stage using NOR boot flow. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* arm: mach-k3: j7200: Detect if ROM has already loaded sysfwLokesh Vutla2020-08-113-1/+12
| | | | | | | | | | Detect if sysfw is already loaded by ROM and pass this information to sysfw loader. Based on this information sysfw loader either loads the sysfw image from boot media or just receives the boot notification message form sysfw. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
* arm: mach-k3: j7200: Add support for storing extended boot info from ROMLokesh Vutla2020-08-113-2/+15
| | | | | | | | | | Starting J7200 SoC, ROM supports for loading sysfw directly from boot image. ROM passes this information on number of images that are loaded to bootloader at certain location. Add support for storing this information before it gets corrupted. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
* arm: mach-k3: j7200: Add support for SOC detectionLokesh Vutla2020-08-113-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The J7200 SoC is a part of the K3 Multicore SoC architecture platform. It is targeted for automotive gateway, vehicle compute systems, Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. The SoC aims to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, two clusters of lockstep capable dual Cortex-R5F MCUs and a Centralized Device Management and Security Controller (DMSC). * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS. * Integrated Ethernet switch supporting up to a total of 4 external ports in addition to legacy Ethernet switch of up to 2 ports. * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and I2C, eCAP/eQEP, eHRPWM among other peripherals. * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 Add support for detection J7200 SoC Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
* arm: mach-k3: j721e: Fix unlocking control module registersLokesh Vutla2020-08-111-2/+2
| | | | | | | | In main control mmr there is no partition 4 and partition 6 is available only on J721e. Fix the same in ctrl_mmr_unlock function Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
* arm: mach-k3: j721e: Add detection for j721eLokesh Vutla2020-08-115-0/+18
| | | | | | | | | Add an api soc_is_j721e(), and use it to enable certain functionality that is available only on j721e. This detection is needed when DT is not available. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
* arm: mach-k3: sysfw-loader: Add support for rom loading sysfw imageLokesh Vutla2020-08-114-21/+43
| | | | | | | | | | | Starting J7200 SoC, ROM supports for loading sysfw directly from boot image. In such cases, SPL need not load sysfw from boot media, but need to receive boot notification message from sysfw. So separate out remoteproc calls for system controller from sysfw loader and just receive the boot notification if sysfw is already loaded. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
* arm: mach-k3: Move mmr_unlock to a common locationLokesh Vutla2020-08-114-20/+11
| | | | | | | | mmr_unlock api is common for all k3 devices. Move it to a common location. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
* arm: mach-k3: Fix platform hang when SPL_MULTI_DTB_FIT is not enabledJean-Jacques Hiblot2020-08-111-1/+7
| | | | | | | | | If SPL_MULTI_DTB_FIT is not enabled, then CONFIG_SPL_OF_LIST is not defined And in turn tispl.bin ends up not embedding any DTB. Fixing it by using CONFIG_DEFAULT_DEVICE_TREE if SPL_OF_LIST is empty. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* board: ti: j721e: Probe eeprom only when CONFIG_TI_I2C_BOARD_DETECT is definedLokesh Vutla2020-08-111-1/+2
| | | | | | | | | Guard all eeprom probe with TI_I2C_BOARD_DETECT to avoid reading eeprom when eeprom is not available Reviewed-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
* arm: mach-k3: am6_init: Add support for USB boot modeFaiz Abbas2020-08-113-1/+9
| | | | | | Add support for identifying USB host and device boot modes Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
* arm: mach-k3: am6_init: Do USB fixups to facilitate host and device boot modesFaiz Abbas2020-08-111-0/+40
| | | | | | | | | | | | | | | | | U-boot only supports either USB host or device mode for a node at a time in dts. To support both host and dfu bootmodes, set "peripheral" as the default dr_mode but fixup property to "host" if host bootmode is detected. This needs to happen before the dwc3 generic layer binds the usb device to a host or device driver. Therefore, add an fdtdec_setup_board() implementation to fixup the dt based on the boot mode. Also use the same fixup function to set the USB-PCIe Serdes mux to PCIe in both the host and device cases. This is required for accessing the interface at USB 2.0 speeds. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
* arm: mach-k3: am6_init: Gate mmc related configurations with the appropriate ↵Faiz Abbas2020-08-111-1/+4
| | | | | | | | | config Gate mmc related system related configurations with DM_MMC to avoid build errors when MMC is not enabled Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
* arm: mach-k3: sysfw-loader: Add support to load SYSFW from USBFaiz Abbas2020-08-111-0/+11
| | | | | | Add support for loading system firmware from a USB mass storage device Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
* armv7R: K3: am654: Use full malloc in SPL both pre and post relocFaiz Abbas2020-08-111-0/+18
| | | | | | | | | | | | In order to be able to use things like file system drivers early on in SPL (before relocation) in a memory-constrained environment when DDR is not yet available we cannot use the simple malloc scheme which does not implement the freeing of previously allocated memory blocks. To address this issue go ahead and enable the use of the full malloc by manually initializing the required functionality inside board_init_f by creating a full malloc pool inside the pre-relocation malloc pool. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
* arm: mach-k3: Clean non-coherent lines out of L3 cacheAndrew F. Davis2020-08-112-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | When switching on or off the ARM caches some care must be taken to ensure existing cache line allocations are not left in an inconsistent state. An example of this is when cache lines are considered non-shared by and L3 controller even though the lines are shared. To prevent these and other issues all cache lines should be cleared before enabling or disabling a coherent master's cache. ARM cores and many L3 controllers provide a way to efficiently clean out all cache lines to allow for this, unfortunately there is no such easy way to do this on current K3 MSMC based systems. We could explicitly clean out every valid external address tracked by MSMC (all of DRAM), or we could attempt to identify only the set of addresses accessed by a given boot stage and flush only those specifically. This patch attempts the latter. We start with cleaning the SPL load address. More addresses can be added here later as they are identified. Note that we perform a flush operation for both the flush and invalidate operations, this is not a typo. We do this to avoid the situation that some ARM cores will promote an invalidate to a clean+invalidate, but only emit the invalidation operation externally, leading to a loss of data. Signed-off-by: Andrew F. Davis <afd@ti.com> Tested-by: Faiz Abbas <faiz_abbas@ti.com>
* sf: Drop dm.h header file from spi_flash.hSimon Glass2020-08-031-0/+1
| | | | | | | This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* Makefile: Rename ALL-y to INPUTS-ySimon Glass2020-07-281-5/+5
| | | | | | | | | | | When binman is in use, most of the targets built by the Makefile are inputs to binman. We then need a final rule to run binman to produce the final outputs. Rename the variable to indicate this, and add a new 'inputs' target. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* arm: mach-k3: Use SOC driver for device identificationDave Gerlach2020-07-253-36/+19
| | | | | | | Make use of UCLASS_SOC to find device family and revision for print_cpuinfo. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini2020-07-243-19/+36
| | | | | | | | | | This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: mach-k3: Use SOC driver for device identificationDave Gerlach2020-07-203-36/+19
| | | | | | | Make use of UCLASS_SOC to find device family and revision for print_cpuinfo. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* arm: k3: use correct weak function name spl_board_prepare_for_linuxPatrick Delaunay2020-07-131-1/+1
| | | | | | | Replace the function spl_board_prepare_for_boot_linux by the correct name of the weak function spl_board_prepare_for_linux defined in spl.h. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* arm: k3: Consolidate and silence k3_fit_atf.sh callJan Kiszka2020-07-131-8/+9
| | | | | | | | | | Buiding u-boot-spl-k3[_HS].its is currently unconditionally verbose about what it does. Change that by wrapping the call to k3_fit_atf.sh into a cmd, also using that chance to reduce duplicate lines of makefile code - only IS_HS=1 is different when CONFIG_TI_SECURE_DEVICE is on. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
* Merge tag 'ti-v2020.07-rc3' of ↵Tom Rini2020-05-256-2/+85
|\ | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Enable DM_ETH on omap3_logic board - Enable Caches in SPL for K3 platforms - Enable backup boot mode support for J721E - Update the DDR timings for AM654 EVM - Add automated tests for RX-51
| * arm: mach-k3: Enable dcache in SPLJan Kiszka2020-05-194-0/+38
| | | | | | | | | | | | | | | | | | | | Add support for enabling dcache already in SPL. It accelerates the boot and resolves the risk to run into unaligned 64-bit accesses. Based on original patch by Lokesh Vulta. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: mach-k3: j721e_init: Add support for backup boot modesAndreas Dannenberg2020-05-193-2/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | When the boot of J721E devices using the primary bootmode (configured via device pins) fails a boot using the configured backup bootmode is attempted. To take advantage of the backup boot mode feature go ahead and add support to the J721E init code to determine whether the ROM code performed the boot using the primary or backup boot mode, and if booted from the backup boot mode, decode the bootmode settings into the appropriate U-Boot mode accordingly so that the boot can proceed. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
* | common: Drop linux/bitops.h from common headerSimon Glass2020-05-183-0/+7
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop log.h from common headerSimon Glass2020-05-183-0/+3
| | | | | | | | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop init.h from common headerSimon Glass2020-05-183-0/+3
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop image.h from common headerSimon Glass2020-05-183-0/+3
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop net.h from common headerSimon Glass2020-05-183-0/+3
|/ | | | | | | | | | | Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: K3: Increase default SYSFW image size allocationAndrew F. Davis2020-05-111-1/+1
| | | | | | | | | The memory allocated to store the FIT image containing SYSFW and board configuration data is statically defined to the largest size expected. Some additions to the board configuration data has pushed us slightly over the current defined size on some HS devices, expand to 278000. Signed-off-by: Andrew F. Davis <afd@ti.com>
generated by cgit (git 2.34.1) at 2024-09-22 14:35:59 +0000