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* pinctrl: at91-pio4: add support for slew-rateClaudiu Beznea2021-03-021-0/+1
| | | | | | | | | SAMA7G5 supports slew rate configuration. Adapt the driver for this. For switching frequencies lower than 50MHz the slew rate needs to be enabled. Since most of the pins on SAMA7G5 fall into this category enabled the slew rate by default. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* sam9x60.h: Fix Galois Field Table offsetsKai Stuhlemmer (ebee Engineering)2021-01-221-2/+2
| | | | | | | | | | | Because ATMEL_BASE_ROM is defined to 0x100000, it already points to the begin of the index table for 512 byte sectors correction. Thus its offset must be zero and the index of the table for 1024 byte sectors must start at offset 0x8000. Signed-off-by: Kai Stuhlemmer (ebee Engineering) <kai.stuhlemmer@ebee.de> [ta: update commit message] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* sama5d3: Fix Galois Field Table offsetsTudor Ambarus2021-01-221-2/+2
| | | | | | | | | | | | Offsets are described in the datasheet at section: "11.4.4.2 NAND Flash Boot: PMECC Error Detection and Correction". For testing I "injected" bit flips into u-boot NAND memory area, and then read back. PMECC could not correct the errors. With the offsets updated everything is fine. Fixes: 3225f34e5c ("ARM: atmel: add sama5d3xek support") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* pinctrl: at91-pio4: implement drive strength supportEugen Hristev2021-01-221-0/+1
| | | | | | | Implement drive strength support, by preserving the same bindings as in Linux. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
* dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass2020-12-132-2/+2
| | | | | | | Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
* ARM: at91: Add chip ID for SAM9X60 SiPNicolas Ferre2020-10-191-0/+3
| | | | | | SAM9X60 SiP (System in Package) are added for SoC identification. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
* ARM: mach-at91: add support for new SoC sama7g5Eugen Hristev2020-09-252-0/+76
| | | | | | Add support for new SoC sama7g5 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
* board: atmel: common: introduce at91_set_eth1addr for second interfaceEugen Hristev2020-09-221-0/+1
| | | | | | | | | | We already have a function to retrieve the mac address from one EEPROM. For boards with a second Ethernet interface, however, we would require another EEPROM with a second unique MAC address. Introduce at91_set_eth1addr which will look for a second EEPROM and set the 'eth1addr' variable with the obtained MAC address. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
* Convert CONFIG_AT91_GPIO to KconfigTom Rini2020-06-261-2/+0
| | | | | | | This converts the following to Kconfig: CONFIG_AT91_GPIO Signed-off-by: Tom Rini <trini@konsulko.com>
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-183-0/+3
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge tag 'u-boot-atmel-2020.04-a' of ↵Tom Rini2020-01-071-0/+1
|\ | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel features for 2020.04 cycle This feature set is a patch series from Tudor Ambarus which includes parsing of the spi flash SFDP parser for SST flashes, and using those tables to retrieve unique saved per device MAC address. This is then used as base mac address on the SAMA5D2 Wireless SOM EK board.
| * board: atmel: sama5d27_wlsom1_ek: Set ethaddr from spi-nor flashTudor Ambarus2019-12-171-0/+1
| | | | | | | | | | | | | | | | | | The SST26VF064BEUI spi-nor flash is programmed at the factory with a globally unique address stored in the SFDP vendor parameter table and it is permanently writeprotected. Retrieve the EUI-48 address and set it as ethaddr env. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* | dm: gpio: Allow control of GPIO uclass in SPLSimon Glass2019-12-151-1/+1
|/ | | | | | | | | | | | | | | | | | | | At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* ARM: at91: Add SFR definitionsTudor Ambarus2019-10-081-3/+45
| | | | | | | | sama5's SFR has at offset 0x04 the DDR Configuration Register, while sam9x60's SFR contains the EBI Chip Select Register. Add a union to reconcile both boards. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* ARM: at91: Rename sama5_sfr.h to at91_sfr.hTudor Ambarus2019-10-081-2/+2
| | | | | | | The Special Function Registers (SFR) are present in sam9x5 and sam9x60 too, rename sama5_sfr to at91_sfr.h. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* ARM: at91: Add sam9x60 socSandeep Sheriker Mallikarjun2019-10-082-0/+171
| | | | | | | | Add new Microchip sam9x60 SoC based on an ARM926. Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com> [tudor.ambarus@microchip.com: fix SFR definition] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* ARM: at91: mpddrc: add lpddr2 initialization procedureEugen Hristev2019-10-081-0/+23
| | | | | | | Implement the lpddr2 initialization procedure for at91 mpddrc multi-port ddram controller. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
* ARM: at91: sfr: implement DDR input buffers open functionEugen Hristev2019-10-081-0/+3
| | | | | | | | Add a function in SFR implementation that will open the DDR input buffers. This can be called at DRAM initialization time. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
* ARM: at91: Add the chip ID for SAMA5D2 LPDDR2 SiPNicolas Ferre2019-10-081-0/+4
| | | | | | | The SAMA5D2 LPDDR2 SiP (System in Package) is added for SoC identification. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
* Convert CONFIG_ARCH_CPU_INIT to KconfigAdam Ford2019-08-251-1/+0
| | | | | | | | | This converts the following to Kconfig: CONFIG_ARCH_CPU_INIT Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Tested-by: Felix Brack <fb@ltec.ch>
* watchdog: at91sam9_wdt: Remove now superfluous wdt start and resetStefan Roese2019-04-261-2/+0
| | | | | | | | | | | | | With the new generic function, the scattered other functions are now removed to be replaced by the generic one. The new version also enables the configuration of the watchdog timeout via the DT "timeout-sec" property (if enabled via CONFIG_OF_CONTROL). The watchdog servicing is enabled via CONFIG_WATCHDOG. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com>
* arm: at91: Enable watchdog supportStefan Roese2019-04-091-0/+10
| | | | | | | | | | | | This patch enables and starts the watchdog on the AT91 platform if configured. The WD timeout value is read in the AT91 WD device driver from the DT, using the "timeout-sec" DT property. If not provided in the DT, the default value of 2 seconds is used. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com>
* ARM: at91: sama5d2: Wrap cpu detection to fix macb driverAlexander Dahl2019-04-091-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When introducing the SAMA5D27 SoCs, the SAMA5D2 series got an additional chip id. The check if the cpu is sama5d2 was changed from a preprocessor definition (inlining a call to 'get_chip_id()') to a C function, probably to not call get_chip_id twice? That however broke a check in the macb ethernet driver. That driver is more generic and also used for other platforms. I suppose this solution was implemented to use it in 'gem_is_gigabit_capable()', without having to stricly depend on the at91 platform: #ifndef cpu_is_sama5d2 #define cpu_is_sama5d2() 0 #endif That only works as long as cpu_is_sama5d2 is a preprocessor definition. (The same is still true for sama5d4 by the way.) So this is a straight forward fix for the workaround. The not working check on the SAMA5D2 CPU lead to an issue on a custom board with a LAN8720A ethernet phy connected to the SoC: => dhcp ethernet@f8008000: PHY present at 1 ethernet@f8008000: Starting autonegotiation... ethernet@f8008000: Autonegotiation complete ethernet@f8008000: link up, 1000Mbps full-duplex (lpa: 0xffff) BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 BOOTP broadcast 4 BOOTP broadcast 5 BOOTP broadcast 6 BOOTP broadcast 7 BOOTP broadcast 8 BOOTP broadcast 9 BOOTP broadcast 10 BOOTP broadcast 11 BOOTP broadcast 12 BOOTP broadcast 13 BOOTP broadcast 14 BOOTP broadcast 15 BOOTP broadcast 16 BOOTP broadcast 17 Retry time exceeded; starting again Notice the wrong reported link speed, although both SoC and phy only support 100 MBit/s! The real issue on reliably detecting the features of that cadence ethernet mac IP block, is probably more complicated, though. Fixes: 245cbc583d ("ARM: at91: Get the Chip ID of SAMA5D2 SiP") Signed-off-by: Alexander Dahl <ada@thorsis.com>
* arm: at91: wdt: Convert watchdog driver to dm/dtPrasanthi Chellakumar2018-11-161-1/+5
| | | | | | | | Convert the Watchdog driver for AT91SAM9x processors to support the driver model and device tree. Changes "CONFIG_AT91SAM9_WATCHDOG" to new "CONFIG_WDT_AT91" Kconfig option. Signed-off-by: Prasanthi Chellakumar <prasanthi.chellakumar@microchip.com>
* gpio: atmel_pio4: give a full configuration when muxing pinsLudovic Desroches2018-05-081-8/+8
| | | | | | | | When a pin is muxed to a peripheral or as a GPIO, the only configuration that can be set is the pullup. It is too restrictive so this patch allows to give a full configuration. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
* gpio: atmel_pio4: add drive strength macrosLudovic Desroches2018-05-081-0/+4
| | | | | | Macros for drive strength configuration were missing. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-0749-98/+49
| | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
* clk: at91: add USB Host clock driverWenyou Yang2018-03-161-0/+6
| | | | | | | | Add USB clock driver to configure the input clock and the divider in the PMC_USB register to generate a 48MHz and a 12MHz signal to the USB Host OHCI. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* board: laird: add WB45N CPU moduleBen Whitten2017-11-291-0/+2
| | | | | | | | | | | | This board is based on the Atmel 9x5 eval board. Supporting the following features: - Boot from NAND Flash - Ethernet - FIT - SPL Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com> Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>
* ARM: at91: add sama5d2 smc headerLudovic Desroches2017-11-291-0/+76
| | | | | | | | | Add a header for SAMA5D2 SMC since it's not compatible with SAMA5D3 one. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> [wenyou: fix the wrong base address of the SMC register] Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* ARM: at91: Move CONFIG_AT91FAMILY option to KconfigWenyou Yang2017-09-1410-43/+0
| | | | | | | Move the CONFIG_AT91FAMILY option from include/mach/<soc>.h header file to Kconfig. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* ARM: at91: Get the Chip ID of SAMA5D2 SiPWenyou Yang2017-09-141-1/+6
| | | | | | | | The SAMA5D2 SiP(System in Package) has different Chip IDs in the CHIPID and CHIP_EXID registers. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: at91: mach: Add missing defines of MPDDRCWenyou Yang2017-09-141-0/+4
| | | | | | | Add missing defines of Multiport DDR-SDRAM Controller (MPDDRC). Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: at91: spl: Add mck function to lower rate while switchingWenyou Yang2017-09-141-0/+1
| | | | | | | | | | | | | | | Refer to the commit 70f8c8316ad(PMC: add new mck function to lower rate while switching) from AT91Bootstrap. While switching to a lower clock source, we must switch the clock source first instead of last. Otherwise, we could end up with too high frequency on internal bus and peripherals. This happens on SAMA5D2 as exitting from the ROM code. Add a function pmc_mck_init_down() to allow this sequence. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: at91: spl: Adjust switching to oscillator for SAMA5D2Wenyou Yang2017-09-141-0/+2
| | | | | | | | | As said in 29.5.7 section of SAMA5D2 datasheet, before switching to the crystal oscillator, a check must be carried out to ensure that the oscillator is present and that its freqency is valid. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* atmel: common: Add function to display via DM_VIDEO's APIWenyou Yang2017-09-141-0/+1
| | | | | | | | | Add a function to display the company's logo and board information via the API from DM_VIDEO. This function can be shared by other atmel boards, so locate it in board/atmel/common folder. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: at91: utmi: Set the reference clock frequencyWenyou Yang2017-09-141-0/+5
| | | | | | | | | | | | | | | | | | | By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way. The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz. The patch is cloned from the patch of mailing-list: [PATCH v2] clk: at91: utmi: set the mainck rate Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> [trini: Depend on SPL_DM] Signed-off-by: Tom Rini <trini@konsulko.com>
* board: atmel: Create board/$(VENDOR)/common folderWenyou Yang2017-09-111-0/+2
| | | | | | | | | Create board/$(VENDOR)/common folder to accommodate the common code shared by other atmel boards, now put the code to set ethernet mac address from eeprom, which uses the i2c eeprom driver. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* board: sama5d4ek: fix DD2 configurationWenyou Yang2017-05-091-1/+6
| | | | | | Fix the DDR2 configuration to make SPL work. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
* pinctrl: at91: add pinctrl driverWenyou Yang2017-04-131-1/+5
| | | | | | | | | | | | | | AT91 PIO controller is a combined gpio-controller, pin-mux and pin-config module. The peripheral's pins are assigned through per-pin based muxing logic. Each SoC will have to describe the its limitation and pin configuration via device tree. This will allow to do not need to touch the C code when adding new SoC if the IP version is supported. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* gpio: at91_gpio: remove CPU_HAS_PIO3 macroWenyou Yang2017-04-134-35/+34
| | | | | | | | | | | The intention of the removal is the preparation to introduce the new AT91 PIO pinctrl driver. Use the union to make the PIO3 and PIO2's registers be together and make their offset aligned. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: at91: gpio: fix at91_set_gpio_value() defineWenyou Yang2017-04-131-7/+5
| | | | | | | | | | | | | | | | When the CONFIG_ATMEL_LEGACY is undefined, according to the following defines, at91_set_gpio_value() references to at91_set_pio_value(x, y) with two parameters. #define at91_set_gpio_value(x, y) at91_set_pio_value(x, y) #define at91_get_gpio_value(x) at91_get_pio_value(x) But there isn't the implementation of at91_set_pio_value(x, y) with two parameters in U-Boot. This is an error. Same as at91_get_gpio_value(x) define. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: at91: mpddrc: add missing MPDDRC_MD definesHeiko Schocher2016-10-281-0/+3
| | | | | | | | add missing MPDDRC_MD defines Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-231-1/+1
| | | | | | | | | | | Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
* gpio: atmel_pio4: Move PIO4 definitions to head fileWenyou Yang2016-08-151-0/+35
| | | | | | | | | In order to make these PIO4 definitions shared with AT91 PIO4 pinctrl driver, move them from the existing gpio driver to the head file, and rephrase them. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: at91: Add clock driverWenyou Yang2016-08-151-3/+8
| | | | | | | | The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: at91: add CONFIG_AT91SAM9M10G45Heiko Schocher2016-06-261-12/+14
| | | | | | | add support for CONFIG_AT91SAM9M10G45. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* ARM: at91: Fix PMC bit definitionsMarek Vasut2016-06-121-8/+8
| | | | | | | Add missing parenthesis around the variable into the macro. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com>
* ARM: at91: sama5: Extend boot device autodetectionMarek Vasut2016-06-122-12/+25
| | | | | | | | | | | | Extend the boot device autodetection from SAMA5D2 only to the entire SAMA5Dx family of microcontrollers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [minor compile fix for SAMA5D2] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
* arm: at91: Add a header file for the real-time clockAndre Renaud2016-06-121-0/+71
| | | | | | | | | | Add register definitions for the AT91 RTC so that this can potentially be used in U-Boot. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
generated by cgit (git 2.34.1) at 2025-09-02 20:07:01 +0000