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* arm: Add support for Kobol Helios64 boardHEADmasterChristian Glombek2021-06-123-0/+1256
| | | | | | | | | | | | | | The hardware is described in detail on Kobol's wiki at https://wiki.kobol.io/helios64/intro/. This commit is based on downstream work in Armbian by Aditya Prayoga [1]. The devicetree is taken from Linux v5.12-rc1 and was originally submitted there by Uwe Kleine-Koenig [2]. [1] https://github.com/ukleinek/armbian-build/blob/35c85295d351830aa59b624db524ba04b238faae/patch/kernel/rockchip64-current/add-board-helios64.patch [2] https://github.com/torvalds/linux/blob/7a7fd0de4a9804299793e564a555a49c1fc924cb/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts Signed-off-by: Dennis Gilmore <dennis@ausil.us>
* arm: mvebu: dts: turris_mox: add nodes for SPI NOR partitionsMarek Behún2021-06-101-0/+31
| | | | | | | | Add nodes for SPI NOR partitions to the device tree of Turris MOX, as are in Linux' device tree. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* arm: mvebu: dts: turris_mox: add button and LED nodesMarek Behún2021-06-101-0/+24
| | | | | | | | | Add nodes for indicator LED and reset button so that board code can implement board factory reset mechanism. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
* arm: a37xx: pci: Increase PCIe MEM size from 16 MiB to 127 MiBPali Rohár2021-06-041-3/+10
| | | | | | | | | | | | For some configurations with more PCIe cards and PCIe bridges, 16 MiB of PCIe MEM space may not be enough. Since TF-A already allocates a 128 MiB CPU window for PCIe, and since IO port space is only 64 KiB in total, use all the remaining space (64 + 32 + 16 + 8 + 4 + 2 + 1 = 127 MiB) for PCIe MEM. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* arm: a37xx: pci: Fix DT compatible string to Linux' DT compatiblePali Rohár2021-06-041-1/+1
| | | | | | | | | | Change DT compatible string for A3700 PCIe from 'marvell,armada-37xx-pcie' to 'marvell,armada-3700-pcie' to make U-Boot A3700 PCIe DT node compatible with Linux' DT node. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* sunxi: Bring back SD card as MMC device 0Andre Przywara2021-05-311-0/+1
| | | | | | | | | | | | | | | | | | | | | Commit 2243d19e5618 ("mmc: mmc-uclass: Use dev_seq() to read aliases node's index") now actually enforces U-Boot's device enumeration policy, where explicitly named devices come first, then any other non-named devices follow, without filling gaps. For quite a while we have had an "mmc1 = &mmc2;" alias in our sunxi-u-boot.dtsi, which now leads to the problem that the SD card (which was always mmc device 0) now gets to be number 2. This breaks quite some boot scripts, including our own distro boot commands, and some other features looking at $mmc_bootdev, also fastboot. Just add an explicit mmc0 alias in the very same file to fix this and restore the old behaviour. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reported-by: Samuel Holland <samuel@sholland.org> Tested-by: Simon Baatz <gmbnomis@gmail.com>
* arm: dts: stm32mp157c-odyssey-som: enable the RNG1Grzegorz Szymaszek2021-05-281-0/+4
| | | | | | | | | | | | Enable the true random number generator. It can be used, for example, to generate partition UUIDs when partitioning with the gpt command. The generator is already enabled in the device trees of several other STM32MP1‐based boards, like DKx or DHCOM. Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* arm: dts: k3-am642-sk: Add sysreset controller nodeSuman Anna2021-05-271-0/+4
| | | | | | | | | | | | | The AM64x SoC uses a central Device Management and Security Controller (DMSC) processor that manages all the low-level device controls including the system-wide SoC reset. The system-wide reset is managed through the system reset driver. Add a sysreset controller node as a child of the dmsc node to enable the "reset" command from U-Boot prompt for the K3 AM642 SK. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* arm: dts: k3-am642-evm: Add sysreset controller nodeSuman Anna2021-05-271-0/+4
| | | | | | | | | | | | | The AM64x SoC uses a central Device Management and Security Controller (DMSC) processor that manages all the low-level device controls including the system-wide SoC reset. The system-wide reset is managed through the system reset driver. Add a sysreset controller node as a child of the dmsc node to enable the "reset" command from U-Boot prompt for the K3 AM642 EVM. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* arm: dts: k3-j721e: Fix up MAIN R5FSS cluster mode back to Split-modeSuman Anna2021-05-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The default U-Boot environment variables and design are all set up for both the MAIN R5FSS clusters to be in Split-mode. This is the setting in v2021.01 U-Boot and the dt nodes are synched with the kernel binding property names in commit 468ec2f3ef8f ("remoteproc: k3_r5: Sync to upstreamed kernel DT property names") merged in v2021.04-rc2. The modes for both the clusters got switched back to LockStep mode by mistake in commit 70e167495ab2 ("arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into U-Boot") also in v2021.04-rc2. This throws the following warning messages when early-booting the cores using default env variables, k3_r5f_rproc r5f at 5d00000: Invalid op: Trying to start secondary core 7 in lockstep mode Load Remote Processor 3 with data at addr=0x82000000 98484 bytes: Failed! k3_r5f_rproc r5f at 5f00000: Invalid op: Trying to start secondary core 9 in lockstep mode Load Remote Processor 5 with data at addr=0x82000000 98484 bytes: Failed! Fix this by switching back both the clusters to the expected Split-mode. Make this mode change in the u-boot specific dtsi file to avoid such sync overrides in the future until the kernel dts is also switched to Split-mode by default. Fixes: 70e167495ab2 ("arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into U-Boot") Reported-by: Minas Hambardzumyan <minas@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* arm: mvebu: armada-3720-uDPU.dts: Change back to phy-mode "2500base-x"Stefan Roese2021-05-201-2/+2
| | | | | | | | | | | | | With commit 8678776df6f5 (arm: mvebu: armada-3720-uDPU: fix PHY mode definition to sgmii-2500) the PHY mode was switch to "sgmii-2500", even when this is functionally incorrect since "2500base-x" was not supported in U-Boot at that time. As this mode is now supported (at least present in the headers), this patch moves back to the orinal version. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jakov Petrina <jakov.petrina@sartura.hr> Cc: Vladimir Vid <vladimir.vid@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm64: zynqmp: Add description for SOM/Kria boardsMichal Simek2021-05-197-0/+1109
| | | | | | | | | | | | The patch contains several DT files for SOM platform. Carrier card is sck-kv (KV260) revA/B. SMK-K26 is description for starter kit which doesn't have EMMC populated. And SM-K26 is full som with EMMC. Files are divided in this way to make sure that SOM can be plugged to different carrier card and all peripherals on SOM (or defined by a spec) can be used by U-Boot. Full DT for SOM+CC can be merged together as overlays. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add psgtr DT descriptionsMichal Simek2021-05-1910-1/+79
| | | | | | | | | Mainline kernel has psgtr driver that's why it is good to add description to DT files. Some boards are just missing description for USB3 and sata. zc1751-dc1 and p-a2197 are also missing clock descriptions for input clocks. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add pinctrl descriptionMichal Simek2021-05-1911-1/+2470
| | | | | | | ZynqMP pinctrl Linux driver has been merged to 5.13-rc1 kernel. Based on it DT files can be extended by pinctrl configurations. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add zynqmp firmware specific DT nodesT Karthik Reddy2021-05-192-0/+80
| | | | | | | Probe zynqmp firmware driver by adding zynqmp firmware, power & ipi mailbox device tree nodes for mini emmc. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
* arm64: zynqmp: Add missing mio-bank properties to sdhciMichal Simek2021-05-191-0/+1
| | | | | | | | | Add missing xlnx,mio-bank property to sdhci node. Also add properties with 0 value to have it listed in case that files are copied to different projects where default case doesn't need to be handled in the same way. That's why explicitly list them too. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Remove comment about clock chipsMichal Simek2021-05-192-10/+10
| | | | | | These comments weren't push to mainline that's why remove them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add 'i2c-mux-idle-disconnect' propertyRaviteja Narayanam2021-05-193-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | I2C muxes that have the slave devices with same address are falling into the below problem. VCK190 system controller (SC) - zynqmp-e-a2197-00-revA.dts I2C1 (0xff030000) -> Mux1 (@0x74) -> Channel 3 -> 0x50 I2C1 (0xff030000) -> Mux2 (@0x75) -> Channel 0 -> 0x50 1. SC accesses I2C1 - Mux1 (0x74) - Channel 3 and then 2. SC accesses I2C1 - Mux2 (0x75) - Channel 0. Now it results in 2 slave devices with same address (0x50) on the I2C bus, making the communication un-reliable. When ' i2c-mux-idle-disconnect' is in DT, after '1', the Mux channel output is disconnected, making none of the channels available to the I2C1. So, there is no question of having the same addressed slave (0x50) present on the bus when we are doing '2'. Same pattern is seen in below two boards also. ZCU208 - zynqmp-zcu208-revA.dts ZCU216 - zynqmp-zcu216-revA.dts Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
* arm64: zynqmp: Add label to all GPIO lines for VCK190 SCSaeed Nowshadi2021-05-191-7/+7
| | | | | | | | | | | | Add label to GPIO lines so the user-level applications can find any line without knowing its physical path on System Controller on VCK190/VMK180. These labels are describing EMIO gpio connection which depends on PL which we normally don't describe but that's only way to go for now. Lately this should be done out of this source code. Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add 'silabs,skip-recall' to DDR DIMM si570 clk nodeSaeed Nowshadi2021-05-191-1/+2
| | | | | | | | The 'silabs,skip-recall' property prevents interruption in operation of the clock while the driver is being probed. Without this property, the DDR DIMM clk can cause a failure during Versal's boot. Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
* arm64: zynqmp: Add missing silabs,skip-recall for si570 ref clk nodesMichal Simek2021-05-195-3/+8
| | | | | | | | | All si570 which are used for ps reference clock generation should contain silabs,skip-recall property not to cause break on ps clock. On Versal boards this will cause hang on Versal cpu when it is booted at the same time with SC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN913x DBKonstantin Porotchkin2021-05-1611-0/+1004
| | | | | | | | | This patch adds the dtsi/dts files needed to support the Marvell Octeon TX2 CN913x DB. This is only the base port with not all interfaces supported fully. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ARM: dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-ProNeil Armstrong2021-05-142-0/+14
| | | | | | | This lacks the right u-boot specific DT include to make HDMI work. Reported-by: B1oHazard <ty3uk@mail.ua> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* Merge tag 'ti-v2021.07-rc3' of ↵Tom Rini2021-05-1214-0/+8447
|\ | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-ti - Initial support for AM64 EVM and SK - K3 DDR driver unification for J7 and AM64 platforms. - Minor fixes for TI clock driver
| * ARM: dts: k3-am642-sk: Add ethernet related DT nodesVignesh Raghavendra2021-05-122-0/+78
| | | | | | | | | | | | | | Add CPSW related nodes for AM642 SK. There are two CPSW ports on the board but U-Boot supports only the first port. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * ARM: dts: k3-am64-main: Add CPSW DT nodesVignesh Raghavendra2021-05-124-0/+185
| | | | | | | | | | | | | | | | | | AM64 as CPSW3G IP with 2 external ports. Add DT entries for the same (based on kernel DT). Disable second port as its by default set to ICSS usage on EVM. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * arm: dts: am642-r5-sk: Add r5 specific dtsLokesh Vutla2021-05-123-1/+2337
| | | | | | | | | | | | | | Add R5 specific dts for AM64 SK Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
| * arm: dts: am642-sk: Add initial sk dtsLokesh Vutla2021-05-123-1/+183
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM642 StarterKit (SK) board is a low cost, small form factor board designed for TI’s AM642 SoC. It supports the following interfaces: * 2 GB LPDDR4 RAM * x2 Gigabit Ethernet interfaces capable of working in switch and MAC mode * x1 USB 3.0 Type-A port * x1 UHS-1 capable µSD card slot * 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837 * 512 Mbit OSPI flash * x2 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * 40-pin Raspberry Pi compatible GPIO header * 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO) * 54-pin header for Programmable Realtime Unit (PRU) IO pins * Interface for remote automation. Includes: * power measurement and reset control * boot mode change Add basic support for AM642 SK. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: dts: am642-evm: Add I2C nodesLokesh Vutla2021-05-123-0/+64
| | | | | | | | | | | | Add I2C nodes for AM64 and enable pinmux for i2c0 for reading eeprom data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: dts: k3-am642-r5-evm: Do not use power-domains for I2CLokesh Vutla2021-05-121-0/+5
| | | | | | | | | | | | | | I2C EEPROM will be probed before SYSFW is available. So drop the power-domains property for I2C. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: dts: k3-am64-evm: Make chip id available before pre-relocLokesh Vutla2021-05-121-0/+7
| | | | | | | | | | | | | | Chipid will be needed for SoC detection for all stages of U-Boot. So make it u-boot,dm-spl Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: dts: k3-am642-r5-evm: Add GPIO DDR VTT regulatorNishanth Menon2021-05-121-0/+28
| | | | | | | | | | | | | | Add DDR VTT regulator. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: dts: k3-am64-main: Add GPIO nodesNishanth Menon2021-05-121-0/+44
| | | | | | | | | | | | | | Add main domain GPIO nodes. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: dts: k3-am642: Add ddr nodeDave Gerlach2021-05-123-0/+4394
| | | | | | | | | | | | | | | | | | Introduce ddr node for am642 needed for all ddr configurations. Also, introduce the 1600MTs DDR4 configuration that is supported on the am642-evm. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: dts: k3-am642: Add r5 specific dt supportDave Gerlach2021-05-123-1/+229
| | | | | | | | | | | | Add initial support for dt that runs on r5. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: dts: k3-am642: Add initial support for EVMDave Gerlach2021-05-122-0/+247
| | | | | | | | | | | | | | | | | | | | The AM642 EValuation Module (EVM) is a board that provides access to various peripherals available on the AM642 SoC, such as PCIe, USB 2.0, CPSW Ethernet, ADC, and more. Add basic support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: dts: ti: Add Support for AM642 SoCDave Gerlach2021-05-124-0/+649
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Introduce basic support for the AM642 SoC to enable SD/MMC boot. Introduce a limited set of MAIN domain peripherals under cbass_main and a set of MCU domain peripherals under cbass_mcu. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* | ARM:imx:imx8mq-cm: Add support for Ronetix iMX8MQ-CMIlko Iliev2021-05-023-0/+647
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Supported peripherals: Ethernet, eMMC, Serial. U-Boot SPL 2021.04-00911-g5fa1e2ffeb-dirty (Apr 23 2021 - 09:11:14 +0200) Normal Boot Trying to boot from MMC2 U-Boot 2021.04-00911-g5fa1e2ffeb-dirty (Apr 23 2021 - 09:11:14 +0200) CPU: Freescale i.MX8MQ rev2.1 at 1000 MHz Reset cause: POR Model: Ronetix iMX8M-CM SoM DRAM: 1 GiB WDT: Started with servicing (60s timeout) MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: Warning: ethernet@30be0000 (eth0) using random MAC address - 42:0d:e7:78:da:53 eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 u-boot=> Signed-off-by: Ilko Iliev <iliev@ronetix.at>
* | imx: Add support for Ronetix's iMX7-CM boardIlko Iliev2021-05-023-0/+450
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Console boot log: U-Boot SPL 2021.04-00836-ga6232e065d-dirty (Apr 16 2021 - 15:16:35 +0200) Trying to boot from MMC1 U-Boot 2021.04-00836-ga6232e065d-dirty (Apr 16 2021 - 15:16:35 +0200) CPU: Freescale i.MX7D rev1.3 1000 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 44C Reset cause: POR Model: Ronetix iMX7-CM Board Board: iMX7-CM DRAM: 512 MiB PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11 MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: Warning: ethernet@30be0000 (eth0) using random MAC address - fe:be:37:01:5a:3f eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 Signed-off-by: Ilko Iliev <iliev@ronetix.at>
* | arm: dts: add imx8mm-cl-iot-gate dts fileYing-Chun Liu (PaulLiu)2021-05-023-0/+810
| | | | | | | | | | | | | | | | | | | | Add board dts for imx8mm-cl-iot-gate Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il> Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Signed-off-by: Valentin Raevsky <valentin@compulab.co.il> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Peter Robinson <pbrobinson@gmail.com>
* | arm: dts: imx6qdl-gw552x.dtsi: fix VBUS supplyTim Harvey2021-05-021-1/+0
| | | | | | | | | | | | | | | | | | | | Remove the invalid 'regulator-always-on' property to resolve: starting USB... Bus usb@2184000: Error enabling VBUS supply (ret=-13) probe failed, error -13 Bus usb@2184200: USB EHCI 1.00 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | board: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0Jagan Teki2021-05-023-0/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier board. Genaral features: - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. i.Core MX8M Mini needs to mount on top of this Carrier board for creating complete i.Core MX8M Mini C.TOUCH 2.0 board. Linux dts commit details: commit <a142252061ff> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0") Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* | board: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter KitJagan Teki2021-05-024-0/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board. Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Mini PCIe - MIPI CSI - 2x CAN - Audio Out i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. i.Core MX8M Mini needs to mount on top of this Evaluation board for creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit. Linux dts commit details: commit <051c08eea682> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit") Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* | arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoMJagan Teki2021-05-021-0/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. General features: - NXP i.MX8M Mini - Up to 2GB LDDR4 - 8/16GB eMMC - Gigabit Ethernet - USB 2.0 Host/OTG - PCIe Gen2 interface - I2S - MIPI DSI to LVDS - rest of i.MX8M Mini features i.Core MX8M Mini needs to mount on top of Engicam baseboards for creating complete platform solutions. Linux dts commit details: commit <470d6dad5ddd> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM") Add support for it. Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* | arm64: dts: imx8mm: Add common -u-boot.dtsiJagan Teki2021-05-027-209/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | /soc@0 aips1 aips2 aips3 clk iomuxc osc_24m are common node enablements across imx8mm platform for dm-spi, dm-pre-reloc stages. Move them into common dtsi, imx8mm-u-boot.dtsi Cc: Tim Harvey <tharvey@gateworks.com> Cc: Adam Ford <aford173@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Teresa Remmet <t.remmet@phytec.de> Cc: Igor Opaniuk <igor.opaniuk@toradex.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* | board: ge: bx50v3: add phy reset GPIOSebastian Reichel2021-05-021-0/+12
|/ | | | | | | | | | | | Add PHY's reset GPIO, so that U-Boot does a PHY hard reset. This is needed, since the PHY might become unresponsive if watchdog reboots the system while a transaction is ongoing. The reset GPIO is added to the U-Boot specific DT files, since the kernel does not setup the reserved registers correctly after resetting the PHY and thus must not reset it. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
* phy: marvell: add support for SFI1Igal Liberman2021-04-297-11/+12
| | | | | | | | | | | | | | | In CP115, comphy4 can be configured into SFI port1 (in addition to SFI0). This patch adds the option described above. In addition, rename all existing SFI/XFI references: COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0 No functional change for exsiting configuration. Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0 Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
* phy: marvell: fix pll initialization for second utmi portGrzegorz Jaszczyk2021-04-291-15/+21
| | | | | | | | | | | | | | | | | According to Design Reference Specification the PHY PLL and Calibration register from PHY0 are shared for multi-port PHY. PLL control registers inside other PHY channels are not used. This commit reworks utmi device tree nodes in a way that common PHY PLL registers are moved to main utmi node. Accordingly both child nodes utmi-unit range is reduced and register offsets in utmi_phy.h are updated to this change. This fixes issues in scenarios when only utmi port1 was in use, which resulted with lack of correct pll initialization. Change-Id: Icc520dfa719f43a09493ab31f671efbe88872097 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
* phy: marvell: cp110: remove unused definitionsMarcin Wojtas2021-04-291-1/+1
| | | | | | | | | | | | Even if comphy types of SATA2/SATA3/SGMII3 and comphy speeds of 1.5G/3G/6.25G were referenced in the driver non configuration (dts) was using it. This patch removes unused definitions. Change-Id: I53ed6f9d3a82b9d18cb4e488bc14d3cf687f9488 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
* phy: marvell: rename comphy related definitions to COMPHY_XXIgal Liberman2021-04-2912-122/+124
| | | | | | | | | | | | | | | Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX. Those definition might be confused with MDIO PHY definitions. This patch does the following changes: - PHY_TYPE_XX --> COMPHY_TYPE_XX - PHY_SPEED_XX --> COMPHY_SPEED_XX This improves readability, no functional change. Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
generated by cgit (git 2.34.1) at 2025-01-11 04:48:09 +0000