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* armv8: SPL: discard relocation informationMarek Behún2021-05-241-0/+1
| | | | | | | | | | | | For some reason when building SPL for ARMv8 with LTO, the relocation information is not discarded. Discard it explicitly in the linker script. This fixes LTO build for imx8mm_venice_defconfig. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: kona: fix clk_bsc_enable() type mismatch for LTOMarek Behún2021-05-241-1/+1
| | | | | | | | | | | | | When building with LTO, the compiler complains about type mismatch of function clk_bsc_enable() in file: arch/arm/cpu/armv7/kona-common/clk-stubs.c vs other files that define or use this function: warning: type of ‘clk_bsc_enable’ does not match original declaration. Change the type of this function to that of the other usages. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* ARM: fix LTO for imx28_xeaMarek Behún2021-05-242-2/+2
| | | | | | | | | | | | When imx28_xea_defconfig is built with LTO, the compiler complains about the two different declarations of _start: include/asm-generic/sections.h as extern void _start(void); arch/arm/cpu/arm926ejs/mxs/mxs.c as extern uint32_t _start; Fix this. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* ARM: fix LTO build for some thumb-interwork casesMarek Behún2021-05-241-0/+2
| | | | | | | | | | | | Fix LTO build for some thumb-interwork usecases (such as for da850evm_defconfig), where inline assmebly such as mrc p15,0,r2,c1,c0,0 causes the compiler to fail during LTO linking with Error: selected processor does not support `mrc p15,0,r2,c1,c0,0' in Thumb mode Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: make gd a function call for LTO and set via set_gd()Marek Behún2021-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | On ARM, the gd pointer is stored in registers r9 / x18. For this the -ffixed-r9 / -ffixed-x18 flag is used when compiling, but using global register variables causes errors when building with LTO, and these errors are very difficult to overcome. Richard Biener says [1]: Note that global register vars shouldn't be used with LTO and if they are restricted to just a few compilation units the recommended fix is to build those CUs without -flto. We cannot do this for U-Boot since all CUs use -ffixed-reg flag. It seems that with LTO we could in fact store the gd pointer differently and gain performance or size benefit by allowing the compiler to use r9 / x18. But this would need more work. So for now, when building with LTO, go the clang way, and instead of declaring gd a global register variable, we make it a function call via macro. [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68384 Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org>
* treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún2021-05-243-4/+4
| | | | | | | | | | | | | | | | | This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Revert "spl: Drop bd_info in the data section"Alexandru Gagniuc2021-04-191-4/+1
| | | | | | | | | | | | | | | | | | | | | This reverts commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75. struct global_data contains a pointer to the bd_info structure. This pointer was populated spl_set_bd() to a pre-allocated bd_info in the ".data" section. The referenced commit replaced this mechanism to one that uses malloc(). That new mechanism is only used if SPL_ALLOC_BD=y. which very few boards do. The result is that (struct global_data)->bd is NULL in SPL on most platforms. This breaks falcon mode, since arch_fixup_fdt() tries to access (struct global_data)->bd and set the "/memory" node in the devicetree. The result is that the "/memory" node contains garbage values, causing linux to panic() as it sets up the page table. Instead of trying to fix the mess, potentially causing other issues, revert to the code that worked, while this change is reworked. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* Merge branch '2021-04-14-assorted-vboot-improvements'Tom Rini2021-04-151-9/+0
|\ | | | | | | | | | | - Add ECDSA support to FIT images - Improve FIT image loadables (incl fpga) support - Further FIT improvements with SPL
| * common: fit: Add weak board_fit_config_name_matchSean Anderson2021-04-141-9/+0
| | | | | | | | | | | | | | | | | | | | Several architectures had a default board_fit_config_name_match already; this provides a generic weak version. We default to rejecting all configs. This will use the FIT's default config, instead of the first config. This may result in boot failures if there are multiple configurations and the first config is *not* the default. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* | armv8: fsl-layerscape: spl: call spl_early_init()Michael Walle2021-04-151-0/+8
| | | | | | | | | | | | | | | | | | DM_SERIAL needs both the device tree as well as an early heap. Thus, we have to call spl_early_init() to initialize the memory allocator and the setup the device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | armv8: fsl-layerscape: spl: add debug UART supportMichael Walle2021-04-151-0/+3
|/ | | | | | | | | | | | | To use the debug UART we have to call debug_uart_init() in the SPL. Do so as soon as possible. As an example, here is how you can use it on a LS1028A SoC: CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0x21c0500 CONFIG_DEBUG_UART_CLOCK=200000000 Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* arm: Remove s32v234evb boardTom Rini2021-04-105-470/+1
| | | | | | | | This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Eddy Petrișor <eddy.petrisor@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* mmc: fsl_esdhc: add pulse width detection workaroundMichael Walle2021-04-061-0/+1
| | | | | | | | | | | HS400 mode on the LS1028A SoC isn't reliable. The linux driver has a workaroung for the pulse width detection. Apply this workaround in u-boot, too. This will make HS400 mode work reliably on the LS1028A SoC. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: fsl_esdhc: add workaround for erratum A-011334Michael Walle2021-04-061-0/+1
| | | | | | | LS1028A SoCs are restricted in what divider values are allowed for HS400 mode. This is basically a port from the corresponding linux driver. Signed-off-by: Michael Walle <michael@walle.cc>
* Merge tag 'v2021.04-rc4' into nextTom Rini2021-03-151-0/+10
|\ | | | | | | Prepare v2021.04-rc4
| * configs: fsl: move bootrom specific defines to KconfigRajesh Bhagat2021-03-051-0/+10
| | | | | | | | | | | | | | | | | | | | Moves below bootrom specific defines to Kconfig: CONFIG_SYS_FSL_BOOTROM_BASE CONFIG_SYS_FSL_BOOTROM_SIZE Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | arm: cp15: remove weak function arm_init_domainsPatrick Delaunay2021-03-021-3/+0
| | | | | | | | | | | | | | Remove the unused weak function arm_init_domains used to change the DACR value. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* | reset: Remove addr parameter from reset_cpu()Harald Seiler2021-03-0219-22/+22
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* image: Adjust the workings of fit_check_format()Simon Glass2021-02-151-1/+1
| | | | | | | | | | | | | | | | | At present this function does not accept a size for the FIT. This means that it must be read from the FIT itself, introducing potential security risk. Update the function to include a size parameter, which can be invalid, in which case fit_check_format() calculates it. For now no callers pass the size, but this can be updated later. Also adjust the return value to an error code so that all the different types of problems can be distinguished by the user. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Bruce Monroe <bruce.monroe@intel.com> Reported-by: Arie Haenel <arie.haenel@intel.com> Reported-by: Julien Lenoir <julien.lenoir@intel.com>
* Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini2021-02-1534-1/+33
|\ | | | | | | - Merge the patch to take <asm/global_data.h> out of <common.h>
| * common: Drop asm/global_data.h from common headerSimon Glass2021-02-0234-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | arm: Remove ls2080a_simu boardTom Rini2021-02-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it. Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | armv7: ls102xa: Enable I-Cache to speed up the boot timeHou Zhiqiang2021-02-081-0/+2
|/ | | | | | | | | Enable the I-Cache to speed up the boot time, especailly for the NOR boot, currently it takes about 15 seconds from power up to the U-Boot prompt, and with the I-Cache enabled it only takes around 2.5 seconds. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* arm: Remove #include <version.h> from armv8/fwcall.cPali Rohár2021-02-011-1/+0
| | | | | | | | | No version information is used in armv8/fwcall.c therefore do not include version.h header file. This change prevents recompiling fwcall.o when SOURCE_DATE_EPOCH changes. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* sunxi: Add H616 FEL supportJernej Skrabec2021-01-251-1/+4
| | | | | | | | H616 uses different address for reset. Add it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* armv8: Makefile: build cache files when neededPeng Fan2021-01-161-1/+3
| | | | | | If no need cache support, not build the cache files, such as in SPL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* sunxi: Add arm64 FEL supportAndre Przywara2021-01-112-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far we did not support the BootROM based FEL USB debug mode on the 64-bit builds for Allwinner SoCs: The BootROM is using AArch32, but the SPL runs in AArch64. Returning back to AArch32 was not working as expected, since the RMR reset into 32-bit mode always starts execution in the BootROM, but not in the FEL routine. After some debug and research and with help via IRC, the CPU hotplug mechanism emerged as a solution: If a certain R_CPUCFG register contains some magic, the BootROM will immediately branch to an address stored in some other register. This works well for our purposes. Enable the FEL feature by providing early AArch32 code to first save the FEL state, *before* initially entering AArch64. If we eventually determine that we should return to FEL, we reset back into AArch32, and use the CPU hotplug mechanism to run some small AArch32 code snippet that restores the initially saved FEL state. That allows the normal AArch64 SPL build to be loaded via the sunxi-fel tool, with it returning into FEL mode, so that other payloads can be transferred via FEL as well. Tested on A64, H5 and H6. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Priit Laes <plaes@plaes.org> (on Olimex A64-Olinuxino)
* Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini2021-01-052-1/+8
|\ | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
| * dm: Use access methods for dev/uclass private dataSimon Glass2021-01-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
| * spl: Drop bd_info in the data sectionSimon Glass2021-01-051-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | This uses up space in the SPL binary but it always starts as zero. Also some boards cannot support data in TPL (e.g. Intel Apollo Lake). Use malloc() to allocate this structure instead, by moving the init a little later, after malloc() is inited. Make this function optional since it pulls in malloc(). This reduces the TPL binary size on coral by about 64 bytes Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge tag 'v2021.01-rc5' into nextTom Rini2021-01-0511-48/+147
|\ \ | |/ |/| | | | | | | Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
| * arm: ls102xa: select USB PHY erratum's only if USB is enabledAleksandar Gerasimovski2020-12-101-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | The USB support is not by default enabled on all designs, so it does not make seance to have USB specific erratum's enabled on such a designs. On our internal Hitachi-Powergrids design not using the USB controller there is a crash when accessing those specific memory locations selected by the erratum flags. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * armv8: fsl-layerscape: Fix automatic setting of bootmcd with TF-AAlban Bedel2020-12-101-23/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting from TF-A there is a logic that attempt to detect if the default environment is used, if this is the case it then set the `bootcmd` and `mcinitcmd` depending of the device we booted from. This detection logic is dubious as it access internals of the env implementation and it doesn't always work correctly. First of all it detect any valid environment as not being the default, so after running `env default -a && saveenv` the board doesn't boot anymore as `bootcmd` is then empty. But it also fails in some other ways, for example it always detect a default environment when redundant env is enabled on MMC, so in that case `bootcmd` is overwritten on every boot. Instead of increasing the complexity of the detection just check if `bootcmd` and `mcinitcmd` are set in the environment and set them if they are not. Signed-off-by: Alban Bedel <alban.bedel@aerq.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * layerscape: fdt.c: Check for NULL return value from fdt_getprop()Priyanka Singh2020-12-101-4/+6
| | | | | | | | | | | | | | | | | | Check for NULL return value from fdt_getprop() in fdt_fixup_remove_jr() Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> [Fixed checkpatch errors/warnings] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * armv8: lx2162a: Add Soc changes to support LX2162AMeenakshi Aggarwal2020-12-109-17/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* | armv8: layerscape: don't initialize GIC in SPLMichael Walle2020-12-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The BL31 expects the GIC to be uninitialized. Thus, if we are loading the BL31 by the SPL we must not initialize it. If u-boot is loaded by the SPL directly, it will initialize the GIC again (in the same lowlevel_init()). This was tested on a custom board with SPL loading the BL31 and jumping to u-boot as BL33 as well as loading u-boot directly by the SPL. In case the ATF BL1/BL2 is used, this patch won't change anything, because no SPL is used at all. Signed-off-by: Michael Walle <michael@walle.cc>
* | treewide: use CONFIG_IS_ENABLED() for ARMV8_SEC_FIRMWARE_SUPPORTMichael Walle2020-12-043-6/+6
|/ | | | | | | | There is SPL_ARMV8_SEC_FIRMWARE_SUPPORT and ARMV8_SEC_FIRMWARE_SUPPORT. Thus use CONFIG_IS_ENABLED() instead of the simple #ifdef. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Michal Simek <michal.simek@xilinx.com>
* armv8: layerscape: don't remove crypto node if just partially disabledMichael Walle2020-10-231-1/+40
| | | | | | | | | | | | | | On all newer Layerscape SoCs, only the export-controlled ciphers of the crypto module are disabled on non-E parts. Thus it doesn't make sense to completely remove the node. Linux will figure out what is there and what is not. Just remove it for older SoCs, where the module is indeed completely disabled on non-E parts. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* net: lx2160a.c: Update to set ECx_PMUX precedenceRazvan Ionut Cirjan2020-10-231-8/+8
| | | | | | | | | | | | As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* pci: layerscape: add a way of specifying additional iommu mappingsLaurentiu Tudor2020-10-231-0/+67
| | | | | | | | | | | | | | | | | | | In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add an u-boot env var and a device tree property (to be used for example in more static scenarios such as hardwired PCI endpoints that get initialized later in the system setup) that would allow two things: - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number of VFs that will ever be created for it - for hot-plug case, specify the B.D.F with which the device will show up on the PCI bus More details can be found in the included documentation: arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* arm: fsl-layerscape: Include device_compat.h in soc.cTom Rini2020-10-161-0/+1
| | | | | | Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
* arm64: PIE: Skip fixups if distance is zeroAndre Przywara2020-10-081-1/+2
| | | | | | | | | | | | | | When the actual offset between link and runtime address is zero, there is no need for patching up U-Boot early when running with CONFIG_POSITION_INDEPENDENT. Skip the whole routine when the distance is 0. This helps when U-Boot is loaded into ROM, or in otherwise sensitive memory locations. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Merge branch 'next'Tom Rini2020-10-052-3/+22
|\ | | | | | | | | | | | | Bring in the assorted changes that have been staged in the 'next' branch prior to release. Signed-off-by: Tom Rini <trini@konsulko.com>
| * arm64: Add support for larger PIE U-BootEdgar E. Iglesias2020-09-221-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linking a U-Boot larger than 1MB fails with PIE enabled: u-boot/arch/arm/cpu/armv8/start.S:71:(.text+0x3c): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__rel_dyn_end' defined in .bss_start section in u-boot. This extends the supported range by using adrp & add to load symbols early while starting up. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: Trap PIE builds early if load address is not 4K alignedEdgar E. Iglesias2020-09-221-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | PIE requires a 4K aligned load address. If this is not met, trap the startup sequence in a WFI loop rather than running into obscure failures. Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: André Przywara <andre.przywara@arm.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | armv8: lx2160a: fix reset sequenceMeenakshi Aggarwal2020-09-241-6/+8
| | | | | | | | | | | | | | | | | | Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | arm64: Layerscape: Survive LPI one-way reset workaroundHou Zhiqiang2020-09-241-1/+16
| | | | | | | | | | | | | | | | | | | | | | The workaround of LPI one-way reset issue is broken by the series: https://patchwork.ozlabs.org/project/uboot/list/?series=192398 This patch is to add DT node for GIC RD tables and create corresponding reserved-memory node in kernel DT to fix it. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | fsl-layerscape: enable dwc3 snooping featureRan Wang2020-09-241-0/+37
|/ | | | | | | | | | Configure DWC3’s cache type to ‘cacheable’ for better performance. Actually related register definition and values are SoC specific, which means this setting is only applicable to Layerscape SoC, not generic for all platforms which have integrated DWC3 IP. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* board: Introduce xenguest_arm64 boardAndrii Anisov2020-08-144-0/+119
| | | | | | | | | | | | | | | | Introduce a minimal Xen guest board running as a virtual machine under Xen Project's hypervisor [1], [2]. Part of the code is ported from Xen mini-os and also uses work initially done by different authors from NXP: please see relevant files for their copyrights. [1] https://xenbits.xen.org [2] https://wiki.xenproject.org/ Signed-off-by: Andrii Anisov <andrii_anisov@epam.com> Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
* ARM: add Kconfig option for PSCI 0.1Icenowy Zheng2020-08-051-0/+4
| | | | | | | | | | | | | | We still have some platforms that only implements functionalities in PSCI 0.1 (e.g. Allwinner ARMv7 SoCs). Add a Kconfig option for exporting only PSCI 0.1. The code to export PSCI 0.1 is still available and gets activated by this patch. In addition, default ARCH_SUNXI U-Boot PSCI implementation to export PSCI 0.1, to fix poweroff/reboot regression on Allwinner multi-core ARMv7 SoCs. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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