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| * | arm:pdu001: Use pseudo partition UUID for LINUX kernel boot paramter rootFelix Brack2021-01-121-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As more and more LINUX drivers are modified to use asynchronous probing instead of synchronous probing, relying on device names being equal in U-Boot and LINUX is not possible anymore. This is also true for block device names like mmc0, mmc1 ect. With LINUX kernel commit a1a4891 the probing type for the sdhci-omap driver has been set to asynchronous mode too (probe_type is now PROBE_PREFER_ASYNCHRONOUS). In the case of the PDU001 board this results in the devices mmc0 and mmc1 being swapped between U-Boot and LINUX. Device mmc0 in U-Boot becomes mmc1 in LINUX an vice versa. Hence using device name identifiers with LINUX kernel parameter root does not work anymore. This patch changes the LINUX kernel boot parameter root to use the pseudo (since we use MBR not GPT) partition UUID to locate the partition hosting the root file system. Signed-off-by: Felix Brack <fb@ltec.ch>
| * | board: ti: k2g: Add support for K2G ICE with 1GHz SiliconLokesh Vutla2021-01-126-6/+19
| | | | | | | | | | | | | | | | | | Add board detection support for K2G ICE with FlagChip 1GHz silicon. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | arm: dts: k3-j721e: ddr: Update to 0.5.0 version of DDR config toolPraneeth Bajjuri2021-01-122-219/+219
| | | | | | | | | | | | | | | | | | | | | | | | Update the ddr settings to use the DDR reg config tool rev 0.5.0. This enables 4266MTs DDR configuration. Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Kevin Scholz <k-scholz@ti.com>
| * | spi: omap3_spi: Fix speed and mode selectionVignesh Raghavendra2021-01-121-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | McSPI IP provides per CS specific speed and mode selection. Therefore it is possible to apply these settings only after CS is known. But set_speed and set_mode can be called without bus being claimed, this would lead driver to set up wrong CS (or previously used CS). Fix this by apply set_speed and set_mode only if bus is already claimed. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * | spi: ti_qspi: Fix "spi-max-frequency" error path in ti_qspi_ofdata_to_platdataOvidiu Panait2021-01-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct ti_qspi_priv->max_hz is declared as unsigned int, so the following error path check will always be false, even when "spi-max-frequency" property is invalid/missing: priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); if (priv->max_hz < 0) { ... } Replace the fdtdec call with dev_read_u32_default() and use 0 as the default value. Error out if max_hz is zero. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
| * | gpio: tca642x: fix input subcommand for gpio banks > 0Tomas Novotny2021-01-121-14/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The value of input pin for bank > 0 is always 0 for input subcommand. The reason is that gpio_bank variable is computed only for invert and output subcommands (it depends on number of arguments). The default value of zero causes to shift the mask away for banks > 0. Please note that info subcommand works as expected, because the input pin values are accessed differently. Fixes: 61c1775f16ed ("gpio: tca642x: Add the tca642x gpio expander driver") Cc: Dan Murphy <dmurphy@ti.com> Signed-off-by: Tomas Novotny <tomas@novotny.cz>
| * | configs: am65x_evm: Define the maximum file size for DFUAswath Govindraju2021-01-121-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In include/dfu.h, if CONFIG_SYS_DFU_MAX_FILE_SIZE is not defined then it is defined as CONFIG_SYS_DFU_DATA_BUF_SIZE. This is 128 KiB for a53 core and 20 KiB for r5 core. If a larger file is transferred using dfu then it fails. CONFIG_SYS_DFU_DATA_BUF_SIZE can not be increased as there is not enough heap memory to be allocated for the buffer in case of R5 spl. Fix this by defining CONFIG_SYS_DFU_MAX_FILE_SIZE as the default CONFIG_SYS_DFU_DATA_BUF_SIZE value. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
| * | arm: dts: am654-base-board-uboot: Add aliases for USB subsystemsAswath Govindraju2021-01-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sequence number assigned for USB subsystem in a uclass is dependent on the order of occurrence in the device tree. If the dr_mode of USB3SS0 controller is varied then the sequence number of USB3SS1 controller also changes. If aliases are added then sequence numbers are assigned using the alias number. This makes the sequence number of USB3SS1 controller independent of USB3SS0 controller's dr_mode. Therefore, add aliases to fix the sequence number assigned to the USB subsystems. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
| * | arm: dts: am654-base-board-uboot: Set USB0 dr_mode to hostAswath Govindraju2021-01-121-1/+1
| | | | | | | | | | | | | | | | | | | | | USB3SS0 controller is to be used as a host in U-boot. Fix it by changing the dr_mode to host. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
| * | board: ti: am65x: Set SERDES0 mux to PCIe to use USB 2.0 interfaceAswath Govindraju2021-01-121-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It has been observed that setting SERDES0 lane mux to USB prevents USB 2.0 operation on USB0. Setting SERDES0 lane mux to non-USB when USB0 is used in USB 2.0 only mode solves this issue. However, for USB3.0+2.0 operation this issue is not present. Implement this workaround by writing 1 to LANE_FUNC_SEL field in CTRLMMR_SERDES0_CTRL register. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
* | | Merge tag 'u-boot-atmel-2021.04-a' of ↵Tom Rini2021-01-1262-50/+739
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel features for 2021.04 cycle This feature set includes the new board SAMA7G5 EK, the new evaluation kit for Microchip AT91 SAMA7G5 SoC . The current board support includes two configurations for booting from eMMC (SDMMC0), SD-Card (SDMMC1), and support for two Ethernet interfaces.
| * | | ARM: dts: sama7g5ek: fix TXC pin configurationNicolas Ferre2021-01-071-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TXC line is directly connected from the SoC to the KSZ9131 PHY. There is a transient state on this signal, before configuring it to RGMII, which leads to packet transmit being blocked. Keeping a pull-up when muxing this pin as function A (G0_TXCK) fixes the issue. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
| * | | configs: sama7g5ek: add i2c and eepromEugen Hristev2021-01-072-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Add drivers for flexcom, i2c and eeproms Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | board: atmel: sama7g5ek: add support for MAC address retreivalEugen Hristev2021-01-071-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Obtain two MAC addresses from the two EEPROMs and configure the two available Ethernet interfaces accordingly. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: sama7g5ek: add i2c1 bus and eepromsEugen Hristev2021-01-071-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add node for flx1 i2c1 subnode (and alias to bus 0) This bus has two eeprom devices connected. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: at91: sama7g5: add flexcom1 and i2c subnodeEugen Hristev2021-01-071-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | Add flexcom1 and i2c subnode. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | configs: sama7g5: add mmc config for sdmmc0Eugen Hristev2021-01-073-3/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new config for storing environment from sdmmc0. Also clean-up sama7g5ek_emmc1 to point to the proper mmc device. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | board: atmel: sama7g5ek: clean-up header bootcommandEugen Hristev2021-01-071-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean-up boot command to use the predefined device and part for FAT environment. According to this device and partition, select the proper boot media. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: at91: sama7g5ek: enable sdmmc0 with pinctrlEugen Hristev2021-01-071-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable sdmmc0 on this board. A non-removable eMMC is connected on this block. Configure pincontrol accordingly. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: at91: sama7g5: add node for sdmmc0Eugen Hristev2021-01-071-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Add node for sdmmc0 block. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: at91: sama7g5: add assigned clocks for sdmmc1Eugen Hristev2021-01-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SDMMC1 requires clock specification with assigned-clocks, such that the PMC will know which parent to assign and the initial start-up frequency. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | configs: sama7g5ek: enable CCFClaudiu Beznea2021-01-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable CCF for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | configs: sama7g5ek: enable support for KSZ9131Claudiu Beznea2021-01-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Enable support for KSZ9131. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | board: atmel: sama7g5ek: increase arp timeout and retry countClaudiu Beznea2021-01-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Increase ARP timeout and retry count as this will increase the speed of communication. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add GMAC1Claudiu Beznea2021-01-072-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | Add GMAC1. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add GMAC0Claudiu Beznea2021-01-072-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | Add GMAC0. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | configs: sama7g5ek: enable mii commandClaudiu Beznea2021-01-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable mii command as ethernet's PHY specific programming is based on it. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: at91: sama7g5ek: add pinctrl for sdmmc1 and flx3Eugen Hristev2021-01-072-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl for sdmmc1 and flx3. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: at91: sama7g5: add pinctrl nodeEugen Hristev2021-01-072-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | Add pioA pinctrl node. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: sama7g5: add pit64b supportClaudiu Beznea2021-01-072-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Add DT bindings for PIT64B driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: enable autobootClaudiu Beznea2021-01-071-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Enable autoboot. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | configs: sama7g5: use PIT64BClaudiu Beznea2021-01-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use PIT64B driver. ATMEL_PIT is not available for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add CPU bindingsClaudiu Beznea2021-01-071-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Add CPU DT bindings. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | configs: sama7g5: enable CONFIG_CPUClaudiu Beznea2021-01-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable CONFIG_CPU. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: switch to PMC bindingsClaudiu Beznea2021-01-072-13/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Get rid of software defined MCK and switch to PMC bindings for IPs currently present in device tree. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add PMC bindingsClaudiu Beznea2021-01-072-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Add DT bindings for PMC driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add slow clock bindingsClaudiu Beznea2021-01-071-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Add DT bindings for slow clock driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add u-boot,dm-pre-reloc bindings for xtalsClaudiu Beznea2021-01-071-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Add dm-pre-reloc DT binding property for cristals. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: add slow rc and main rc oscillatorsClaudiu Beznea2021-01-072-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | Add slow rc and main rc oscillators to dtsi. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | ARM: dts: sama7g5: move clock frequencies for xtals in board fileClaudiu Beznea2021-01-072-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | Move clock frequencies for crystals on board specific files. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | configs: sama7g5ek: enable pll driverClaudiu Beznea2021-01-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Enable PLL driver for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | configs: sama7g5ek: set malloc pool to 68KClaudiu Beznea2021-01-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Set malloc pool to 68K for sama7g5ek. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | board: atmel: sama7g5ek: add SYS_MALLOC_F_LEN to SYS_INIT_SP_ADDRClaudiu Beznea2021-01-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Heap base address is computed based on SYS_INIT_SP_ADDR by subtracting the SYS_MALLOC_F_LEN value in board_init_f_init_reserve(). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | | board: atmel: sama7g5ek: add initial support for sama7g5ekEugen Hristev2021-01-0710-0/+285
| | | | | | | | | | | | | | | | | | | | | | | | Add initial support for sama7g5 evaluation kit board. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | ARM: dts: sama7g5: add initial DT for sama7g5 SoCEugen Hristev2021-01-071-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | Add initial basic devicetree for sama7g5 SoC Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | | arm: at91: configs: Enable CONFIG_SYS_NAND_USE_FLASH_BBT on all boardsNicolas Ferre2021-01-0750-50/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As highlighted by Stefan in the commit e074d0f79b2e ("arm: at91: gardena-smart-gateway-at91sam: Enable CONFIG_SYS_NAND_USE_FLASH_BBT") it's important to use BBT when Linux enables it. We use it for a long time on all our boards. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Stefan Roese <sr@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Tom Rini <trini@konsulko.com> Acked-by: Alexander Dahl <ada@thorsis.com>
* | | | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2021-01-1118-163/+508
|\ \ \ \ | |_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | - Pinecube board support - 64-bit FEL support - mkimage support for eGON images (superseding mksunxiboot) - Bluetooth BD address generation - some fixes
| * | | sunxi: board: add a config option to fixup a Bluetooth addressAndre Heider2021-01-112-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Bluetooth controllers, like the BCM4345C5 of the Orange Pi 3, ship with the controller default address. Add a config option to fix it up so it can function properly. Signed-off-by: Andre Heider <a.heider@gmail.com> Tested-by: Ondrej Jirman <megous@megous.com> Acked-by: Maxime Ripard <mripard@kernel.org> [rebased] Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | sunxi: board: extract creating a unique sid into a helper functionAndre Heider2021-01-111-47/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor setup_environment() so we can use the created sid for a Bluetooth address too. Signed-off-by: Andre Heider <a.heider@gmail.com> Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [rebased] Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | sunxi: dram: h6: Improve DDR3 config detectionJernej Skrabec2021-01-111-44/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that in rare cases, current analytical approach to detect correct DRAM bus width and rank on H6 doesn't work. On some TV boxes with DDR3, incorrect DRAM configuration triggers write leveling error which immediately stops initialization process. Exact reason why this error appears isn't known. However, if correct configuration is used, initalization works without problem. In order to fix this issue, simply try another configuration when any kind of error appears during initialization, not just those related to rank and bus width. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Tested-by: Thomas Graichen <thomas.graichen@googlemail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
generated by cgit (git 2.34.1) at 2025-10-01 21:41:42 +0000