diff options
| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2020-06-09 13:53:00 +0300 |
|---|---|---|
| committer | Eugen Hristev <eugen.hristev@microchip.com> | 2021-01-07 09:44:15 +0200 |
| commit | e95af87e9b4f6a251329da5ee1fa72dcf54abb86 (patch) | |
| tree | 7a5ac704459421a8920b5f9a8531f0e8839478b5 | |
| parent | 02dae80ee49ab0fd8d524b9c7a768476fcdfe1b5 (diff) | |
ARM: dts: sama7g5: add GMAC0
Add GMAC0.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| -rw-r--r-- | arch/arm/dts/sama7g5.dtsi | 11 | ||||
| -rw-r--r-- | arch/arm/dts/sama7g5ek.dts | 32 |
2 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi index 1955dd4a5b..df271a78bf 100644 --- a/arch/arm/dts/sama7g5.dtsi +++ b/arch/arm/dts/sama7g5.dtsi @@ -114,6 +114,17 @@ clock-names = "usart"; status = "disabled"; }; + + gmac0: ethernet@e2800000 { + compatible = "cdns,sama7g5-gem"; + reg = <0xe2800000 0x4000>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>; + clock-names = "hclk", "pclk", "tx_clk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 51>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 21>; /* eth pll div. */ + assigned-clock-rates = <125000000>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/dts/sama7g5ek.dts b/arch/arm/dts/sama7g5ek.dts index a9190bfcb3..194f4644b5 100644 --- a/arch/arm/dts/sama7g5ek.dts +++ b/arch/arm/dts/sama7g5ek.dts @@ -53,6 +53,19 @@ }; }; +&gmac0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gmac0_default>; + phy-mode = "rgmii-id"; + status = "okay"; + + ethernet-phy@7 { + reg = <0x7>; + }; +}; + &pinctrl { pinctrl_flx3_default: flx3_default { pinmux = <PIN_PD16__FLEXCOM3_IO0>, @@ -76,4 +89,23 @@ <PIN_PC4__SDMMC1_CD>; bias-pull-up; }; + + pinctrl_gmac0_default: gmac0_default { + pinmux = <PIN_PA16__G0_TX0>, + <PIN_PA17__G0_TX1>, + <PIN_PA26__G0_TX2>, + <PIN_PA27__G0_TX3>, + <PIN_PA19__G0_RX0>, + <PIN_PA20__G0_RX1>, + <PIN_PA28__G0_RX2>, + <PIN_PA29__G0_RX3>, + <PIN_PA15__G0_TXEN>, + <PIN_PA24__G0_TXCK>, + <PIN_PA30__G0_RXCK>, + <PIN_PA18__G0_RXDV>, + <PIN_PA22__G0_MDC>, + <PIN_PA23__G0_MDIO>, + <PIN_PA25__G0_125CK>; + bias-disable; + }; }; |