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* arm: socfpga: arria10: Add qts-filter for Arria10 socfpgaDalon Westergreen2020-10-092-4/+174
| | | | | | | | | Add a script to process HPS handoff data and generate a header for inclusion in u-boot specific devicetree addons. The header should be included in the top level of u-boot.dtsi. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: soc64: Disable CONFIG_PSCI_RESETChee Hong Ang2020-10-092-0/+2
| | | | | | | | Don't invoke 'SYSTEM_RESET' PSCI function because PSCI function calls are not supported by u-boot running in EL3. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: mailbox: Add mailbox retry supportLey Foon Tan2020-10-091-9/+31
| | | | | | | | | | | Resend mailbox command for 3 times with 2ms interval in between if it receives MBOX_RESP_TIMEOUT and MBOX_RESP_DEVICE_BUSY response code. Add a wrapper function mbox_send_cmd_common_retry() for retry, change all the callers to use this wrapper function. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* arm: socfpga: mailbox: Update mailbox response codesLey Foon Tan2020-10-091-2/+36
| | | | | | | Sync latest mailbox response codes from SDM firmware. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* arm: socfpga: mailbox: Support sending large mailbox commandChee Hong Ang2020-10-091-35/+78
| | | | | | | | Mailbox command which is too large to fit into the mailbox FIFO command buffer can be sent to SDM in multiple parts. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: mailbox: Always read mailbox responses before returning statusChee Hong Ang2020-10-091-4/+2
| | | | | | | | | Mailbox driver should always check for the length of the response and read the response data before returning the response status to caller. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: mailbox: Refactor mailbox timeout event handlingChee Hong Ang2020-10-091-4/+9
| | | | | | | | Add miliseconds delay when waiting for mailbox event to happen before timeout. This will ensure the timeout duration is predictive. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: soc64: Document down boot_scratch_cold register usageChin Liang See2020-10-091-0/+8
| | | | | | | | | | | Document down the usage of boot_scratch_cold register to avoid overlapping of usage in the code for S10 & Agilex. The boot_scratch_cold register is generally used for passing critical system info between SPL, U-Boot and Linux. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: soc64: Add timeout waiting for NOC idle ACKChee Hong Ang2020-10-091-9/+16
| | | | | | | Add timeout waiting for NOC idle ACK during FPGA bridge disable/enable. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* arm: socfpga: agilex: Enable FPGA Full Reconfiguration supportChee Hong Ang2020-10-092-1/+2
| | | | | | | | Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* fpga: intel_sdm_mb: Add watchdog resetChee Hong Ang2020-10-091-0/+3
| | | | | | | | Ensure watchdog reset is not triggered if the fpga reconfiguration is taking too long. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM MailboxChee Hong Ang2020-10-097-17/+19
| | | | | | | | | Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: Use DM watchdog timerChee Hong Ang2020-10-097-3/+13
| | | | | | | | | All SoCFPGA platforms (except Cyclone V) are now switching to CONFIG_WDT (driver model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: soc64: Show reset state in SPLChee Hong Ang2020-10-094-0/+25
| | | | | | | | | Print reset state (warm/cold) together with the source (watchdog/MPU) which has triggered the warm reset on S10 & Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: soc64: Add SDM triggered warm reset bit maskChee Hong Ang2020-10-091-2/+9
| | | | | | | | | Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat register when checking for HPS warm reset status. Refactor the warm reset mask macro for clarity purpose. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* sysreset: socfpga: agilex: Enable sysreset supportChee Hong Ang2020-10-092-2/+2
| | | | | | | Enable sysreset support for Agilex platform. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* sysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to SoC64Chee Hong Ang2020-10-094-5/+5
| | | | | | | | Rename the driver from S10 to SoC64 because Intel Agilex platform also using the this SYSRESET SoCFPGA driver for S10. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* configs: socfpga: soc64: Avoid SPL enter infinite loop during exceptionChin Liang See2020-10-092-0/+2
| | | | | | | | | | | | | | In current implementation, any exception would trigger a CPU reset. But a bad written SPL would cause infinite loop where the system will reload the same SPL instead of loading factory safe image. Hence this patch is to ensure any exception will cause a hang. At this moment, watchdog shall be triggered and Remote System Update mechanism shall load the next production image or factory safe image. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: soc64: Initialize timer in SPL onlyChee Hong Ang2020-10-091-1/+2
| | | | | | | | | Timer only need to be initialized once in SPL. This patch remove the redundancy of initializing the timer again in U-Boot proper Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: soc64: Remove PHY interface setup from misc arch initChee Hong Ang2020-10-091-83/+2
| | | | | | | | 'dwmac_socfpga' driver will setup the PHY interface during probe. PHY interface setup in arch_misc_init() is no longer needed. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* clk: agilex: Additional membus writes for HPS PLLChee Hong Ang2020-10-091-16/+78
| | | | | | | | Add additional membus writes to configure main and peripheral PLL for Agilex's clock manager. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* clk: agilex: Handle clock configuration differently in SPL and U-Boot properChee Hong Ang2020-10-091-0/+10
| | | | | | | | | | | | | Since warm reset may optionally set the CLock Manager to'boot mode', the clock driver should always force the Agilex's Clock Manager to 'boot mode' before the clock driver start configuring the Clock Manager in SPL. In SSBL, clock driver will skip the Clock Manager configuration if it's already being setup by SPL (Clock Manager NOT in 'boot mode') to prevent any inaccurate clocking issues happened on HPS peripherals such as UART, MAC and etc. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* clk: agilex: Add clock enable supportLey Foon Tan2020-10-091-0/+6
| | | | | | | | | | | Some drivers probing failed if clock enable function is not supported in clock driver. So, add clock enable function to clock driver to solve it. Return 0 (success) for *.enable function because all clocks are enabled by default in clock driver probe. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* clk: agilex: Add NAND clock supportLey Foon Tan2020-10-091-0/+3
| | | | | | | Add get nand_clk and nand_x clock support. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-cfi-flashTom Rini2020-10-083-21/+11
|\ | | | | | | | | - Fix devicetree address determination seen on QEMU ARM64 - Use DMA for reads is available
| * cfi_flash: Fix devicetree address determinationAndre Przywara2020-10-081-18/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cfi-flash driver uses an open-coded version of the generic algorithm to decode and translate multiple frames of a "reg" property. This starts off the wrong foot by using the address-cells and size-cells properties of *this* very node, and not of the parent. This somewhat happened to work back when we were using a wrong default size of 2, but broke about a year ago with commit 0ba41ce1b781 ("libfdt: return correct value if #size-cells property is not present"). Instead of fixing the reinvented wheel, just use the generic function that does all of this properly. This fixes U-Boot on QEMU (-arm64), which was crashing due to decoding a wrong flash base address: DRAM: 1 GiB Flash: "Synchronous Abort" handler, esr 0x96000044 elr: 00000000000211dc lr : 00000000000211b0 (reloc) elr: 000000007ff5e1dc lr : 000000007ff5e1b0 x0 : 00000000000000f0 x1 : 000000007ff5e1d8 x2 : 000000007edfbc48 x3 : 0000000000000000 x4 : 0000000000000000 x5 : 00000000000000f0 x6 : 000000007edfbc2c x7 : 0000000000000000 x8 : 000000007ffd8d70 x9 : 000000000000000c x10: 0400000000000003 x11: 0000000000000055 ^^^^^^^^^^^^^^^^ Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * mtd: cfi_mtd: Use DMA for readsVignesh Raghavendra2020-10-081-1/+3
| | | | | | | | | | | | | | | | | | | | | | When possible use DMA for reading from CFI flash, this provides upto 5x improvement in read performance with high speed CFI compliant flashes like HyperFlash. Code will gracefully fallback to CPU copy when DMA is unavailable. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * dma: Reduce error level when DMA channel type does not existVignesh Raghavendra2020-10-081-2/+2
| | | | | | | | | | | | | | | | Caller would need gracefully handle failures of dma_get_device(), therefore reduce pr_err() to pr_debug() when DMA device is not found. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
* | Merge tag 'mips-pull-2020-10-07' of ↵Tom Rini2020-10-0737-23/+26127
|\ \ | |/ |/| | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mips - mips: octeon: add support for DDR4 memory controller - mips: octeon: add support for DWC3 USB - mips: octeon: add support for booting Linux
| * mips: octeon: octeon_common.h: Increase CONFIG_SYS_BOOTM_LENStefan Roese2020-10-071-0/+2
| | | | | | | | | | | | Increase CONFIG_SYS_BOOTM_LEN to 64MiB for Linux kernel booting. Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add bootoctlinux commandAaron Williams2020-10-073-0/+716
| | | | | | | | | | | | | | | | | | | | | | | | Octeon needs a platform specific cmd to boot the Linux kernel, as specific parameters need to be passed and special handling for the multiple cores (SMP) is needed. Co-developed-by: Stefan Roese <sr@denx.de> Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> [use gd->ram_base instead of gd->bd->bi_memstart] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mips: octeon: Add bootmem supportAaron Williams2020-10-073-0/+1994
| | | | | | | | | | | | | | | | This is needed for Linux booting, as the memory infos need to be passed in this bootmem format to the Linux kernel. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add coremask supportAaron Williams2020-10-073-0/+1119
| | | | | | | | | | | | | | This patch adds the coremask handling functions. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add header cvmx-bootinfo.hAaron Williams2020-10-071-0/+350
| | | | | | | | | | | | | | | | Add header to handle bootinfo support, needed for Octeon Linux kernel booting. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add header cvmx-fuse.hAaron Williams2020-10-071-0/+71
| | | | | | | | | | | | | | Add header to handle Octeon fuse access. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add header octeon-feature.hAaron Williams2020-10-071-0/+442
| | | | | | | | | | | | | | | | This header includes the Octeon feature detection used in many Octeon drivers. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add header cvmx-regs.hAaron Williams2020-10-071-0/+144
| | | | | | | | | | | | | | This header includes common register defines and accessor functions. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: lowlevel_init.S: Add NMI handling code for SMP Linux bootingStefan Roese2020-10-071-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the necessary lowlevel init code, to enable SMP Linux booting. This code will be used with the platform specific Octeon Linux boot command "bootoctlinux", which starts a configurable number of cores into Linux. Additionally some erratas and lowlevel register initializations are copied from the original Cavium / Marvell U-Boot source code, enabling booting into the Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: octeon-model.h: Enable inclusion from assembler filesStefan Roese2020-10-071-0/+4
| | | | | | | | | | | | | | Add the #ifdef __ASSEMBLY__ checks to enable inclusion of this header from assembler files. Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: octeon_ebb7304_defconfig: Enable USB supportStefan Roese2020-10-071-0/+17
| | | | | | | | | | | | | | This patch enables USB support with some helpful commands, like fs support. Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add USB DT nodesStefan Roese2020-10-072-0/+84
| | | | | | | | | | | | | | Add the USB device tree nodes to the Octeon dts/dtsi files. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * mips: octeon: cache.c: Flush all pending writes in flush_dcache_range()Stefan Roese2020-10-071-6/+6
| | | | | | | | | | | | | | | | As noticed while working on the USB xHCI support, Octeon needs to flush all pending writes so that the values are present in the memory. Add this "syncw" instruction (twice) to flush_dcache_range(). Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: Add mangle-port.hStefan Roese2020-10-071-0/+56
| | | | | | | | | | | | | | | | | | Import platform specific mangle-port.h header, allowing a area specific swapping, which is needed on Octeon for USB & PCI areas. Imported from Linux v5.7. Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: cpu.c: Add table for selective swappingStefan Roese2020-10-071-0/+21
| | | | | | | | | | | | | | | | | | | | Import octeon_should_swizzle_table[] which is needed for the area specific swapping. It will be used by the platform specific mangle-port.h header. Imported from Linux v5.7. Signed-off-by: Stefan Roese <sr@denx.de>
| * usb: xhci: octeon: Add DWC3 glue layer for OcteonStefan Roese2020-10-073-0/+403
| | | | | | | | | | | | | | | | | | | | This patch adds the glue layer for the MIPS Octeon SoCs. It's ported mainly from the Linux code. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de>
| * usb: xhci: xhci_bulk_tx: Don't "BUG" when comparing addressesStefan Roese2020-10-071-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Octeon uses mapped addresses for virtual and physical memory. It's not that easy to calculate the resulting addresses here. So let's remove this BUG_ON() completely, as it's not really helpful. Please also note, that BUG_ON() is not recommended any more in the Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de>
| * usb: xhci: xhci-dwc3.c: Use dev_remap_addr() instead of dev_get_addr()Stefan Roese2020-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | On MIPS platforms, mapping of the base address is needed. This patch switches from dev_get_addr() to dev_remap_addr() to get the mapped base address of the xHCI controller. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de>
| * mips: octeon: octeon_ebb7304: Add DDR4 supportStefan Roese2020-10-074-7/+479
| | | | | | | | | | | | | | | | | | | | | | This patch adds the board specific configuration (struct) for the Octeon 3 EBB7304 EVK. This struct is ported from the 2013er Cavium / Marvell U-Boot repository. Also, the Octeon RAM driver is enabled in the board defconfig for its usage. Tested with one and two DIMMs on the EBB7304 EVK (8 & 16 GiB). Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: dram.c: Add RAM driver supportStefan Roese2020-10-071-8/+64
| | | | | | | | | | | | | | | | | | This patch adds the initialization call for the Octeon RAM driver to the Octeon platforms code. So if enabled via Kconfig, the DDR driver will be called and the RAM will be configured and used. If the RAM driver is not enabled, the L2 cache is still used as RAM. Signed-off-by: Stefan Roese <sr@denx.de>
| * ram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3)Aaron Williams2020-10-075-0/+435
| | | | | | | | | | | | | | | | | | | | | | | | This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile integration. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
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