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| author | Chee Hong Ang <chee.hong.ang@intel.com> | 2020-07-10 23:53:13 +0800 |
|---|---|---|
| committer | Ley Foon Tan <ley.foon.tan@intel.com> | 2020-10-09 17:53:11 +0800 |
| commit | 12cc44884b0e74260c2f7396b993f178f8c8df27 (patch) | |
| tree | 1c5563da0860eb414a0643a38b4c3af06c80d706 | |
| parent | 464ca99f8e8ea43e31cffc6dcf026520c8de0609 (diff) | |
| download | u-boot-12cc44884b0e74260c2f7396b993f178f8c8df27.tar.gz u-boot-12cc44884b0e74260c2f7396b993f178f8c8df27.tar.xz u-boot-12cc44884b0e74260c2f7396b993f178f8c8df27.zip | |
arm: socfpga: soc64: Initialize timer in SPL only
Timer only need to be initialized once in SPL.
This patch remove the redundancy of initializing the
timer again in U-Boot proper
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| -rw-r--r-- | arch/arm/mach-socfpga/timer_s10.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c index 3ad98bdb25..7d5598e1a3 100644 --- a/arch/arm/mach-socfpga/timer_s10.c +++ b/arch/arm/mach-socfpga/timer_s10.c @@ -14,6 +14,7 @@ */ int timer_init(void) { +#ifdef CONFIG_SPL_BUILD int enable = 0x3; /* timer enable + output signal masked */ int loadval = ~0; @@ -22,6 +23,6 @@ int timer_init(void) /* enable processor pysical counter */ asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable)); asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval)); - +#endif return 0; } |