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* bootstage: Allow SPL to obtain bootstage info from TPLSimon Glass2019-10-271-1/+13
| | | | | | | | | It is possible to enable bootstage in TPL. TPL can stash the info for SPL. But at present this information is then lost because SPL does not read from the stash. Add support for SPL not being the first phase to enable bootstage. Signed-off-by: Simon Glass <sjg@chromium.org>
* bootstage: Mark the start/end of TPL and SPL separatelySimon Glass2019-10-272-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present bootstage in TPL and SPL use the same ID so it is not possible to see the timing of each. Separate out the IDs and use the correct one depending on which phase we are at. Example output: Timer summary in microseconds (14 records): Mark Elapsed Stage 0 0 reset 224,787 224,787 TPL 282,248 57,461 end TPL 341,067 58,819 SPL 925,436 584,369 end SPL 931,710 6,274 board_init_f 1,035,482 103,772 board_init_r 1,387,852 352,370 main_loop 1,387,911 59 id=175 Accumulated time: 196 dm_r 8,300 dm_spl 14,139 dm_f 229,121 fsp-m 262,992 fsp-s Signed-off-by: Simon Glass <sjg@chromium.org>
* bootstage: Correct relocation algorithmSimon Glass2019-10-273-4/+23
| | | | | | | | | | | | | | | | At present bootstage relocation assumes that it is possible to point back to memory available before relocation, so it does not relocate the strings. However this is not the case on some platforms, such as x86 which uses the cache as RAM and loses access to this when the cache is enabled. Move the relocation step to before U-Boot relocates, expand the allocated region to include space for the strings and relocate the strings at the same time as the bootstage records. This ensures that bootstage data can remain accessible from TPL through SPL to U-Boot before/after relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
* bootstage: Avoid conflicts between stash/unstashSimon Glass2019-10-271-1/+4
| | | | | | | | | | | | | | | At present there is a single shared address for bootstage data in both TPL and SPL. If SPL unstashs TPL bootstage info and then stashes it again to pass it to U-Boot, the new stash overwrites the strings of the old stash. Fix this by duplicating the strings into the malloc() region. This should be a small code. Fix the header-file order at the same time. This problem doesn't happen at the next stage (SPL->U-Boot) since U-Boot relocates the boostage data. Signed-off-by: Simon Glass <sjg@chromium.org>
* bootstage: Fix counting of entries in stashSimon Glass2019-10-271-10/+2
| | | | | | | | | | The current code searches for empty records but these not existing with bootstage now. This used to be needed when bootstage records were stored in a spare array. Drop the unnecessary code and fix a code-style nit at the same time. Signed-off-by: Simon Glass <sjg@chromium.org>
* bootstage: Store the next ID in the stashSimon Glass2019-10-271-4/+7
| | | | | | | | When stashing bootstage info, store the next ID so that it can be used when the stash is restored. This avoids the ID starting at zero and potentially overwriting existing entries. Signed-off-by: Simon Glass <sjg@chromium.org>
* bloblist: Reserve an aligned baseSimon Glass2019-10-271-0/+1
| | | | | | | Make sure that the bloblist starts on an aligned boundary. This protects against one of the early allocating causing the alignment to be lost. Signed-off-by: Simon Glass <sjg@chromium.org>
* tiny-printf: Reorder code to support %pSimon Glass2019-10-271-13/+17
| | | | | | | | | With a bit of code reordering we can support %p using the existing code for ulong. Move the %p code up and adjust the logic accordingly. Signed-off-by: Simon Glass <sjg@chromium.org>
* tiny-printf: Add print_grouped_ull()Simon Glass2019-10-271-0/+6
| | | | | | | | | | This function is used in the bootstage report which may be trigged in TPL or TPL. Add a very basic implication of this function so that it builds. There is no attempt to get the formatting right, since this would add too much code size. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
* tiny-printf: Reduce size by removing ctypeSimon Glass2019-10-271-0/+7
| | | | | | | | The ctype array is brought into the image, adding 256 bytes, when it is unlikely to be needed. The extra code for %p is only present when DEBUG is defined, so let's drop ctype as well unless DEBUG is defined. Signed-off-by: Simon Glass <sjg@chromium.org>
* test: regmap: check the values read from the regmapJean-Jacques Hiblot2019-10-271-3/+16
| | | | | | | | | | | | The test did reads after writes but didn't check the value. It probably was because the sandbox didn't implement the writeX/readX functions. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Updated to use sandbox_set_enable_memio(): Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: regmap: Fix mask in regmap_update_bits()Simon Glass2019-10-272-2/+3
| | | | | | | | | | This function assumes that the 'val' parameter has no masked bits set. This is not defined by the function prototype though. Fix the function to mask the value and update the documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
* sandbox: test: Add a prototype for sandbox_set_enable_memio()Simon Glass2019-10-271-0/+11
| | | | | | | This function needs a prototype so that tests can use it. Add one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* sandbox: Drop 'const' from sandbox_write()Simon Glass2019-10-272-8/+6
| | | | | | | | This function writes to its address so the address should not be declared as const. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* sandbox: test: Show hex values on failureSimon Glass2019-10-271-1/+2
| | | | | | | | | | | Quite a few tests use addresses or hex values for comparisons. Add hex output for test failures, e.g.: 0x55ca22fa == reg: Expected 0x55ca22fa (1439310586), got 0x55ea22fb (1441407739) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mipsTom Rini2019-10-2575-545/+2327
|\ | | | | | | | | | | | | | | | | - bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC
| * configs: mtmips: remove configs which are selected in Kconfig or uselessWeijie Gao2019-10-254-28/+0
| | | | | | | | | | | | | | Some configs are selected in Kconfig and is no longer needed in the defconfig files. Some configs (power domain, ram) are never used. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mips: mtmips: select essential drivers in KconfigWeijie Gao2019-10-252-0/+8
| | | | | | | | | | | | | | Some drivers (clk, pinctrl, reset, ...) are necessary for reset of the system, they should be always selected. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mips: mtmips: change baudrate table for all boardsWeijie Gao2019-10-252-2/+2
| | | | | | | | | | | | | | This patch changes baudrate table for all boards preparing for using mtk highspeed uart driver. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: add default pinctrl to eth nodes for all boardsWeijie Gao2019-10-252-0/+4
| | | | | | | | | | | | | | | | | | | | | | This patch adds default eth pinctrl for all boards. There are two pinctrl nodes used for two scenarios: ephy_iot_mode - for IOT boards which have only one port (PHY0) ephy_router_mode - For routers which have more than one ports Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: add default pinctrl for gardena-smart-gateway-mt7688Weijie Gao2019-10-251-0/+3
| | | | | | | | | | | | | | This adds default pinctrl (dual SPI chip select) for gardena smart gateway Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: add mmc related nodes for mt7628an.dtsiWeijie Gao2019-10-251-0/+22
| | | | | | | | | | | | This patch adds mmc related nodes for mt7628an.dtsi Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mmc: mtk-sd: add a dts property cd-active-high for builtin-cd modeWeijie Gao2019-10-251-1/+5
| | | | | | | | | | | | | | This patch adds a dts property cd-active-high for builtin-cd mode to make it configurable instead of using hardcoded active-low. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mmc: mtk-sd: add support for MediaTek MT7620/MT7628 SoCsWeijie Gao2019-10-252-4/+21
| | | | | | | | | | | | This patch adds mmc support for MediaTek MT7620/MT7628 SoCs. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: enable eth port0 led and link poll functions for all boardsWeijie Gao2019-10-253-1/+27
| | | | | | | | | | | | | | This patch adds default p0led status and phy0 link polling for all boards. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * net: mt7628-eth: add support to isolate LAN/WAN portsWeijie Gao2019-10-251-0/+32
| | | | | | | | | | | | | | This patch add support for mt7628-eth to isolate LAN/WAN ports mainly to prevent LAN devices from getting IP address from WAN. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * net: mt7628-eth: free rx descriptor on receiving failureWeijie Gao2019-10-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When received a packet with an invalid length recorded in rx descriptor, we should free this rx descriptor to allow us to continue to receive following packets. Without doing so, u-boot will stuck in a dead loop trying to process this invalid rx descriptor. This patch adds a call to mt7628_eth_free_pkt() after received an invalid packet length. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * net: mt7628-eth: make phy link up detection optional via DTWeijie Gao2019-10-252-29/+31
| | | | | | | | | | | | | | | | | | | | | | | | The mt7628 has an embedded ethernet switch (5 phy ports + 1 cpu port). Although in IOT mode only port0 is usable, the phy0 is still connected to the switch, not the ethernet gmac directly. This patch rewrites it and makes it optional. It can be turned on by adding mediatek,poll-link-phy = <?> explicitly into the eth node. By default the driver is switch mode with all 5 phy ports working without link detection. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * net: mt7628-eth: remove hardcoded gpio settings and regmap-based phy resetWeijie Gao2019-10-251-37/+8
| | | | | | | | | | | | | | | | | | This patch removes hardcoded gpio settings as they have been replaced by pinctrl in dts, and also replaces regmap-based phy reset with a more generic reset controller. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * phy: mt76x8-usb-phy: add slew rate calibration and remove non-mt7628 partWeijie Gao2019-10-252-68/+158
| | | | | | | | | | | | | | | | This patch adds slew rate calibration for mt76x8-usb-phy, removes code which belongs to mt7620, and gets rid of using syscon and regmap by using clock driver and reset controller. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: update reset controller node for mt7628Weijie Gao2019-10-251-12/+24
| | | | | | | | | | | | This patch updates reset controller node for mt7628 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * reset: add reset controller driver for MediaTek MIPS platformWeijie Gao2019-10-254-0/+126
| | | | | | | | | | | | | | This patch adds reset controller driver for MediaTek MIPS platform and header file for mt7628. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: add default pinctrl for uart nodesWeijie Gao2019-10-251-0/+9
| | | | | | | | | | | | This patch adds default pinctrl for uart nodes Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: add pinctrl node for mt7628Weijie Gao2019-10-251-0/+150
| | | | | | | | | | | | This patch adds pinctrl node with default pin state for mt7628an.dtsi. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * pinctrl: add support for MediaTek MT7628Weijie Gao2019-10-257-0/+747
| | | | | | | | | | | | | | This patch adds pinctrl support for mt7628, with a file for common pinmux functions and a file for mt7628 which has additional support for pinconf. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * spi: mt7621-spi: restore default register value after each xferWeijie Gao2019-10-251-13/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently this driver uses a different way to implement the spi xfer, by modifying some fields of two registers, which is incompatible with the MTK's original SDK linux driver. This will cause the flash data being damaged by the SDK driver. This patch lets the mt7621_spi_set_cs() restore the original register fields after cs deactivated. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * spi: mt7621-spi: remove data cache and rewrite its xfer functionWeijie Gao2019-10-251-106/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mt7621 spi controller supports continuous generic half-duplex spi transaction. There is no need to cache xfer data at all. To achieve this goal, the OPADDR register must be used as the first data to be sent. And follows the eight generic DIDO registers. But one thing different between OPADDR and DIDO registers is OPADDR has a reversed byte order. With this patch, any amount of data can be read/written in a single xfer function call. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * spi: mt7621-spi: use clock frequency from clk driverWeijie Gao2019-10-251-7/+13
| | | | | | | | | | | | | | This patch lets the spi driver to use clock provided by the clk driver since the new clk-mt7628 driver provides accurate sys clock frequency. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: add clock node for mt7628Weijie Gao2019-10-251-4/+17
| | | | | | | | | | | | | | This patch adds clkctrl node for mt7628 and adds clocks property for some node. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * clk: add clock driver for MediaTek MT76x8 platformWeijie Gao2019-10-254-0/+199
| | | | | | | | | | | | | | | | This patch adds a clock driver for MediaTek MT7628/7688 SoC. It provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: enable high-speed UART support for mt7628Weijie Gao2019-10-251-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | All three UARTs of mt7628 are actually MediaTek's high-speed UARTs which support baudrate up to 921600. The high-speed UART is compatible with ns16550 when baudrate <= 115200. Add compatible string to dtsi file so u-boot can use it when serial_mtk driver is built in. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: move uart property clock-frequency into mt7628an.dtsiWeijie Gao2019-10-253-2/+6
| | | | | | | | | | | | | | | | The UART of MT7628 has fixed 40MHz input clock so there is no need to put clock-frequency in every dts files. Just put it into the common dtsi file. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * serial: serial_mtk: add non-DM version for SPLWeijie Gao2019-10-252-17/+187
| | | | | | | | | | | | | | | | This patch adds non-DM version for mtk hsuart driver and makes it compatible with ns16550a driver in configuration. This is needed in SPL with CONFIG_SPL_DM disabled for reducing size. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * serial: serial_mtk: enable FIFO and disable flow controlWeijie Gao2019-10-251-0/+21
| | | | | | | | | | | | | | This patch adds codes to enable FIFO and disable flow control taken from ns16550 driver. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * drivers: nand: brcmnand: fix nand_chip ecc layout structureWilliam Zhang2019-10-251-156/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current brcmnand driver is based on 4.18 linux kernel which uses mtd_set_ooblayout to set ecc layout. But nand base code in u-boot is from old kernel which does not use this new API and expect nand_chip.ecc.layout structure to be set. This cause nand_scan_tail function running into a bug check if the device has a different oob size than the default ones. This patch ports the brcmstb_choose_ecc_layout function from kernel 4.6.7 that supports the ecc layout struture and replaces the mtd_set_ooblayout method Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
| * mips: bmips: switch to board defines for dtbÁlvaro Fernández Rojas2019-10-251-2/+2
| | | | | | | | | | | | Fixes commit 344db3f, which added missing bmips dtbs depending on their SoCs. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
| * bmips: correct name charactersÁlvaro Fernández Rojas2019-10-257-7/+7
| | | | | | | | Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
| * bmips: configs: switch to size definitionsÁlvaro Fernández Rojas2019-10-2522-45/+58
| | | | | | | | | | Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mips: bmips: remove unneeded definitionsÁlvaro Fernández Rojas2019-10-251-4/+0
| | | | | | | | | | | | | | These are no longer needed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * bmips: enable vr-3032u nand supportÁlvaro Fernández Rojas2019-10-253-0/+23
| | | | | | | | Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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