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-rw-r--r--include/asm-arm/arch-s3c44b0/hardware.h281
-rw-r--r--include/configs/B2.h209
-rw-r--r--include/configs/at91rm9200dk.h1
3 files changed, 491 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c44b0/hardware.h b/include/asm-arm/arch-s3c44b0/hardware.h
new file mode 100644
index 0000000000..146e265d9a
--- /dev/null
+++ b/include/asm-arm/arch-s3c44b0/hardware.h
@@ -0,0 +1,281 @@
+/********************************************************/
+/* */
+/* Samsung S3C44B0 */
+/* tpu <tapu@371.net> */
+/* */
+/********************************************************/
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#define REGBASE 0x01c00000
+#define REGL(addr) (*(volatile unsigned int *)(REGBASE+addr))
+#define REGW(addr) (*(volatile unsigned short *)(REGBASE+addr))
+#define REGB(addr) (*(volatile unsigned char *)(REGBASE+addr))
+
+
+/*****************************/
+/* CPU Wrapper Registers */
+/*****************************/
+
+#define SYSCFG REGL(0x000000)
+#define NCACHBE0 REGL(0x000004)
+#define NCACHBE1 REGL(0x000008)
+#define SBUSCON REGL(0x040000)
+
+/************************************/
+/* Memory Controller Registers */
+/************************************/
+
+#define BWSCON REGL(0x080000)
+#define BANKCON0 REGL(0x080004)
+#define BANKCON1 REGL(0x080008)
+#define BANKCON2 REGL(0x08000c)
+#define BANKCON3 REGL(0x080010)
+#define BANKCON4 REGL(0x080014)
+#define BANKCON5 REGL(0x080018)
+#define BANKCON6 REGL(0x08001c)
+#define BANKCON7 REGL(0x080020)
+#define REFRESH REGL(0x080024)
+#define BANKSIZE REGL(0x080028)
+#define MRSRB6 REGL(0x08002c)
+#define MRSRB7 REGL(0x080030)
+
+/*********************/
+/* UART Registers */
+/*********************/
+
+#define ULCON0 REGL(0x100000)
+#define ULCON1 REGL(0x104000)
+#define UCON0 REGL(0x100004)
+#define UCON1 REGL(0x104004)
+#define UFCON0 REGL(0x100008)
+#define UFCON1 REGL(0x104008)
+#define UMCON0 REGL(0x10000c)
+#define UMCON1 REGL(0x10400c)
+#define UTRSTAT0 REGL(0x100010)
+#define UTRSTAT1 REGL(0x104010)
+#define UERSTAT0 REGL(0x100014)
+#define UERSTAT1 REGL(0x104014)
+#define UFSTAT0 REGL(0x100018)
+#define UFSTAT1 REGL(0x104018)
+#define UMSTAT0 REGL(0x10001c)
+#define UMSTAT1 REGL(0x10401c)
+#define UTXH0 REGB(0x100020)
+#define UTXH1 REGB(0x104020)
+#define URXH0 REGB(0x100024)
+#define URXH1 REGB(0x104024)
+#define UBRDIV0 REGL(0x100028)
+#define UBRDIV1 REGL(0x104028)
+
+/*******************/
+/* SIO Registers */
+/*******************/
+
+#define SIOCON REGL(0x114000)
+#define SIODAT REGL(0x114004)
+#define SBRDR REGL(0x114008)
+#define ITVCNT REGL(0x11400c)
+#define DCNTZ REGL(0x114010)
+
+/********************/
+/* IIS Registers */
+/********************/
+
+#define IISCON REGL(0x118000)
+#define IISMOD REGL(0x118004)
+#define IISPSR REGL(0x118008)
+#define IISFIFCON REGL(0x11800c)
+#define IISFIF REGW(0x118010)
+
+/**************************/
+/* I/O Ports Registers */
+/**************************/
+
+#define PCONA REGL(0x120000)
+#define PDATA REGL(0x120004)
+#define PCONB REGL(0x120008)
+#define PDATB REGL(0x12000c)
+#define PCONC REGL(0x120010)
+#define PDATC REGL(0x120014)
+#define PUPC REGL(0x120018)
+#define PCOND REGL(0x12001c)
+#define PDATD REGL(0x120020)
+#define PUPD REGL(0x120024)
+#define PCONE REGL(0x120028)
+#define PDATE REGL(0x12002c)
+#define PUPE REGL(0x120030)
+#define PCONF REGL(0x120034)
+#define PDATF REGL(0x120038)
+#define PUPF REGL(0x12003c)
+#define PCONG REGL(0x120040)
+#define PDATG REGL(0x120044)
+#define PUPG REGL(0x120048)
+#define SPUCR REGL(0x12004c)
+#define EXTINT REGL(0x120050)
+#define EXTINTPND REGL(0x120054)
+
+/*********************************/
+/* WatchDog Timers Registers */
+/*********************************/
+
+#define WTCON REGL(0x130000)
+#define WTDAT REGL(0x130004)
+#define WTCNT REGL(0x130008)
+
+/*********************************/
+/* A/D Converter Registers */
+/*********************************/
+
+#define ADCCON REGL(0x140000)
+#define ADCPSR REGL(0x140004)
+#define ADCDAT REGL(0x140008)
+
+/***************************/
+/* PWM Timer Registers */
+/***************************/
+
+#define TCFG0 REGL(0x150000)
+#define TCFG1 REGL(0x150004)
+#define TCON REGL(0x150008)
+#define TCNTB0 REGL(0x15000c)
+#define TCMPB0 REGL(0x150010)
+#define TCNTO0 REGL(0x150014)
+#define TCNTB1 REGL(0x150018)
+#define TCMPB1 REGL(0x15001c)
+#define TCNTO1 REGL(0x150020)
+#define TCNTB2 REGL(0x150024)
+#define TCMPB2 REGL(0x150028)
+#define TCNTO2 REGL(0x15002c)
+#define TCNTB3 REGL(0x150030)
+#define TCMPB3 REGL(0x150034)
+#define TCNTO3 REGL(0x150038)
+#define TCNTB4 REGL(0x15003c)
+#define TCMPB4 REGL(0x150040)
+#define TCNTO4 REGL(0x150044)
+#define TCNTB5 REGL(0x150048)
+#define TCNTO5 REGL(0x15004c)
+
+/*********************/
+/* IIC Registers */
+/*********************/
+
+#define IICCON REGL(0x160000)
+#define IICSTAT REGL(0x160004)
+#define IICADD REGL(0x160008)
+#define IICDS REGL(0x16000c)
+
+/*********************/
+/* RTC Registers */
+/*********************/
+
+#define RTCCON REGB(0x170040)
+#define RTCALM REGB(0x170050)
+#define ALMSEC REGB(0x170054)
+#define ALMMIN REGB(0x170058)
+#define ALMHOUR REGB(0x17005c)
+#define ALMDAY REGB(0x170060)
+#define ALMMON REGB(0x170064)
+#define ALMYEAR REGB(0x170068)
+#define RTCRST REGB(0x17006c)
+#define BCDSEC REGB(0x170070)
+#define BCDMIN REGB(0x170074)
+#define BCDHOUR REGB(0x170078)
+#define BCDDAY REGB(0x17007c)
+#define BCDDATE REGB(0x170080)
+#define BCDMON REGB(0x170084)
+#define BCDYEAR REGB(0x170088)
+#define TICINT REGB(0x17008c)
+
+/*********************************/
+/* Clock & Power Registers */
+/*********************************/
+
+#define PLLCON REGL(0x180000)
+#define CLKCON REGL(0x180004)
+#define CLKSLOW REGL(0x180008)
+#define LOCKTIME REGL(0x18000c)
+
+/**************************************/
+/* Interrupt Controller Registers */
+/**************************************/
+
+#define INTCON REGL(0x200000)
+#define INTPND REGL(0x200004)
+#define INTMOD REGL(0x200008)
+#define INTMSK REGL(0x20000c)
+#define I_PSLV REGL(0x200010)
+#define I_PMST REGL(0x200014)
+#define I_CSLV REGL(0x200018)
+#define I_CMST REGL(0x20001c)
+#define I_ISPR REGL(0x200020)
+#define I_ISPC REGL(0x200024)
+#define F_ISPR REGL(0x200038)
+#define F_ISPC REGL(0x20003c)
+
+/********************************/
+/* LCD Controller Registers */
+/********************************/
+
+#define LCDCON1 REGL(0x300000)
+#define LCDCON2 REGL(0x300004)
+#define LCDSADDR1 REGL(0x300008)
+#define LCDSADDR2 REGL(0x30000c)
+#define LCDSADDR3 REGL(0x300010)
+#define REDLUT REGL(0x300014)
+#define GREENLUT REGL(0x300018)
+#define BLUELUT REGL(0x30001c)
+#define DP1_2 REGL(0x300020)
+#define DP4_7 REGL(0x300024)
+#define DP3_5 REGL(0x300028)
+#define DP2_3 REGL(0x30002c)
+#define DP5_7 REGL(0x300030)
+#define DP3_4 REGL(0x300034)
+#define DP4_5 REGL(0x300038)
+#define DP6_7 REGL(0x30003c)
+#define LCDCON3 REGL(0x300040)
+#define DITHMODE REGL(0x300044)
+
+/*********************/
+/* DMA Registers */
+/*********************/
+
+#define ZDCON0 REGL(0x280000)
+#define ZDISRC0 REGL(0x280004)
+#define ZDIDES0 REGL(0x280008)
+#define ZDICNT0 REGL(0x28000c)
+#define ZDCSRC0 REGL(0x280010)
+#define ZDCDES0 REGL(0x280014)
+#define ZDCCNT0 REGL(0x280018)
+
+#define ZDCON1 REGL(0x280020)
+#define ZDISRC1 REGL(0x280024)
+#define ZDIDES1 REGL(0x280028)
+#define ZDICNT1 REGL(0x28002c)
+#define ZDCSRC1 REGL(0x280030)
+#define ZDCDES1 REGL(0x280034)
+#define ZDCCNT1 REGL(0x280038)
+
+#define BDCON0 REGL(0x380000)
+#define BDISRC0 REGL(0x380004)
+#define BDIDES0 REGL(0x380008)
+#define BDICNT0 REGL(0x38000c)
+#define BDCSRC0 REGL(0x380010)
+#define BDCDES0 REGL(0x380014)
+#define BDCCNT0 REGL(0x380018)
+
+#define BDCON1 REGL(0x380020)
+#define BDISRC1 REGL(0x380024)
+#define BDIDES1 REGL(0x380028)
+#define BDICNT1 REGL(0x38002c)
+#define BDCSRC1 REGL(0x380030)
+#define BDCDES1 REGL(0x380034)
+#define BDCCNT1 REGL(0x380038)
+
+
+#define CLEAR_PEND_INT(n) I_ISPC = (1<<(n))
+#define INT_ENABLE(n) INTMSK &= ~(1<<(n))
+#define INT_DISABLE(n) INTMSK |= (1<<(n))
+
+#define HARD_RESET_NOW()
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/configs/B2.h b/include/configs/B2.h
new file mode 100644
index 0000000000..2fc97b27c2
--- /dev/null
+++ b/include/configs/B2.h
@@ -0,0 +1,209 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ *
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * Configuation settings for the B2 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#define CONFIG_INIT_CRITICAL /* undef for developing */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
+#define CONFIG_B2 1 /* on an B2 Board */
+#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */
+#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
+
+#define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/
+
+
+#undef CONFIG_USE_IRQ /* don't need them anymore */
+
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_ENV_SIZE 1024 /* 1024 bytes may be used for env vars*/
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024 )
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE 0x04000300 /* base address */
+#define CONFIG_SMC_USE_32_BIT
+#undef CONFIG_SHOW_ACTIVITY
+#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1 1 /* we use Serial line 1 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_DATE | \
+ CFG_CMD_ELF | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_I2C )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_ETHADDR 00:50:c2:1e:af:fb
+#define CONFIG_BOOTARGS "setenv bootargs root=/dev/ram ip=192.168.0.70:::::eth0:off \
+ ether=25,0,0,0,eth0 ethaddr=00:50:c2:1e:af:fb"
+#define CONFIG_NETMASK 255.255.0.0
+#define CONFIG_IPADDR 192.168.0.70
+#define CONFIG_SERVERIP 192.168.0.23
+#define CONFIG_BOOTFILE "B2-rootfs/usr/B2-zImage.u-boot"
+#define CONFIG_BOOTCOMMAND "bootm 20000 f0000"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0C400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C800000 /* 4 ... 8 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0x0c700000 /* default load address */
+
+#define CFG_HZ 1000 /* 1 kHz */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */
+#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
+#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
+#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
+#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
+#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET 0x0 /* environment starts at the beginning of the EEPROM */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (STM24C02W6) for environment
+ */
+#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0xFE
+
+#define CFG_I2C_EEPROM_ADDR 0xA8 /* EEPROM STM24C02W6 */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
+#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
+ /* 16 byte page write mode using*/
+ /* last 4 bits of the address */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/* Flash banks JFFS2 should use */
+/*
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_FIRST_SECTOR 2
+#define CFG_JFFS2_NUM_BANKS 1
+*/
+
+/*
+ Linux TAGs (see lib_arm/armlinux.c)
+*/
+#define CONFIG_CMDLINE_TAG
+#undef CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index d97182678b..90cf8a2b4a 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -112,6 +112,7 @@
#define CONFIG_DRIVER_ETHER
#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_AT91C_USE_RMII
#define CONFIG_HAS_DATAFLASH 1
#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
generated by cgit (git 2.34.1) at 2024-11-18 21:08:01 +0000