diff options
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/video/Makefile | 3 | ||||
| -rw-r--r-- | drivers/video/bridge/Kconfig | 27 | ||||
| -rw-r--r-- | drivers/video/bridge/Makefile | 9 | ||||
| -rw-r--r-- | drivers/video/bridge/ps862x.c | 134 | ||||
| -rw-r--r-- | drivers/video/bridge/ptn3460.c | 38 | ||||
| -rw-r--r-- | drivers/video/bridge/video-bridge-uclass.c | 119 | ||||
| -rw-r--r-- | drivers/video/exynos_dp.c | 24 | ||||
| -rw-r--r-- | drivers/video/exynos_dp_lowlevel.c | 2 | ||||
| -rw-r--r-- | drivers/video/parade.c | 231 | ||||
| -rw-r--r-- | drivers/video/tegra.c | 2 |
11 files changed, 334 insertions, 257 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 9ae23e8dd0..3244cd7edd 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -240,3 +240,5 @@ config VIDEO_TEGRA124 HDMI. At present only eDP is supported by U-Boot. This option enables this support which can be used on devices which have an eDP display connected. + +source "drivers/video/bridge/Kconfig" diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 2ead7f192c..c2c4dfc57e 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_VIDEO_VESA) += vesa_fb.o obj-$(CONFIG_FORMIKE) += formike.o obj-$(CONFIG_LG4573) += lg4573.o obj-$(CONFIG_AM335X_LCD) += am335x-fb.o -obj-$(CONFIG_VIDEO_PARADE) += parade.o obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ + +obj-y += bridge/ diff --git a/drivers/video/bridge/Kconfig b/drivers/video/bridge/Kconfig new file mode 100644 index 0000000000..2a3b6c4bee --- /dev/null +++ b/drivers/video/bridge/Kconfig @@ -0,0 +1,27 @@ +config VIDEO_BRIDGE + bool "Support video bridges" + depends on DM + help + Some platforms use video bridges to convert from one output to + another. For example, where the SoC only supports eDP and the LCD + requires LVDS, an eDP->LVDS bridge chip can be used to provide the + necessary conversion. This option enables support for these devices. + +config VIDEO_BRIDGE_PARADE_PS862X + bool "Support Parade PS862X DP->LVDS bridge" + depends on VIDEO_BRIDGE + help + The Parade PS8622 and PS8625 are DisplayPort-to-LVDS (Low voltage + differential signalling) converters. They enable an LVDS LCD panel + to be connected to an eDP output device such as an SoC that lacks + LVDS capability, or where LVDS requires too many signals to route + on the PCB. Setup parameters are provided in the device tree. + +config VIDEO_BRIDGE_NXP_PTN3460 + bool "Support NXP PTN3460 DP->LVDS bridge" + depends on VIDEO_BRIDGE + help + The NXP PTN3460 is a DisplayPort-to-LVDS (Low voltage differential + signalling) converter. It enables an LVDS LCD panel to be connected + to an eDP output device such as an SoC that lacks LVDS capability, + or where LVDS requires too many signals to route on the PCB. diff --git a/drivers/video/bridge/Makefile b/drivers/video/bridge/Makefile new file mode 100644 index 0000000000..ce731fa4ca --- /dev/null +++ b/drivers/video/bridge/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2015 Google, Inc +# Written by Simon Glass <sjg@chromium.org> +# +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_VIDEO_BRIDGE) += video-bridge-uclass.o +obj-$(CONFIG_VIDEO_BRIDGE_PARADE_PS862X) += ps862x.o +obj-$(CONFIG_VIDEO_BRIDGE_NXP_PTN3460) += ptn3460.o diff --git a/drivers/video/bridge/ps862x.c b/drivers/video/bridge/ps862x.c new file mode 100644 index 0000000000..80f63e3eb5 --- /dev/null +++ b/drivers/video/bridge/ps862x.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <i2c.h> +#include <video_bridge.h> +#include <power/regulator.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Initialisation of the chip is a process of writing certain values into + * certain registers over i2c bus. The chip in fact responds to a range of + * addresses on the i2c bus, so for each written value three parameters are + * required: i2c address, register address and the actual value. + * + * The base address is derived from the device tree, but oddly the chip + * responds on several addresses with different register sets for each. + */ + +/** + * ps8622_write() Write a PS8622 eDP bridge i2c register + * + * @param dev I2C device + * @param addr_off offset from the i2c base address for ps8622 + * @param reg_addr register address to write + * @param value value to be written + * @return 0 on success, non-0 on failure + */ +static int ps8622_write(struct udevice *dev, unsigned addr_off, + unsigned char reg_addr, unsigned char value) +{ + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + uint8_t buf[2]; + struct i2c_msg msg; + int ret; + + msg.addr = chip->chip_addr + addr_off; + msg.flags = 0; + buf[0] = reg_addr; + buf[1] = value; + msg.buf = buf; + msg.len = 2; + ret = dm_i2c_xfer(dev, &msg, 1); + if (ret) { + debug("%s: write failed, reg=%#x, value=%#x, ret=%d\n", + __func__, reg_addr, value, ret); + return ret; + } + + return 0; +} + +static int ps8622_set_backlight(struct udevice *dev, int percent) +{ + int level = percent * 255 / 100; + + debug("%s: level=%d\n", __func__, level); + return ps8622_write(dev, 0x01, 0xa7, level); +} + +static int ps8622_attach(struct udevice *dev) +{ + const uint8_t *params; + struct udevice *reg; + int ret, i, len; + + debug("%s: %s\n", __func__, dev->name); + /* set the LDO providing the 1.2V rail to the Parade bridge */ + ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, + "power-supply", ®); + if (!ret) { + ret = regulator_autoset(reg); + } else if (ret != -ENOENT) { + debug("%s: Failed to enable power: ret=%d\n", __func__, ret); + return ret; + } + + ret = video_bridge_set_active(dev, true); + if (ret) + return ret; + + params = fdt_getprop(gd->fdt_blob, dev->of_offset, "parade,regs", &len); + if (!params || len % 3) { + debug("%s: missing/invalid params=%p, len=%x\n", __func__, + params, len); + return -EINVAL; + } + + /* need to wait 20ms after power on before doing I2C writes */ + mdelay(20); + for (i = 0; i < len; i += 3) { + ret = ps8622_write(dev, params[i + 0], params[i + 1], + params[i + 2]); + if (ret) + return ret; + } + + return 0; +} + +static int ps8622_probe(struct udevice *dev) +{ + debug("%s\n", __func__); + if (device_get_uclass_id(dev->parent) != UCLASS_I2C) + return -EPROTONOSUPPORT; + + return 0; +} + +struct video_bridge_ops ps8622_ops = { + .attach = ps8622_attach, + .set_backlight = ps8622_set_backlight, +}; + +static const struct udevice_id ps8622_ids[] = { + { .compatible = "parade,ps8622", }, + { .compatible = "parade,ps8625", }, + { } +}; + +U_BOOT_DRIVER(parade_ps8622) = { + .name = "parade_ps8622", + .id = UCLASS_VIDEO_BRIDGE, + .of_match = ps8622_ids, + .probe = ps8622_probe, + .ops = &ps8622_ops, +}; diff --git a/drivers/video/bridge/ptn3460.c b/drivers/video/bridge/ptn3460.c new file mode 100644 index 0000000000..2e2ae7c5a6 --- /dev/null +++ b/drivers/video/bridge/ptn3460.c @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <video_bridge.h> + +static int ptn3460_attach(struct udevice *dev) +{ + int ret; + + debug("%s: %s\n", __func__, dev->name); + ret = video_bridge_set_active(dev, true); + if (ret) + return ret; + + return 0; +} + +struct video_bridge_ops ptn3460_ops = { + .attach = ptn3460_attach, +}; + +static const struct udevice_id ptn3460_ids[] = { + { .compatible = "nxp,ptn3460", }, + { } +}; + +U_BOOT_DRIVER(parade_ptn3460) = { + .name = "nmp_ptn3460", + .id = UCLASS_VIDEO_BRIDGE, + .of_match = ptn3460_ids, + .ops = &ptn3460_ops, +}; diff --git a/drivers/video/bridge/video-bridge-uclass.c b/drivers/video/bridge/video-bridge-uclass.c new file mode 100644 index 0000000000..6c5990f54c --- /dev/null +++ b/drivers/video/bridge/video-bridge-uclass.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <video_bridge.h> + +int video_bridge_set_backlight(struct udevice *dev, int percent) +{ + struct video_bridge_ops *ops = video_bridge_get_ops(dev); + + if (!ops->set_backlight) + return -ENOSYS; + + return ops->set_backlight(dev, percent); +} + +int video_bridge_attach(struct udevice *dev) +{ + struct video_bridge_ops *ops = video_bridge_get_ops(dev); + + if (!ops->attach) + return -ENOSYS; + + return ops->attach(dev); +} + +int video_bridge_check_attached(struct udevice *dev) +{ + struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev); + struct video_bridge_ops *ops = video_bridge_get_ops(dev); + int ret; + + if (!ops->check_attached) { + ret = dm_gpio_get_value(&uc_priv->hotplug); + + return ret > 0 ? 0 : ret == 0 ? -ENOTCONN : ret; + } + + return ops->check_attached(dev); +} + +static int video_bridge_pre_probe(struct udevice *dev) +{ + struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev); + int ret; + + debug("%s\n", __func__); + ret = gpio_request_by_name(dev, "sleep-gpios", 0, + &uc_priv->sleep, GPIOD_IS_OUT); + if (ret) { + debug("%s: Could not decode sleep-gpios (%d)\n", __func__, ret); + return ret; + } + /* + * Drop this for now as we do not have driver model pinctrl support + * + * ret = dm_gpio_set_pull(&uc_priv->sleep, GPIO_PULL_NONE); + * if (ret) { + * debug("%s: Could not set sleep pull value\n", __func__); + * return ret; + * } + */ + ret = gpio_request_by_name(dev, "reset-gpios", 0, &uc_priv->reset, + GPIOD_IS_OUT); + if (ret) { + debug("%s: Could not decode reset-gpios (%d)\n", __func__, ret); + return ret; + } + /* + * Drop this for now as we do not have driver model pinctrl support + * + * ret = dm_gpio_set_pull(&uc_priv->reset, GPIO_PULL_NONE); + * if (ret) { + * debug("%s: Could not set reset pull value\n", __func__); + * return ret; + * } + */ + ret = gpio_request_by_name(dev, "hotplug-gpios", 0, &uc_priv->hotplug, + GPIOD_IS_IN); + if (ret && ret != -ENOENT) { + debug("%s: Could not decode hotplug (%d)\n", __func__, ret); + return ret; + } + + return 0; +} + +int video_bridge_set_active(struct udevice *dev, bool active) +{ + struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev); + int ret; + + debug("%s: %d\n", __func__, active); + ret = dm_gpio_set_value(&uc_priv->sleep, !active); + if (ret) + return ret; + if (active) { + ret = dm_gpio_set_value(&uc_priv->reset, true); + if (ret) + return ret; + udelay(10); + ret = dm_gpio_set_value(&uc_priv->reset, false); + } + + return ret; +} + +UCLASS_DRIVER(video_bridge) = { + .id = UCLASS_VIDEO_BRIDGE, + .name = "video_bridge", + .per_device_auto_alloc_size = sizeof(struct video_bridge_priv), + .pre_probe = video_bridge_pre_probe, +}; diff --git a/drivers/video/exynos_dp.c b/drivers/video/exynos_dp.c index f60b060ec1..5b6fc140e0 100644 --- a/drivers/video/exynos_dp.c +++ b/drivers/video/exynos_dp.c @@ -22,8 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct exynos_dp_platform_data *dp_pd; - void __exynos_set_dp_phy(unsigned int onoff) { } @@ -851,7 +849,6 @@ static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info) return ret; } -#ifdef CONFIG_OF_CONTROL int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info) { unsigned int node = fdtdec_next_compatible(blob, 0, @@ -905,7 +902,6 @@ int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info) "samsung,color-depth", 0); return 0; } -#endif unsigned int exynos_init_dp(void) { @@ -918,16 +914,8 @@ unsigned int exynos_init_dp(void) return -EFAULT; } -#ifdef CONFIG_OF_CONTROL if (exynos_dp_parse_dt(gd->fdt_blob, edp_info)) debug("unable to parse DP DT node\n"); -#else - edp_info = dp_pd->edp_dev_info; - if (edp_info == NULL) { - debug("failed to get edp_info data.\n"); - return -EFAULT; - } -#endif exynos_dp_set_base_addr(); @@ -967,17 +955,7 @@ unsigned int exynos_init_dp(void) return ret; } - printf("Exynos DP init done\n"); + debug("Exynos DP init done\n"); return ret; } - -void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd) -{ - if (pd == NULL) { - debug("pd is NULL\n"); - return; - } - - dp_pd = pd; -} diff --git a/drivers/video/exynos_dp_lowlevel.c b/drivers/video/exynos_dp_lowlevel.c index bf0ea108e8..05118f801b 100644 --- a/drivers/video/exynos_dp_lowlevel.c +++ b/drivers/video/exynos_dp_lowlevel.c @@ -823,7 +823,7 @@ int exynos_dp_read_bytes_from_i2c(unsigned int device_addr, reg = readl(&dp_regs->aux_rx_comm); if (reg == AUX_RX_COMM_AUX_DEFER || reg == AUX_RX_COMM_I2C_DEFER) { - printf("DP Defer: %d\n\n", reg); + printf("DP Defer: %d\n", reg); defer = 1; } } diff --git a/drivers/video/parade.c b/drivers/video/parade.c deleted file mode 100644 index ae5097160f..0000000000 --- a/drivers/video/parade.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file is a driver for Parade dP<->LVDS bridges. The original submission - * is for the ps8625 chip. - */ -#include <config.h> -#include <common.h> -#include <i2c.h> -#include <fdtdec.h> -#include <asm/gpio.h> - -/* - * Initialization of the chip is a process of writing certaing values into - * certain registers over i2c bus. The chip in fact responds to a range of - * addresses on the i2c bus, so for each written value three parameters are - * required: i2c address, register address and the actual value. - * - * The base address is derived from the device tree, only address offset is - * stored in the table below. - */ -/** - * struct reg_data() - data for a parade register write - * - * @addr_off offset from the i2c base address for parade - * @reg_addr register address to write - * @value value to be written - */ -struct reg_data { - uint8_t addr_off; - uint8_t reg; - uint8_t value; -} _packed; - -#define END_OF_TABLE 0xff /* Ficticious offset */ - -static const struct reg_data parade_values[] = { - {0x02, 0xa1, 0x01}, /* HPD low */ - /* - * SW setting - * [1:0] SW output 1.2V voltage is lower to 96% - */ - {0x04, 0x14, 0x01}, - /* - * RCO SS setting - * [5:4] = b01 0.5%, b10 1%, b11 1.5% - */ - {0x04, 0xe3, 0x20}, - {0x04, 0xe2, 0x80}, /* [7] RCO SS enable */ - /* - * RPHY Setting - * [3:2] CDR tune wait cycle before - * measure for fine tune b00: 1us, - * 01: 0.5us, 10:2us, 11:4us. - */ - {0x04, 0x8a, 0x0c}, - {0x04, 0x89, 0x08}, /* [3] RFD always on */ - /* - * CTN lock in/out: - * 20000ppm/80000ppm. Lock out 2 - * times. - */ - {0x04, 0x71, 0x2d}, - /* - * 2.7G CDR settings - * NOF=40LSB for HBR CDR setting - */ - {0x04, 0x7d, 0x07}, - {0x04, 0x7b, 0x00}, /* [1:0] Fmin=+4bands */ - {0x04, 0x7a, 0xfd}, /* [7:5] DCO_FTRNG=+-40% */ - /* - * 1.62G CDR settings - * [5:2]NOF=64LSB [1:0]DCO scale is 2/5 - */ - {0x04, 0xc0, 0x12}, - {0x04, 0xc1, 0x92}, /* Gitune=-37% */ - {0x04, 0xc2, 0x1c}, /* Fbstep=100% */ - {0x04, 0x32, 0x80}, /* [7] LOS signal disable */ - /* - * RPIO Setting - * [7:4] LVDS driver bias current : - * 75% (250mV swing) - */ - {0x04, 0x00, 0xb0}, - /* - * [7:6] Right-bar GPIO output strength is 8mA - */ - {0x04, 0x15, 0x40}, - /* EQ Training State Machine Setting */ - {0x04, 0x54, 0x10}, /* RCO calibration start */ - /* [4:0] MAX_LANE_COUNT set to one lane */ - {0x01, 0x02, 0x81}, - /* [4:0] LANE_COUNT_SET set to one lane */ - {0x01, 0x21, 0x81}, - {0x00, 0x52, 0x20}, - {0x00, 0xf1, 0x03}, /* HPD CP toggle enable */ - {0x00, 0x62, 0x41}, - /* Counter number, add 1ms counter delay */ - {0x00, 0xf6, 0x01}, - /* - * [6]PWM function control by - * DPCD0040f[7], default is PWM - * block always works. - */ - {0x00, 0x77, 0x06}, - /* - * 04h Adjust VTotal tolerance to - * fix the 30Hz no display issue - */ - {0x00, 0x4c, 0x04}, - /* DPCD00400='h00, Parade OUI = 'h001cf8 */ - {0x01, 0xc0, 0x00}, - {0x01, 0xc1, 0x1c}, /* DPCD00401='h1c */ - {0x01, 0xc2, 0xf8}, /* DPCD00402='hf8 */ - /* - * DPCD403~408 = ASCII code - * D2SLV5='h4432534c5635 - */ - {0x01, 0xc3, 0x44}, - {0x01, 0xc4, 0x32}, /* DPCD404 */ - {0x01, 0xc5, 0x53}, /* DPCD405 */ - {0x01, 0xc6, 0x4c}, /* DPCD406 */ - {0x01, 0xc7, 0x56}, /* DPCD407 */ - {0x01, 0xc8, 0x35}, /* DPCD408 */ - /* - * DPCD40A, Initial Code major revision - * '01' - */ - {0x01, 0xca, 0x01}, - /* DPCD40B, Initial Code minor revision '05' */ - {0x01, 0xcb, 0x05}, - /* DPCD720, Select internal PWM */ - {0x01, 0xa5, 0xa0}, - /* - * FFh for 100% PWM of brightness, 0h for 0% - * brightness - */ - {0x01, 0xa7, 0xff}, - /* - * Set LVDS output as 6bit-VESA mapping, - * single LVDS channel - */ - {0x01, 0xcc, 0x13}, - /* Enable SSC set by register */ - {0x02, 0xb1, 0x20}, - /* - * Set SSC enabled and +/-1% central - * spreading - */ - {0x04, 0x10, 0x16}, - /* MPU Clock source: LC => RCO */ - {0x04, 0x59, 0x60}, - {0x04, 0x54, 0x14}, /* LC -> RCO */ - {0x02, 0xa1, 0x91}, /* HPD high */ - {END_OF_TABLE} -}; - -/** - * Write values table into the Parade eDP bridge - * - * @return 0 on success, non-0 on failure - */ - -static int parade_write_regs(int base_addr, const struct reg_data *table) -{ - int ret = 0; - - while (!ret && (table->addr_off != END_OF_TABLE)) { - ret = i2c_write(base_addr + table->addr_off, - table->reg, 1, - (uint8_t *)&table->value, - sizeof(table->value)); - table++; - } - return ret; -} - -int parade_init(const void *blob) -{ - struct gpio_desc rst_gpio; - struct gpio_desc slp_gpio; - int bus, old_bus; - int parent; - int node; - int addr; - int ret; - - node = fdtdec_next_compatible(blob, 0, COMPAT_PARADE_PS8625); - if (node < 0) - return 0; - - parent = fdt_parent_offset(blob, node); - if (parent < 0) { - debug("%s: Could not find parent i2c node\n", __func__); - return -1; - } - addr = fdtdec_get_int(blob, node, "reg", -1); - if (addr < 0) { - debug("%s: Could not find i2c address\n", __func__); - return -1; - } - - gpio_request_by_name_nodev(blob, node, "sleep-gpio", 0, &slp_gpio, - GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); - - mdelay(10); - - gpio_request_by_name_nodev(blob, node, "reset-gpio", 0, &rst_gpio, - GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); - - bus = i2c_get_bus_num_fdt(parent); - old_bus = i2c_get_bus_num(); - - debug("%s: Using i2c bus %d\n", __func__, bus); - - /* - * TODO(sjg@chromium.org): Hmmm we seem to need some sort of delay - * here. - */ - mdelay(40); - i2c_set_bus_num(bus); - ret = parade_write_regs(addr, parade_values); - - i2c_set_bus_num(old_bus); - - return ret; -} diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index b8f3431f24..33c6103994 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -92,7 +92,7 @@ void lcd_ctrl_init(void *lcdbase) /* Enable flushing after LCD writes if requested */ lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH); - debug("LCD frame buffer at %08X\n", disp_config->frame_buffer); + debug("LCD frame buffer at %pa\n", &disp_config->frame_buffer); } ulong calc_fbsize(void) |