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-rw-r--r--drivers/pci/Makefile5
-rw-r--r--drivers/pci/pcie_layerscape_fixup.c7
-rw-r--r--drivers/pci/pcie_layerscape_fixup_common.c27
-rw-r--r--drivers/pci/pcie_layerscape_fixup_common.h20
-rw-r--r--drivers/pci/pcie_layerscape_gen4_fixup.c7
5 files changed, 58 insertions, 8 deletions
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 8a33eb0266..c051ecc9f3 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -34,9 +34,10 @@ obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
-obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
+obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o pcie_layerscape_fixup_common.o
obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
- pcie_layerscape_gen4_fixup.o pcie_layerscape.o
+ pcie_layerscape_gen4_fixup.o \
+ pcie_layerscape_fixup_common.o
obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index 27ef20d4c3..e77404cd01 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Layerscape PCIe driver
*/
@@ -17,6 +17,7 @@
#include <asm/arch/clock.h>
#endif
#include "pcie_layerscape.h"
+#include "pcie_layerscape_fixup_common.h"
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
/*
@@ -271,7 +272,7 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
}
/* Fixup Kernel DT for PCIe */
-void ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup_ls(void *blob, bd_t *bd)
{
struct ls_pcie *pcie;
@@ -284,7 +285,7 @@ void ft_pci_setup(void *blob, bd_t *bd)
}
#else /* !CONFIG_OF_BOARD_SETUP */
-void ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup_ls(void *blob, bd_t *bd)
{
}
#endif
diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c
new file mode 100644
index 0000000000..b32236e5f8
--- /dev/null
+++ b/drivers/pci/pcie_layerscape_fixup_common.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2020 NXP
+ *
+ * PCIe DT fixup for NXP Layerscape SoCs
+ * Author: Wasim Khan <wasim.khan@nxp.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/soc.h>
+#include "pcie_layerscape_fixup_common.h"
+
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+#if defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
+ uint svr;
+
+ svr = SVR_SOC_VER(get_svr());
+
+ if (svr == SVR_LX2160A && IS_SVR_REV(get_svr(), 1, 0))
+ ft_pci_setup_ls_gen4(blob, bd);
+ else
+#endif /* CONFIG_PCIE_LAYERSCAPE_GEN4 */
+ ft_pci_setup_ls(blob, bd);
+}
diff --git a/drivers/pci/pcie_layerscape_fixup_common.h b/drivers/pci/pcie_layerscape_fixup_common.h
new file mode 100644
index 0000000000..be729b6fb0
--- /dev/null
+++ b/drivers/pci/pcie_layerscape_fixup_common.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019-2020 NXP
+ *
+ * PCIe DT fixup for NXP Layerscape SoCs
+ * Author: Wasim Khan <wasim.khan@nxp.com>
+ *
+ */
+#ifndef _PCIE_LAYERSCAPE_FIXUP_COMMON_H_
+#define _PCIE_LAYERSCAPE_FIXUP_COMMON_H_
+
+#include <common.h>
+
+void ft_pci_setup_ls(void *blob, bd_t *bd);
+
+#ifdef CONFIG_PCIE_LAYERSCAPE_GEN4
+void ft_pci_setup_ls_gen4(void *blob, bd_t *bd);
+#endif /* CONFIG_PCIE_LAYERSCAPE_GEN4 */
+
+#endif //_PCIE_LAYERSCAPE_FIXUP_COMMON_H_
diff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c b/drivers/pci/pcie_layerscape_gen4_fixup.c
index da9817159f..b99ab0fa5d 100644
--- a/drivers/pci/pcie_layerscape_gen4_fixup.c
+++ b/drivers/pci/pcie_layerscape_gen4_fixup.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
*
* PCIe Gen4 driver for NXP Layerscape SoCs
* Author: Hou Zhiqiang <Minder.Hou@gmail.com>
@@ -19,6 +19,7 @@
#include <asm/arch/clock.h>
#endif
#include "pcie_layerscape_gen4.h"
+#include "pcie_layerscape_fixup_common.h"
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
/*
@@ -234,7 +235,7 @@ static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie)
}
/* Fixup Kernel DT for PCIe */
-void ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup_ls_gen4(void *blob, bd_t *bd)
{
struct ls_pcie_g4 *pcie;
@@ -247,7 +248,7 @@ void ft_pci_setup(void *blob, bd_t *bd)
}
#else /* !CONFIG_OF_BOARD_SETUP */
-void ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup_ls_gen4(void *blob, bd_t *bd)
{
}
#endif