diff options
Diffstat (limited to 'drivers/ddr/altera/sdram.c')
| -rw-r--r-- | drivers/ddr/altera/sdram.c | 146 |
1 files changed, 53 insertions, 93 deletions
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 0bfd564ede..f4f3545dad 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -301,108 +301,72 @@ static void set_sdr_ctrlcfg(void) writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); } -static void set_sdr_dram_timing1(void) +static void set_sdr_dram_timing(void) { - debug("Configuring DRAMTIMING1\n"); - clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL << - SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB); + const u32 dram_timing1 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL << + SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL << + SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL << + SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD << + SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW << + SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC << + SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB); - clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TAL_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL << - SDR_CTRLGRP_DRAMTIMING1_TAL_LSB); + const u32 dram_timing2 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI << + SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD << + SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP << + SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR << + SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR << + SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB); - clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCL_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL << - SDR_CTRLGRP_DRAMTIMING1_TCL_LSB); + const u32 dram_timing3 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP << + SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS << + SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC << + SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD << + SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD << + SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB); - clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD << - SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB); + const u32 dram_timing4 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT << + SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT << + SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB); - clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW << - SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB); + const u32 lowpwr_timing = + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES << + SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES << + SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB); - clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC << - SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB); -} + debug("Configuring DRAMTIMING1\n"); + writel(dram_timing1, &sdr_ctrl->dram_timing1); -static void set_sdr_dram_timing2(void) -{ debug("Configuring DRAMTIMING2\n"); - clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI << - SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD << - SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRP_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP << - SDR_CTRLGRP_DRAMTIMING2_TRP_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWR_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR << - SDR_CTRLGRP_DRAMTIMING2_TWR_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR << - SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB); -} + writel(dram_timing2, &sdr_ctrl->dram_timing2); -static void set_sdr_dram_timing3(void) -{ debug("Configuring DRAMTIMING3\n"); - clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP << - SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS << - SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRC_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC << - SDR_CTRLGRP_DRAMTIMING3_TRC_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD << - SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD << - SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB); -} + writel(dram_timing3, &sdr_ctrl->dram_timing3); -static void set_sdr_dram_timing4(void) -{ debug("Configuring DRAMTIMING4\n"); - clrsetbits_le32(&sdr_ctrl->dram_timing4, - SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT << - SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing4, - SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT << - SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB); -} + writel(dram_timing4, &sdr_ctrl->dram_timing4); -static void set_sdr_dram_lowpwr_timing(void) -{ debug("Configuring LOWPWRTIMING\n"); - clrsetbits_le32(&sdr_ctrl->lowpwr_timing, - SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK, - CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES << - SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB); - - clrsetbits_le32(&sdr_ctrl->lowpwr_timing, - SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK, - CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES << - SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB); + writel(lowpwr_timing, &sdr_ctrl->lowpwr_timing); } static void set_sdr_addr_rw(void) @@ -556,11 +520,7 @@ defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) &sysmgr_regs->iswgrp_handoff[4]); #endif set_sdr_ctrlcfg(); - set_sdr_dram_timing1(); - set_sdr_dram_timing2(); - set_sdr_dram_timing3(); - set_sdr_dram_timing4(); - set_sdr_dram_lowpwr_timing(); + set_sdr_dram_timing(); set_sdr_addr_rw(); debug("Configuring DRAMIFWIDTH\n"); |