diff options
Diffstat (limited to 'board/freescale')
40 files changed, 1 insertions, 4081 deletions
diff --git a/board/freescale/mpc8308rdb/Kconfig b/board/freescale/mpc8308rdb/Kconfig deleted file mode 100644 index 48d25e5a26..0000000000 --- a/board/freescale/mpc8308rdb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8308RDB - -config SYS_BOARD - default "mpc8308rdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8308RDB" - -endif diff --git a/board/freescale/mpc8308rdb/MAINTAINERS b/board/freescale/mpc8308rdb/MAINTAINERS deleted file mode 100644 index 07ff2abd13..0000000000 --- a/board/freescale/mpc8308rdb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPC8308RDB BOARD -M: Ilya Yanok <yanok@emcraft.com> -S: Maintained -F: board/freescale/mpc8308rdb/ -F: include/configs/MPC8308RDB.h -F: configs/MPC8308RDB_defconfig diff --git a/board/freescale/mpc8308rdb/Makefile b/board/freescale/mpc8308rdb/Makefile deleted file mode 100644 index d6eb4dcef2..0000000000 --- a/board/freescale/mpc8308rdb/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# (C) Copyright 2010 -# Ilya Yanok, Emcraft Systems, yanok@emcraft.com - -obj-y := mpc8308rdb.o sdram.o diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c deleted file mode 100644 index db9c5ba193..0000000000 --- a/board/freescale/mpc8308rdb/mpc8308rdb.c +++ /dev/null @@ -1,192 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com - */ - -#include <common.h> -#include <hwconfig.h> -#include <i2c.h> -#include <init.h> -#include <net.h> -#include <spi.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <pci.h> -#include <mpc83xx.h> -#include <vsc7385.h> -#include <netdev.h> -#include <fsl_esdhc.h> -#include <asm/io.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_mpc83xx_serdes.h> - -/* - * The following are used to control the SPI chip selects for the SPI command. - */ -#ifdef CONFIG_MPC8XXX_SPI - -#define SPI_CS_MASK 0x00400000 - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - /* active low */ - clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - /* inactive high */ - setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); -} -#endif /* CONFIG_MPC8XXX_SPI */ - -#ifdef CONFIG_FSL_ESDHC -int board_mmc_init(struct bd_info *bd) -{ - return fsl_esdhc_mmc_init(bd); -} -#endif - -static u8 read_board_info(void) -{ - u8 val8; - i2c_set_bus_num(0); - - if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) - return val8; - else - return 0; -} - -int checkboard(void) -{ - static const char * const rev_str[] = { - "1.0", - "<reserved>", - "<reserved>", - "<reserved>", - "<unknown>", - }; - u8 info; - int i; - - info = read_board_info(); - i = (!info) ? 4 : info & 0x03; - - printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]); - - return 0; -} - -static struct pci_region pcie_regions_0[] = { - { - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, - .size = CONFIG_SYS_PCIE1_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE1_IO_BASE, - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, - .size = CONFIG_SYS_PCIE1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -void pci_init_board(void) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - sysconf83xx_t *sysconf = &immr->sysconf; - law83xx_t *pcie_law = sysconf->pcielaw; - struct pci_region *pcie_reg[] = { pcie_regions_0 }; - - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - - /* Deassert the resets in the control register */ - out_be32(&sysconf->pecr1, 0xE0008000); - udelay(2000); - - /* Configure PCI Express Local Access Windows */ - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - mpc83xx_pcie_init(1, pcie_reg); -} -/* - * Miscellaneous late-boot configurations - * - * If a VSC7385 microcode image is present, then upload it. -*/ -int misc_init_r(void) -{ -#ifdef CONFIG_MPC8XXX_SPI - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - sysconf83xx_t *sysconf = &immr->sysconf; - - /* - * Set proper bits in SICRH to allow SPI on header J8 - * - * NOTE: this breaks the TSEC2 interface, attached to the Vitesse - * switch. The pinmux configuration does not have a fine enough - * granularity to support both simultaneously. - */ - clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO); - puts("WARNING: SPI enabled, TSEC2 support is broken\n"); - - /* Set header J8 SPI chip select output, disabled */ - setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK); - setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); -#endif - -#ifdef CONFIG_VSC7385_IMAGE - if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, - CONFIG_VSC7385_IMAGE_SIZE)) { - puts("Failure uploading VSC7385 microcode.\n"); - return 1; - } -#endif - - return 0; -} -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - fsl_fdt_fixup_dr_usb(blob, bd); - fdt_fixup_esdhc(blob, bd); - - return 0; -} -#endif - -int board_eth_init(struct bd_info *bis) -{ - int rv, num_if = 0; - - /* Initialize TSECs first */ - rv = cpu_eth_init(bis); - if (rv >= 0) - num_if += rv; - else - printf("ERROR: failed to initialize TSECs.\n"); - - rv = pci_eth_init(bis); - if (rv >= 0) - num_if += rv; - else - printf("ERROR: failed to initialize PCI Ethernet.\n"); - - return num_if; -} diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c deleted file mode 100644 index 6340fd16ea..0000000000 --- a/board/freescale/mpc8308rdb/sdram.c +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com - * - * Authors: Nick.Spence@freescale.com - * Wilson.Lo@freescale.com - * scottwood@freescale.com - * - * This files is mostly identical to the original from - * board\freescale\mpc8315erdb\sdram.c - */ - -#include <common.h> -#include <init.h> -#include <mpc83xx.h> -#include <asm/global_data.h> - -#include <asm/bitops.h> -#include <asm/io.h> - -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* Fixed sdram init -- doesn't use serial presence detect. - * - * This is useful for faster booting in configs where the RAM is unlikely - * to be changed, or for things like NAND booting where space is tight. - */ -static long fixed_sdram(void) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; - u32 msize_log2 = __ilog2(msize); - - out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_SDRAM_BASE & 0xfffff000); - out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); - out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); - - out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); - out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); - - /* Currently we use only one CS, so disable the other bank. */ - out_be32(&im->ddr.cs_config[1], 0); - - out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); - out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - - out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); - out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); - out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); - out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); - - out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); - sync(); - - /* enable DDR controller */ - setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); - sync(); - - return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); -} - -int dram_init(void) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize; - - if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) - return -ENXIO; - - /* DDR SDRAM */ - msize = fixed_sdram(); - - /* return total bus SDRAM size(bytes) -- DDR */ - gd->ram_size = msize; - - return 0; -} diff --git a/board/freescale/mpc8349itx/Kconfig b/board/freescale/mpc8349itx/Kconfig deleted file mode 100644 index ce3fffda7d..0000000000 --- a/board/freescale/mpc8349itx/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8349ITX - -config SYS_BOARD - default "mpc8349itx" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8349ITX" - -endif diff --git a/board/freescale/mpc8349itx/MAINTAINERS b/board/freescale/mpc8349itx/MAINTAINERS deleted file mode 100644 index d0388ad6e5..0000000000 --- a/board/freescale/mpc8349itx/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -MPC8349ITX BOARD -#M: - -S: Maintained -F: board/freescale/mpc8349itx/ -F: include/configs/MPC8349ITX.h -F: configs/MPC8349ITX_defconfig -F: configs/MPC8349ITX_LOWBOOT_defconfig -F: configs/MPC8349ITXGP_defconfig diff --git a/board/freescale/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile deleted file mode 100644 index 803cba09ff..0000000000 --- a/board/freescale/mpc8349itx/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) Freescale Semiconductor, Inc. 2006. - -obj-y += mpc8349itx.o -obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/mpc8349itx/README b/board/freescale/mpc8349itx/README deleted file mode 100644 index 3012b83737..0000000000 --- a/board/freescale/mpc8349itx/README +++ /dev/null @@ -1,186 +0,0 @@ -Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards ---------------------------------------------------- - -1. Board Description - - The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring - the Freescale MPC8349E processor in a Mini-ITX form factor. - - The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences: - - A) One 8MB on-board flash EEPROM chip, instead of two. - B) No SATA controller - C) No Compact Flash slot - D) No Mini-PCI slot - E) No Vitesse 7385 5-port Ethernet switch - F) No 4-port USB Type-A interface - -2. Board Switches and Jumpers - -2.0 Descriptions for all of the board jumpers can be found in the User - Guide. Of particular interest to U-Boot developers is jumper J22: - - Pos. Name Default Description - ----------------------------------------------------------------------- - A LGPL0 ON (0) HRCW source, bit 0 - B LGPL1 ON (0) HRCW source, bit 1 - C LGPL3 ON (0) HRCW source, bit 2 - D LGPL5 OFF (1) PCI_SYNC_OUT frequency - E BOOT1 ON (0) Flash EEPROM boot device - F PCI_M66EN ON (0) PCI 66MHz enable - G I2C-WP ON (0) I2C EEPROM write protection - H F_WP OFF (1) Flash EEPROM write protection - - Jumper J22.E is only for the ITX, and it decides the configuration - of the flash chips. If J22.E is ON (i.e. jumpered), then flash chip - U4 is located at address FE000000 and flash chip U7 is at FE800000. - If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000. - - For U-Boot development, J22.E can be used to switch back-and-forth - between two U-Boot images. - -3. Memory Map - -3.1. The memory map should look pretty much like this: - - 0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB) - 0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB) - 0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB) - 0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB) - 0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB) - 0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB) - 0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only) - 0xF001_0000 - 0xF001_FFFF Local bus expansion slot - 0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only) - 0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory - 0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only) - -3.2 Flash EEPROM layout. - - On the ITX, jumper J22.E is used to determine which flash chips are - at which address. When J22.E is switched, addresses from FE000000 - to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF. - - On the ITX, at the normal boot address (aka HIGHBOOT): - - FE00_0000 HRCW - FE70_0000 Alternative U-Boot image - FE80_0000 Alternative HRCW - FEF0_0000 U-Boot image - FEFF_FFFF End of flash - - On the ITX, at the low boot address (LOWBOOT) - - FE00_0000 HRCW and U-Boot image - FE04_0000 U-Boot environment variables - FE80_0000 Alternative HRCW and U-Boot image - FEFF_FFFF End of flash - - On the ITX-GP, the only option is LOWBOOT and there is only one chip - - FE00_0000 HRCW and U-Boot image - FE04_0000 U-Boot environment variables - F7FF_FFFF End of flash - -4. Definitions - -4.1 Explanation of NEW definitions in: - - include/configs/MPC8349ITX.h - - CONFIG_MPC83xx MPC83xx family - CONFIG_MPC8349 MPC8349 specific - CONFIG_MPC8349ITX MPC8349E-mITX - -5. Compilation - - Assuming you're using BASH shell: - - export CROSS_COMPILE=your-cross-compile-prefix - cd u-boot - make distclean - - make MPC8349ITX_config - or: - make MPC8349ITXGP_config - or: - make MPC8349ITX_LOWBOOT_config - - make - -6. Downloading and Flashing Images - -6.1 Download via tftp: - - tftp $loadaddr <uboot> - - where "<uboot>" is the path and filename, on the TFTP server, of - the U-Boot image. - -6.1 Reflash U-Boot Image using U-Boot - - setenv uboot <uboot> - run tftpflash - - where "<uboot>" is the path and filename, on the TFTP server, of - the U-Boot image. - -6.2 Using the HRCW to switch between two different U-Boot images on the ITX - - Because the ITX has 16MB of flash, it is possible to keep two U-Boot - images in flash, and use the HRCW to specify which one is to be used - when the board boots. This trick is especially effective with a - hardware debugger that can override the HRCW, such as the BDI-2000. - - When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image - at address FE000000. When the BMS bit is 1, the ITX will boot the - image at address FEF00000. - - Therefore, just put a U-Boot image at both FE000000 and FEF00000 and - change the BMS bit whenever you want to boot the other image. - - Step-by-step instructions: - - 1) Build an ITX image to be loaded at FEF00000 - - make distclean - make MPC8349ITX_config - make - - 2) Take the u-boot.bin image and flash it at FEF00000. - - tftp $loadaddr u-boot.bin - protect off all - erase FEF00000 +$filesize - cp.b $loadaddr FEF00000 $filesize - - 3) Build an ITX image to be loaded at FE000000 - - make distclean - make MPC8349ITX_LOWBOOT_config - make - - 4) Take the u-boot.bin image and flash it at FE000000. - - tftp $loadaddr u-boot.bin - protect off FE000000 +$filesize - erase FE000000 +$filesize - cp.b $loadaddr FE000000 $filesize - - The HRCW in flash is currently set to boot the image at FE000000. - - If you have a hardware debugger, configure it to set the HRCW to - B460A000 04040000 if you want to boot the image at FEF00000, or set - it to B060A000 04040000 if you want to boot the image at FE000000. - - To change the HRCW in flash to boot the image at FEF00000, use these - U-Boot commands: - - cp.b FE000000 1000 10000 ; copy 1st flash sector to 1000 - mw.b 1020 b4 8 ; modify BMS bit - protect off FE000000 +10000 - erase FE000000 +10000 - cp.b 1000 FE000000 10000 - -7. Notes - 1) The console baudrate for MPC8349EITX is 115200bps. diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c deleted file mode 100644 index 5b4c290df1..0000000000 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ /dev/null @@ -1,402 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - */ - -#include <common.h> -#include <fdt_support.h> -#include <init.h> -#include <ioports.h> -#include <log.h> -#include <mpc83xx.h> -#include <i2c.h> -#include <miiphy.h> -#include <vsc7385.h> -#ifdef CONFIG_PCI -#include <asm/mpc8349_pci.h> -#include <pci.h> -#endif -#include <spd_sdram.h> -#include <asm/bitops.h> -#include <asm/global_data.h> -#include <asm/mmu.h> -#if defined(CONFIG_OF_LIBFDT) -#include <linux/libfdt.h> -#endif -#include <linux/delay.h> - -#include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h" -#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SPD_EEPROM -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - /* The size of RAM, in bytes */ - u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20; - u32 ddr_size_log2 = __ilog2(ddr_size); - - im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; - -#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) -#warning Chip select bounds is only configurable in 16MB increments -#endif - im->ddr.csbnds[0].csbnds = - ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> - CSBNDS_EA_SHIFT) & CSBNDS_EA); - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - - /* Only one CS for DDR */ - im->ddr.cs_config[1] = 0; - im->ddr.cs_config[2] = 0; - im->ddr.cs_config[3] = 0; - - debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); - debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); - - debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar); - debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar); - - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ - im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1; - im->ddr.sdram_mode = - (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); - im->ddr.sdram_interval = - (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << - SDRAM_INTERVAL_BSTOPRE_SHIFT); - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - - udelay(200); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1); - debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); - debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode); - debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval); - debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg); - - return CONFIG_SYS_DDR_SIZE; -} -#endif - -#ifdef CONFIG_PCI -/* - * Initialize PCI Devices, report devices found - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc83xxmitx_config_table[] = { - { - PCI_ANY_ID, - PCI_ANY_ID, - PCI_ANY_ID, - PCI_ANY_ID, - 0x0f, - PCI_ANY_ID, - pci_cfgfunc_config_device, - { - PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} - }, - {} -} -#endif - -volatile static struct pci_controller hose[] = { - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxmitx_config_table, -#endif - }, - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxmitx_config_table, -#endif - } -}; -#endif /* CONFIG_PCI */ - -int dram_init(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; -#ifdef CONFIG_DDR_ECC - volatile ddr83xx_t *ddr = &im->ddr; -#endif - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -ENXIO; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; -#ifdef CONFIG_SPD_EEPROM - msize = spd_sdram(); -#else - msize = fixed_sdram(); -#endif - -#ifdef CONFIG_DDR_ECC - if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) - /* Unlike every other board, on the 83xx spd_sdram() returns - megabytes instead of just bytes. That's why we need to - multiple by 1MB when calling ddr_enable_ecc(). */ - ddr_enable_ecc(msize * 1048576); -#endif - - /* return total bus RAM size(bytes) */ - gd->ram_size = msize * 1024 * 1024; - - return 0; -} - -int checkboard(void) -{ -#ifdef CONFIG_TARGET_MPC8349ITX - puts("Board: Freescale MPC8349E-mITX\n"); -#else - puts("Board: Freescale MPC8349E-mITX-GP\n"); -#endif - - return 0; -} - -/* - * Implement a work-around for a hardware problem with compact - * flash. - * - * Program the UPM if compact flash is enabled. - */ -int misc_init_f(void) -{ -#ifdef CONFIG_VSC7385_ENET - volatile u32 *vsc7385_cpuctrl; - - /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up - default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That - means it is 0 when the IRQ is not active. This makes the wire-AND - logic always assert IRQ7 to CPU even if there is no request from the - switch. Since the compact flash and the switch share the same IRQ, - the Linux kernel will think that the compact flash is requesting irq - and get stuck when it tries to clear the IRQ. Thus we need to set - the L2_IRQ0 and L2_IRQ1 to active low. - - The following code sets the L1_IRQ and L2_IRQ polarity to active low. - Without this code, compact flash will not work in Linux because - unlike U-Boot, Linux uses the IRQ, so this code is necessary if we - don't enable compact flash for U-Boot. - */ - - vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0); - *vsc7385_cpuctrl |= 0x0c; -#endif - -#ifdef CONFIG_COMPACT_FLASH - /* UPM Table Configuration Code */ - static uint UPMATable[] = { - 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00, - 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00, - 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 - }; - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); - set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); - - /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000, - GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 - */ - immap->im_lbc.mamr = 0x08404440; - - upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); - - puts("UPMA: Configured for compact flash\n"); -#endif - - return 0; -} - -/* - * Miscellaneous late-boot configurations - * - * Make sure the EEPROM has the HRCW correctly programmed. - * Make sure the RTC is correctly programmed. - * - * The MPC8349E-mITX can be configured to load the HRCW from - * EEPROM instead of flash. This is controlled via jumpers - * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all - * jumpered), but if they're set to 001 or 010, then the HRCW is - * read from the "I2C EEPROM". - * - * This function makes sure that the I2C EEPROM is programmed - * correctly. - * - * If a VSC7385 microcode image is present, then upload it. - */ -int misc_init_r(void) -{ - int rc = 0; - -#if defined(CONFIG_SYS_I2C) - unsigned int orig_bus = i2c_get_bus_num(); - u8 i2c_data; - -#ifdef CONFIG_SYS_I2C_RTC_ADDR - u8 ds1339_data[17]; -#endif - -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR - static u8 eeprom_data[] = /* HRCW data */ - { - 0xAA, 0x55, 0xAA, /* Preamble */ - 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ - 0x02, 0x40, /* RCWL ADDR=0x0_0900 */ - (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF, - (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF, - (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF, - CONFIG_SYS_HRCW_LOW & 0xFF, - 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ - 0x02, 0x41, /* RCWH ADDR=0x0_0904 */ - (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF, - (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF, - (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF, - CONFIG_SYS_HRCW_HIGH & 0xFF - }; - - u8 data[sizeof(eeprom_data)]; -#endif - - printf("Board revision: "); - i2c_set_bus_num(1); - if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) - printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); - else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) - printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); - else { - printf("Unknown\n"); - rc = 1; - } - -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR - i2c_set_bus_num(0); - - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { - if (memcmp(data, eeprom_data, sizeof(data)) != 0) { - if (i2c_write - (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data, - sizeof(eeprom_data)) != 0) { - puts("Failure writing the HRCW to EEPROM via I2C.\n"); - rc = 1; - } - } - } else { - puts("Failure reading the HRCW from EEPROM via I2C.\n"); - rc = 1; - } -#endif - -#ifdef CONFIG_SYS_I2C_RTC_ADDR - i2c_set_bus_num(1); - - if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) - == 0) { - - /* Work-around for MPC8349E-mITX bug #13601. - If the RTC does not contain valid register values, the DS1339 - Linux driver will not work. - */ - - /* Make sure status register bits 6-2 are zero */ - ds1339_data[0x0f] &= ~0x7c; - - /* Check for a valid day register value */ - ds1339_data[0x03] &= ~0xf8; - if (ds1339_data[0x03] == 0) { - ds1339_data[0x03] = 1; - } - - /* Check for a valid date register value */ - ds1339_data[0x04] &= ~0xc0; - if ((ds1339_data[0x04] == 0) || - ((ds1339_data[0x04] & 0x0f) > 9) || - (ds1339_data[0x04] >= 0x32)) { - ds1339_data[0x04] = 1; - } - - /* Check for a valid month register value */ - ds1339_data[0x05] &= ~0x60; - - if ((ds1339_data[0x05] == 0) || - ((ds1339_data[0x05] & 0x0f) > 9) || - ((ds1339_data[0x05] >= 0x13) - && (ds1339_data[0x05] <= 0x19))) { - ds1339_data[0x05] = 1; - } - - /* Enable Oscillator and rate select */ - ds1339_data[0x0e] = 0x1c; - - /* Work-around for MPC8349E-mITX bug #13330. - Ensure that the RTC control register contains the value 0x1c. - This affects SATA performance. - */ - - if (i2c_write - (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, - sizeof(ds1339_data))) { - puts("Failure writing to the RTC via I2C.\n"); - rc = 1; - } - } else { - puts("Failure reading from the RTC via I2C.\n"); - rc = 1; - } -#endif - - i2c_set_bus_num(orig_bus); -#endif - -#ifdef CONFIG_VSC7385_IMAGE - if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, - CONFIG_VSC7385_IMAGE_SIZE)) { - puts("Failure uploading VSC7385 microcode.\n"); - rc = 1; - } -#endif - - return rc; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - - return 0; -} -#endif diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c deleted file mode 100644 index a09b658688..0000000000 --- a/board/freescale/mpc8349itx/pci.c +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <linux/delay.h> - -#include <asm/mmu.h> -#include <asm/io.h> -#include <mpc83xx.h> -#include <pci.h> -#include <i2c.h> -#include <asm/fsl_i2c.h> - -static struct pci_region pci1_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; - -#ifdef CONFIG_MPC83XX_PCI2 -static struct pci_region pci2_regions[] = { - { - bus_start: CONFIG_SYS_PCI2_MEM_BASE, - phys_start: CONFIG_SYS_PCI2_MEM_PHYS, - size: CONFIG_SYS_PCI2_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI2_IO_BASE, - phys_start: CONFIG_SYS_PCI2_IO_PHYS, - size: CONFIG_SYS_PCI2_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI2_MMIO_BASE, - phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, - size: CONFIG_SYS_PCI2_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; -#endif - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; -#ifndef CONFIG_MPC83XX_PCI2 - struct pci_region *reg[] = { pci1_regions }; -#else - struct pci_region *reg[] = { pci1_regions, pci2_regions }; -#endif - u8 reg8; - -#if defined(CONFIG_SYS_I2C) - i2c_set_bus_num(1); - /* Read the PCI_M66EN jumper setting */ - if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) || - (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) { - if (reg8 & I2C_8574_PCI66) - clk->occr = 0xff000000; /* 66 MHz PCI */ - else - clk->occr = 0xff600001; /* 33 MHz PCI */ - } else { - clk->occr = 0xff600001; /* 33 MHz PCI */ - } -#else - clk->occr = 0xff000000; /* 66 MHz PCI */ -#endif - udelay(2000); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; - - udelay(2000); - -#ifndef CONFIG_MPC83XX_PCI2 - mpc83xx_pci_init(1, reg); -#else - mpc83xx_pci_init(2, reg); -#endif -} diff --git a/board/freescale/mpc837xemds/Kconfig b/board/freescale/mpc837xemds/Kconfig deleted file mode 100644 index 20d29db099..0000000000 --- a/board/freescale/mpc837xemds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC837XEMDS - -config SYS_BOARD - default "mpc837xemds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC837XEMDS" - -endif diff --git a/board/freescale/mpc837xemds/MAINTAINERS b/board/freescale/mpc837xemds/MAINTAINERS deleted file mode 100644 index ce9c446f2d..0000000000 --- a/board/freescale/mpc837xemds/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -MPC837XEMDS BOARD -#M: Dave Liu <daveliu@freescale.com> -S: Orphan (since 2018-05) -F: board/freescale/mpc837xemds/ -F: include/configs/MPC837XEMDS.h -F: configs/MPC837XEMDS_defconfig -F: configs/MPC837XEMDS_SLAVE_defconfig -F: configs/MPC837XEMDS_HOST_defconfig diff --git a/board/freescale/mpc837xemds/Makefile b/board/freescale/mpc837xemds/Makefile deleted file mode 100644 index 5348cdf00c..0000000000 --- a/board/freescale/mpc837xemds/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc837xemds.o -obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/mpc837xemds/README b/board/freescale/mpc837xemds/README deleted file mode 100644 index dbb15171e6..0000000000 --- a/board/freescale/mpc837xemds/README +++ /dev/null @@ -1,104 +0,0 @@ -Freescale MPC837xEMDS Board ------------------------------------------ -1. Board Switches and Jumpers -1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board - For some reason, the HW designers describe the switch settings - in terms of 0 and 1, and then map that to physical switches where - the label "On" refers to logic 0 and "Off" is logic 1. - - Switch bits are numbered 1 through, like, 4 6 8 or 10, but the - bits may contribute to signals that are numbered based at 0, - and some of those signals may be high-bit-number-0 too. Heed - well the names and labels and do not get confused. - - "Off" == 1 - "On" == 0 - - SW4[8] is the bit labeled 8 on Switch 4. - SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. - SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On" - and bits labeled 8 is set as "Off". - -1.1 For the MPC837xEMDS Processor Board - - First, make sure the board default setting is consistent with the - document shipped with your board. Then apply the following setting: - SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting) - SW4[1-8]= 0000_0110 (core PLL setting) - SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash) - SW6[1-8]= 0000_1000 (HRCW is read from NOR FLASH) - SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII) - J3 2-3, TSEC1 LVDD1 with 2.5V - J6 2-3, TSEC2 LVDD2 with 2.5V - J9 2-3, CLKIN from osc on board - J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND - J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND) - mounted, HRCW load from BCSR. - - on board Oscillator: 66M - -2. Memory Map - -2.1. The memory map should look pretty much like this: - - 0x0000_0000 0x7fff_ffff DDR 2G - 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M - 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M - 0xc000_0000 0xdfff_ffff Empty 512M - 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M - 0xe010_0000 0xe02f_ffff Empty 2M - 0xe030_0000 0xe03f_ffff PCI IO 1M - 0xe040_0000 0xe05f_ffff Empty 2M - 0xe060_0000 0xe060_7fff NAND Flash 32K - 0xf400_0000 0xf7ff_ffff Empty 64M - 0xf800_0000 0xf800_7fff BCSR on CS1 32K - 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M - -3. Definitions - -3.1 Explanation of NEW definitions in: - - include/configs/MPC837XEMDS.h - - CONFIG_MPC83xx MPC83xx family for both MPC837x and MPC8360 - CONFIG_MPC837x MPC837x specific - CONFIG_MPC837XEMDS MPC837XEMDS board specific - -4. Compilation - - Assuming you're using BASH shell: - - export CROSS_COMPILE=your-cross-compile-prefix - cd u-boot - make distclean - make MPC837XEMDS_config - make - -5. Downloading and Flashing Images - -5.0 Download over serial line using Kermit: - - loadb - [Drop to kermit: - ^\c - send <u-boot-bin-image> - c - ] - - - Or via tftp: - - tftp 40000 u-boot.bin - -5.1 Reflash U-Boot Image using U-Boot - - tftp 40000 u-boot.bin - protect off fe000000 fe1fffff - erase fe000000 fe1fffff - - cp.b 40000 fe000000 xxxx - -You have to supply the correct byte count with 'xxxx' from the TFTP result log. - -6. Notes - 1) The console baudrate for MPC837XEMDS is 115200bps. diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c deleted file mode 100644 index 71875cf8f8..0000000000 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ /dev/null @@ -1,354 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007,2010 Freescale Semiconductor, Inc. - * Dave Liu <daveliu@freescale.com> - */ - -#include <common.h> -#include <hwconfig.h> -#include <i2c.h> -#include <init.h> -#include <net.h> -#include <asm/bitops.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/fsl_mpc83xx_serdes.h> -#include <spd_sdram.h> -#include <tsec.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <fsl_esdhc.h> -#include <fsl_mdio.h> -#include <phy.h> -#include "pci.h" -#include "../common/pq-mds-pib.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; - - /* Enable flash write */ - bcsr[0x9] &= ~0x04; - /* Clear all of the interrupt of BCSR */ - bcsr[0xe] = 0xff; - -#ifdef CONFIG_FSL_SERDES - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - u32 spridr = in_be32(&immr->sysconf.spridr); - - /* we check only part num, and don't look for CPU revisions */ - switch (PARTID_NO_E(spridr)) { - case SPR_8377: - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - break; - case SPR_8378: - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII, - FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V); - break; - case SPR_8379: - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - break; - default: - printf("serdes not configured: unknown CPU part number: " - "%04x\n", spridr >> 16); - break; - } -#endif /* CONFIG_FSL_SERDES */ - return 0; -} - -#ifdef CONFIG_FSL_ESDHC -int board_mmc_init(struct bd_info *bd) -{ - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; - - if (!hwconfig("esdhc")) - return 0; - - /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */ - bcsr[0xc] |= 0x4c; - - /* Set proper bits in SICR to allow SD signals through */ - clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); - clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI, - SICRH_GPIO2_E_SD | SICRH_SPI_SD); - - return fsl_esdhc_mmc_init(bd); -} -#endif - -#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) -int board_eth_init(struct bd_info *bd) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[2]; - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; - u32 rcwh = in_be32(&im->reset.rcwh); - u32 tsec_mode; - int num = 0; - - /* New line after Net: */ - printf("\n"); - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - - printf(CONFIG_TSEC1_NAME ": "); - - tsec_mode = rcwh & HRCWH_TSEC1M_MASK; - if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) { - printf("RGMII\n"); - /* this is default, no need to fixup */ - } else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) { - printf("SGMII\n"); - tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII; - tsec_info[num].flags = TSEC_GIGABIT; - } else { - printf("unsupported PHY type\n"); - } - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - - printf(CONFIG_TSEC2_NAME ": "); - - tsec_mode = rcwh & HRCWH_TSEC2M_MASK; - if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) { - printf("RGMII\n"); - /* this is default, no need to fixup */ - } else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) { - printf("SGMII\n"); - tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII; - tsec_info[num].flags = TSEC_GIGABIT; - } else { - printf("unsupported PHY type\n"); - } - num++; -#endif - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bd, &mdio_info); - - return tsec_eth_init(bd, tsec_info, num); -} - -static void __ft_tsec_fixup(void *blob, struct bd_info *bd, const char *alias, - int phy_addr) -{ - const u32 *ph; - int off; - int err; - - off = fdt_path_offset(blob, alias); - if (off < 0) { - printf("WARNING: could not find %s alias: %s.\n", alias, - fdt_strerror(off)); - return; - } - - err = fdt_fixup_phy_connection(blob, off, PHY_INTERFACE_MODE_SGMII); - - if (err) { - printf("WARNING: could not set phy-connection-type for %s: " - "%s.\n", alias, fdt_strerror(err)); - return; - } - - ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0); - if (!ph) { - printf("WARNING: could not get phy-handle for %s.\n", - alias); - return; - } - - off = fdt_node_offset_by_phandle(blob, *ph); - if (off < 0) { - printf("WARNING: could not get phy node for %s: %s\n", alias, - fdt_strerror(off)); - return; - } - - phy_addr = cpu_to_fdt32(phy_addr); - err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr)); - if (err < 0) { - printf("WARNING: could not set phy node's reg for %s: " - "%s.\n", alias, fdt_strerror(err)); - return; - } -} - -static void ft_tsec_fixup(void *blob, struct bd_info *bd) -{ - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; - u32 rcwh = in_be32(&im->reset.rcwh); - u32 tsec_mode; - -#ifdef CONFIG_TSEC1 - tsec_mode = rcwh & HRCWH_TSEC1M_MASK; - if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) - __ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII); -#endif - -#ifdef CONFIG_TSEC2 - tsec_mode = rcwh & HRCWH_TSEC2M_MASK; - if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) - __ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII); -#endif -} -#else -static inline void ft_tsec_fixup(void *blob, struct bd_info *bd) {} -#endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */ - -int board_early_init_r(void) -{ -#ifdef CONFIG_PQ_MDS_PIB - pib_init(); -#endif - return 0; -} - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif -int fixed_sdram(void); - -int dram_init(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -ENXIO; - -#if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(); -#else - msize = fixed_sdram(); -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* Initialize DDR ECC byte */ - ddr_enable_ecc(msize * 1024 * 1024); -#endif - - /* return total bus DDR size(bytes) */ - gd->ram_size = msize * 1024 * 1024; - - return 0; -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; - u32 msize_log2 = __ilog2(msize); - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - -#if (CONFIG_SYS_DDR_SIZE != 512) -#warning Currenly any ddr size other than 512 is not supported -#endif - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; - udelay(50000); - - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - udelay(1000); - - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - udelay(1000); - - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - __asm__ __volatile__("sync"); - udelay(1000); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - udelay(2000); - return CONFIG_SYS_DDR_SIZE; -} -#endif /*!CONFIG_SYS_SPD_EEPROM */ - -int checkboard(void) -{ - puts("Board: Freescale MPC837xEMDS\n"); - return 0; -} - -#ifdef CONFIG_PCI -int board_pci_host_broken(void) -{ - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; - const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST; - - /* It's always OK in case of external arbiter. */ - if (hwconfig_subarg_cmp("pci", "arbiter", "external")) - return 0; - - if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask) - return 1; - - return 0; -} - -static void ft_pci_fixup(void *blob, struct bd_info *bd) -{ - const char *status = "broken (no arbiter)"; - int off; - int err; - - off = fdt_path_offset(blob, "pci0"); - if (off < 0) { - printf("WARNING: could not find pci0 alias: %s.\n", - fdt_strerror(off)); - return; - } - - err = fdt_setprop(blob, off, "status", status, strlen(status) + 1); - if (err) { - printf("WARNING: could not set status for pci0: %s.\n", - fdt_strerror(err)); - return; - } -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - ft_tsec_fixup(blob, bd); - fsl_fdt_fixup_dr_usb(blob, bd); - fdt_fixup_esdhc(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); - if (board_pci_host_broken()) - ft_pci_fixup(blob, bd); - ft_pcie_fixup(blob, bd); -#endif - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c deleted file mode 100644 index 188e60ac08..0000000000 --- a/board/freescale/mpc837xemds/pci.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - */ - -#include <init.h> -#include <asm/mmu.h> -#include <asm/io.h> -#include <common.h> -#include <env.h> -#include <mpc83xx.h> -#include <pci.h> -#include <i2c.h> -#include <fdt_support.h> -#include <asm/fsl_i2c.h> -#include <asm/fsl_mpc83xx_serdes.h> -#include <linux/delay.h> - -static struct pci_region pci_regions[] = { - { - bus_start: CONFIG_SYS_PCI_MEM_BASE, - phys_start: CONFIG_SYS_PCI_MEM_PHYS, - size: CONFIG_SYS_PCI_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI_MMIO_BASE, - phys_start: CONFIG_SYS_PCI_MMIO_PHYS, - size: CONFIG_SYS_PCI_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CONFIG_SYS_PCI_IO_BASE, - phys_start: CONFIG_SYS_PCI_IO_PHYS, - size: CONFIG_SYS_PCI_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -static struct pci_region pcie_regions_0[] = { - { - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, - .size = CONFIG_SYS_PCIE1_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE1_IO_BASE, - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, - .size = CONFIG_SYS_PCIE1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -static struct pci_region pcie_regions_1[] = { - { - .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, - .size = CONFIG_SYS_PCIE2_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE2_IO_BASE, - .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, - .size = CONFIG_SYS_PCIE2_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -static int is_pex_x2(void) -{ - const char *pex_x2 = env_get("pex_x2"); - - if (pex_x2 && !strcmp(pex_x2, "yes")) - return 1; - return 0; -} - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile sysconf83xx_t *sysconf = &immr->sysconf; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - volatile law83xx_t *pcie_law = sysconf->pcielaw; - struct pci_region *reg[] = { pci_regions }; - struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; - u32 spridr = in_be32(&immr->sysconf.spridr); - int pex2 = is_pex_x2(); - - if (board_pci_host_broken()) - goto skip_pci; - - /* Enable all 5 PCI_CLK_OUTPUTS */ - clk->occr |= 0xf8000000; - udelay(2000); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - udelay(2000); - - mpc83xx_pci_init(1, reg); -skip_pci: - /* There is no PEX in MPC8379 parts. */ - if (PARTID_NO_E(spridr) == SPR_8379) - return; - - if (pex2) - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - else - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - - /* Configure the clock for PCIE controller */ - clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, - SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); - - /* Deassert the resets in the control register */ - out_be32(&sysconf->pecr1, 0xE0008000); - if (!pex2) - out_be32(&sysconf->pecr2, 0xE0008000); - udelay(2000); - - /* Configure PCI Express Local Access Windows */ - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); - out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); - - mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg); -} - -void ft_pcie_fixup(void *blob, struct bd_info *bd) -{ - const char *status = "disabled (PCIE1 is x2)"; - - if (!is_pex_x2()) - return; - - do_fixup_by_path(blob, "pci2", "status", status, - strlen(status) + 1, 1); -} diff --git a/board/freescale/mpc837xemds/pci.h b/board/freescale/mpc837xemds/pci.h deleted file mode 100644 index a568031988..0000000000 --- a/board/freescale/mpc837xemds/pci.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __BOARD_MPC837XEMDS_PCI_H -#define __BOARD_MPC837XEMDS_PCI_H - -extern void ft_pcie_fixup(void *blob, struct bd_info *bd); - -#endif /* __BOARD_MPC837XEMDS_PCI_H */ diff --git a/board/freescale/mx53evk/Kconfig b/board/freescale/mx53evk/Kconfig deleted file mode 100644 index c226c1ca06..0000000000 --- a/board/freescale/mx53evk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX53EVK - -config SYS_BOARD - default "mx53evk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mx5" - -config SYS_CONFIG_NAME - default "mx53evk" - -endif diff --git a/board/freescale/mx53evk/MAINTAINERS b/board/freescale/mx53evk/MAINTAINERS deleted file mode 100644 index d511046cb0..0000000000 --- a/board/freescale/mx53evk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX53EVK BOARD -M: Jason Liu <jason.hui.liu@nxp.com> -S: Maintained -F: board/freescale/mx53evk/ -F: include/configs/mx53evk.h -F: configs/mx53evk_defconfig diff --git a/board/freescale/mx53evk/Makefile b/board/freescale/mx53evk/Makefile deleted file mode 100644 index cfe4be321e..0000000000 --- a/board/freescale/mx53evk/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> -# -# (C) Copyright 2010 Freescale Semiconductor, Inc. - -obj-y := mx53evk.o diff --git a/board/freescale/mx53evk/imximage.cfg b/board/freescale/mx53evk/imximage.cfg deleted file mode 100644 index ef103d6da7..0000000000 --- a/board/freescale/mx53evk/imximage.cfg +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C Copyright 2009 - * Stefano Babic DENX Software Engineering sbabic@denx.de. - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -/* Setting IOMUXC */ -DATA 4 0x53fa8554 0x00200000 -DATA 4 0x53fa8560 0x00200000 -DATA 4 0x53fa8594 0x00200000 -DATA 4 0x53fa8584 0x00200000 -DATA 4 0x53fa8558 0x00200040 -DATA 4 0x53fa8568 0x00200040 -DATA 4 0x53fa8590 0x00200040 -DATA 4 0x53fa857c 0x00200040 -DATA 4 0x53fa8564 0x00200040 -DATA 4 0x53fa8580 0x00200040 -DATA 4 0x53fa8570 0x00200000 -DATA 4 0x53fa8578 0x00200000 -DATA 4 0x53fa872c 0x00200000 -DATA 4 0x53fa8728 0x00200000 -DATA 4 0x53fa871c 0x00200000 -DATA 4 0x53fa8718 0x00200000 -DATA 4 0x53fa8574 0x00280000 -DATA 4 0x53fa8588 0x00280000 -DATA 4 0x53fa86f0 0x00280000 -DATA 4 0x53fa8720 0x00280000 -DATA 4 0x53fa86fc 0x00000000 -DATA 4 0x53fa86f4 0x00000200 -DATA 4 0x53fa8714 0x00000000 -DATA 4 0x53fa8724 0x06000000 -DATA 4 0x63fd9088 0x34333936 -DATA 4 0x63fd9090 0x49434942 -DATA 4 0x63fd90F8 0x00000800 -DATA 4 0x63fd907c 0x01350138 -DATA 4 0x63fd9080 0x01380139 -DATA 4 0x63fd9018 0x00001710 -DATA 4 0x63fd9000 0xc4110000 -DATA 4 0x63fd900C 0x4d5122d2 -DATA 4 0x63fd9010 0x92d18a22 -DATA 4 0x63fd9014 0x00c70092 -DATA 4 0x63fd902c 0x000026d2 -DATA 4 0x63fd9030 0x009f000e -DATA 4 0x63fd9008 0x12272000 -DATA 4 0x63fd9004 0x00030012 -DATA 4 0x63fd901c 0x04008010 -DATA 4 0x63fd901c 0x00008032 -DATA 4 0x63fd901c 0x00008033 -DATA 4 0x63fd901c 0x00008031 -DATA 4 0x63fd901c 0x0b5280b0 -DATA 4 0x63fd901c 0x04008010 -DATA 4 0x63fd901c 0x00008020 -DATA 4 0x63fd901c 0x00008020 -DATA 4 0x63fd901c 0x0a528030 -DATA 4 0x63fd901c 0x03c68031 -DATA 4 0x63fd901c 0x00448031 -DATA 4 0x63fd901c 0x04008018 -DATA 4 0x63fd901c 0x0000803a -DATA 4 0x63fd901c 0x0000803b -DATA 4 0x63fd901c 0x00008039 -DATA 4 0x63fd901c 0x0b528138 -DATA 4 0x63fd901c 0x04008018 -DATA 4 0x63fd901c 0x00008028 -DATA 4 0x63fd901c 0x00008028 -DATA 4 0x63fd901c 0x0a528038 -DATA 4 0x63fd901c 0x03c68039 -DATA 4 0x63fd901c 0x00448039 -DATA 4 0x63fd9020 0x00005800 -DATA 4 0x63fd9058 0x00033335 -DATA 4 0x63fd901c 0x00000000 -DATA 4 0x63fd9040 0x05380003 -DATA 4 0x53fa8004 0x00194005 diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c deleted file mode 100644 index b006638e2c..0000000000 --- a/board/freescale/mx53evk/mx53evk.c +++ /dev/null @@ -1,270 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux-mx53.h> -#include <linux/errno.h> -#include <asm/mach-imx/boot_mode.h> -#include <netdev.h> -#include <i2c.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <power/pmic.h> -#include <fsl_pmic.h> -#include <asm/gpio.h> -#include <mc13892.h> - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - return 0; -} - -#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) - -static void setup_iomux_uart(void) -{ - static const iomux_v3_cfg_t uart_pads[] = { - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); -} - -#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ - PAD_CTL_HYS | PAD_CTL_ODE) - -static void setup_i2c(unsigned int port_number) -{ - static const iomux_v3_cfg_t i2c1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL), - }; - - static const iomux_v3_cfg_t i2c2_pads[] = { - NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL), - }; - - switch (port_number) { - case 0: - imx_iomux_v3_setup_multiple_pads(i2c1_pads, - ARRAY_SIZE(i2c1_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads(i2c2_pads, - ARRAY_SIZE(i2c2_pads)); - break; - default: - printf("Warning: Wrong I2C port number\n"); - break; - } -} - -void power_init(void) -{ - unsigned int val; - struct pmic *p; - int ret; - - ret = pmic_init(I2C_0); - if (ret) - return; - - p = pmic_get("FSL_PMIC"); - if (!p) - return; - - /* Set VDDA to 1.25V */ - pmic_reg_read(p, REG_SW_2, &val); - val &= ~SWX_OUT_MASK; - val |= SWX_OUT_1_25; - pmic_reg_write(p, REG_SW_2, val); - - /* - * Need increase VCC and VDDA to 1.3V - * according to MX53 IC TO2 datasheet. - */ - if (is_soc_rev(CHIP_REV_2_0) == 0) { - /* Set VCC to 1.3V for TO2 */ - pmic_reg_read(p, REG_SW_1, &val); - val &= ~SWX_OUT_MASK; - val |= SWX_OUT_1_30; - pmic_reg_write(p, REG_SW_1, val); - - /* Set VDDA to 1.3V for TO2 */ - pmic_reg_read(p, REG_SW_2, &val); - val &= ~SWX_OUT_MASK; - val |= SWX_OUT_1_30; - pmic_reg_write(p, REG_SW_2, val); - } -} - -static void setup_iomux_fec(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), - NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, - PAD_CTL_HYS | PAD_CTL_PKE), - }; - - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR}, - {MMC_SDHC3_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; - - imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11); - gpio_direction_input(IMX_GPIO_NR(3, 11)); - imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13); - gpio_direction_input(IMX_GPIO_NR(3, 13)); - - if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - ret = !gpio_get_value(IMX_GPIO_NR(3, 13)); - else - ret = !gpio_get_value(IMX_GPIO_NR(3, 11)); - - return ret; -} - -#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH) - -int board_mmc_init(struct bd_info *bis) -{ - static const iomux_v3_cfg_t sd1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), - MX53_PAD_EIM_DA13__GPIO3_13, - }; - - static const iomux_v3_cfg_t sd2_pads[] = { - NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, - SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), - MX53_PAD_EIM_DA11__GPIO3_11, - }; - - u32 index; - int ret; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - - for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads(sd1_pads, - ARRAY_SIZE(sd1_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads(sd2_pads, - ARRAY_SIZE(sd2_pads)); - break; - default: - printf("Warning: you configured more ESDHC controller" - "(%d) as supported by the board(2)\n", - CONFIG_SYS_FSL_ESDHC_NUM); - return -EINVAL; - } - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} -#endif - -int board_early_init_f(void) -{ - setup_iomux_uart(); - setup_iomux_fec(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)}, - {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)}, - {NULL, 0}, -}; -#endif - -int board_late_init(void) -{ - setup_i2c(1); - power_init(); - -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - return 0; -} - -int checkboard(void) -{ - puts("Board: MX53EVK\n"); - - return 0; -} diff --git a/board/freescale/mx6qarm2/Kconfig b/board/freescale/mx6qarm2/Kconfig deleted file mode 100644 index 8ab8b460f9..0000000000 --- a/board/freescale/mx6qarm2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MX6QARM2 - -config SYS_BOARD - default "mx6qarm2" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mx6qarm2" - -endif diff --git a/board/freescale/mx6qarm2/MAINTAINERS b/board/freescale/mx6qarm2/MAINTAINERS deleted file mode 100644 index fdbc7fa725..0000000000 --- a/board/freescale/mx6qarm2/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -MX6QARM2 BOARD -M: Jason Liu <jason.hui.liu@nxp.com> -M: Ye Li <ye.li@nxp.com> -S: Maintained -F: board/freescale/mx6qarm2/ -F: include/configs/mx6qarm2.h -F: configs/mx6qarm2_defconfig -F: configs/mx6dlarm2_defconfig -F: configs/mx6qarm2_lpddr2_defconfig -F: configs/mx6dlarm2_lpddr2_defconfig diff --git a/board/freescale/mx6qarm2/Makefile b/board/freescale/mx6qarm2/Makefile deleted file mode 100644 index ef80a89672..0000000000 --- a/board/freescale/mx6qarm2/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. - -obj-y := mx6qarm2.o diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg deleted file mode 100644 index 74a33c2503..0000000000 --- a/board/freescale/mx6qarm2/imximage.cfg +++ /dev/null @@ -1,337 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. - * Jason Liu <r64343@freescale.com> - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -#ifdef CONFIG_MX6DQ_LPDDR2 -/* DCD */ -DATA 4 0x020C4018 0x60324 - -DATA 4 0x020E05a8 0x00003038 -DATA 4 0x020E05b0 0x00003038 -DATA 4 0x020E0524 0x00003038 -DATA 4 0x020E051c 0x00003038 - -DATA 4 0x020E0518 0x00003038 -DATA 4 0x020E050c 0x00003038 -DATA 4 0x020E05b8 0x00003038 -DATA 4 0x020E05c0 0x00003038 - -DATA 4 0x020E05ac 0x00000038 -DATA 4 0x020E05b4 0x00000038 -DATA 4 0x020E0528 0x00000038 -DATA 4 0x020E0520 0x00000038 - -DATA 4 0x020E0514 0x00000038 -DATA 4 0x020E0510 0x00000038 -DATA 4 0x020E05bc 0x00000038 -DATA 4 0x020E05c4 0x00000038 - -DATA 4 0x020E056c 0x00000038 -DATA 4 0x020E0578 0x00000038 -DATA 4 0x020E0588 0x00000038 -DATA 4 0x020E0594 0x00000038 - -DATA 4 0x020E057c 0x00000038 -DATA 4 0x020E0590 0x00000038 -DATA 4 0x020E0598 0x00000038 -DATA 4 0x020E058c 0x00000000 - -DATA 4 0x020E059c 0x00000038 -DATA 4 0x020E05a0 0x00000038 -DATA 4 0x020E0784 0x00000038 -DATA 4 0x020E0788 0x00000038 - -DATA 4 0x020E0794 0x00000038 -DATA 4 0x020E079c 0x00000038 -DATA 4 0x020E07a0 0x00000038 -DATA 4 0x020E07a4 0x00000038 - -DATA 4 0x020E07a8 0x00000038 -DATA 4 0x020E0748 0x00000038 -DATA 4 0x020E074c 0x00000038 -DATA 4 0x020E0750 0x00020000 - -DATA 4 0x020E0758 0x00000000 -DATA 4 0x020E0774 0x00020000 -DATA 4 0x020E078c 0x00000038 -DATA 4 0x020E0798 0x00080000 - -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b401c 0x00008000 - -DATA 4 0x021b085c 0x1b5f01ff -DATA 4 0x021b485c 0x1b5f01ff - -DATA 4 0x021b0800 0xa1390000 -DATA 4 0x021b4800 0xa1390000 - -DATA 4 0x021b0890 0x00400000 -DATA 4 0x021b4890 0x00400000 - -DATA 4 0x021b48bc 0x00055555 - -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b48b8 0x00000800 - -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 -DATA 4 0x021b481c 0x33333333 -DATA 4 0x021b4820 0x33333333 -DATA 4 0x021b4824 0x33333333 -DATA 4 0x021b4828 0x33333333 - -DATA 4 0x021b082c 0xf3333333 -DATA 4 0x021b0830 0xf3333333 -DATA 4 0x021b0834 0xf3333333 -DATA 4 0x021b0838 0xf3333333 -DATA 4 0x021b482c 0xf3333333 -DATA 4 0x021b4830 0xf3333333 -DATA 4 0x021b4834 0xf3333333 -DATA 4 0x021b4838 0xf3333333 - -DATA 4 0x021b0848 0x49383b39 -DATA 4 0x021b0850 0x30364738 -DATA 4 0x021b4848 0x3e3c3846 -DATA 4 0x021b4850 0x4c294b35 - -DATA 4 0x021b083c 0x20000000 -DATA 4 0x021b0840 0x0 -DATA 4 0x021b483c 0x20000000 -DATA 4 0x021b4840 0x0 - -DATA 4 0x021b0858 0xf00 -DATA 4 0x021b4858 0xf00 - -DATA 4 0x021b08b8 0x800 -DATA 4 0x021b48b8 0x800 - -DATA 4 0x021b000c 0x555a61a5 -DATA 4 0x021b0004 0x20036 -DATA 4 0x021b0010 0x160e83 -DATA 4 0x021b0014 0xdd -DATA 4 0x021b0018 0x8174c -DATA 4 0x021b002c 0xf9f26d2 -DATA 4 0x021b0030 0x20e -DATA 4 0x021b0038 0x200aac -DATA 4 0x021b0008 0x0 - -DATA 4 0x021b0040 0x5f - -DATA 4 0x021b0000 0xc3010000 - -DATA 4 0x021b400c 0x555a61a5 -DATA 4 0x021b4004 0x20036 -DATA 4 0x021b4010 0x160e83 -DATA 4 0x021b4014 0xdd -DATA 4 0x021b4018 0x8174c -DATA 4 0x021b402c 0xf9f26d2 -DATA 4 0x021b4030 0x20e -DATA 4 0x021b4038 0x200aac -DATA 4 0x021b4008 0x0 - -DATA 4 0x021b4040 0x3f -DATA 4 0x021b4000 0xc3010000 - -DATA 4 0x021b001c 0x3f8030 -DATA 4 0x021b001c 0xff0a8030 -DATA 4 0x021b001c 0xc2018030 -DATA 4 0x021b001c 0x6028030 -DATA 4 0x021b001c 0x2038030 - -DATA 4 0x021b401c 0x3f8030 -DATA 4 0x021b401c 0xff0a8030 -DATA 4 0x021b401c 0xc2018030 -DATA 4 0x021b401c 0x6028030 -DATA 4 0x021b401c 0x2038030 - -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b4800 0xa1390003 - -DATA 4 0x021b0020 0x7800 -DATA 4 0x021b4020 0x7800 - -DATA 4 0x021b0818 0x0 -DATA 4 0x021b4818 0x0 - -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b4800 0xa1390003 - -DATA 4 0x021b08b8 0x800 -DATA 4 0x021b48b8 0x800 - -DATA 4 0x021b001c 0x0 -DATA 4 0x021b401c 0x0 - -DATA 4 0x021b0404 0x00011006 - -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4 0x020e0010 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F - -#else -DATA 4 0x020e05a8 0x00000030 -DATA 4 0x020e05b0 0x00000030 -DATA 4 0x020e0524 0x00000030 -DATA 4 0x020e051c 0x00000030 - -DATA 4 0x020e0518 0x00000030 -DATA 4 0x020e050c 0x00000030 -DATA 4 0x020e05b8 0x00000030 -DATA 4 0x020e05c0 0x00000030 - -DATA 4 0x020e05ac 0x00020030 -DATA 4 0x020e05b4 0x00020030 -DATA 4 0x020e0528 0x00020030 -DATA 4 0x020e0520 0x00020030 - -DATA 4 0x020e0514 0x00020030 -DATA 4 0x020e0510 0x00020030 -DATA 4 0x020e05bc 0x00020030 -DATA 4 0x020e05c4 0x00020030 - -DATA 4 0x020e056c 0x00020030 -DATA 4 0x020e0578 0x00020030 -DATA 4 0x020e0588 0x00020030 -DATA 4 0x020e0594 0x00020030 - -DATA 4 0x020e057c 0x00020030 -DATA 4 0x020e0590 0x00003000 -DATA 4 0x020e0598 0x00003000 -DATA 4 0x020e058c 0x00000000 - -DATA 4 0x020e059c 0x00003030 -DATA 4 0x020e05a0 0x00003030 -DATA 4 0x020e0784 0x00000030 -DATA 4 0x020e0788 0x00000030 - -DATA 4 0x020e0794 0x00000030 -DATA 4 0x020e079c 0x00000030 -DATA 4 0x020e07a0 0x00000030 -DATA 4 0x020e07a4 0x00000030 - -DATA 4 0x020e07a8 0x00000030 -DATA 4 0x020e0748 0x00000030 -DATA 4 0x020e074c 0x00000030 -DATA 4 0x020e0750 0x00020000 - -DATA 4 0x020e0758 0x00000000 -DATA 4 0x020e0774 0x00020000 -DATA 4 0x020e078c 0x00000030 -DATA 4 0x020e0798 0x000C0000 - -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 - -DATA 4 0x021b481c 0x33333333 -DATA 4 0x021b4820 0x33333333 -DATA 4 0x021b4824 0x33333333 -DATA 4 0x021b4828 0x33333333 - -DATA 4 0x021b0018 0x00081740 - -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b000c 0x555A7975 -DATA 4 0x021b0010 0xFF538E64 -DATA 4 0x021b0014 0x01FF00DB -DATA 4 0x021b002c 0x000026D2 - -DATA 4 0x021b0030 0x005B0E21 -DATA 4 0x021b0008 0x09444040 -DATA 4 0x021b0004 0x00025576 -DATA 4 0x021b0040 0x00000027 -DATA 4 0x021b0000 0xC31A0000 - -DATA 4 0x021b001c 0x04088032 -DATA 4 0x021b001c 0x0408803A -DATA 4 0x021b001c 0x00008033 -DATA 4 0x021b001c 0x0000803B -DATA 4 0x021b001c 0x00428031 -DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x09408030 -DATA 4 0x021b001c 0x09408038 - -DATA 4 0x021b001c 0x04008040 -DATA 4 0x021b001c 0x04008048 -DATA 4 0x021b0800 0xA1380003 -DATA 4 0x021b4800 0xA1380003 -DATA 4 0x021b0020 0x00005800 -DATA 4 0x021b0818 0x00022227 -DATA 4 0x021b4818 0x00022227 - -DATA 4 0x021b083c 0x434B0350 -DATA 4 0x021b0840 0x034C0359 -DATA 4 0x021b483c 0x434B0350 -DATA 4 0x021b4840 0x03650348 -DATA 4 0x021b0848 0x4436383B -DATA 4 0x021b4848 0x39393341 -DATA 4 0x021b0850 0x35373933 -DATA 4 0x021b4850 0x48254A36 - -DATA 4 0x021b080c 0x001F001F -DATA 4 0x021b0810 0x001F001F - -DATA 4 0x021b480c 0x00440044 -DATA 4 0x021b4810 0x00440044 - -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b48b8 0x00000800 - -DATA 4 0x021b001c 0x00000000 -DATA 4 0x021b0404 0x00011006 - -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4 0x020e0010 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F - -#endif /* CONFIG_MX6DQ_LPDDR2 */ diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg deleted file mode 100644 index 0d1353119b..0000000000 --- a/board/freescale/mx6qarm2/imximage_mx6dl.cfg +++ /dev/null @@ -1,461 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - * Jason Liu <r64343@freescale.com> - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - - - -#ifdef CONFIG_MX6DL_LPDDR2 - -/* IOMUX SETTINGS */ -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */ -DATA 4 0x020E04bc 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ -DATA 4 0x020E04c0 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */ -DATA 4 0x020E04c4 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */ -DATA 4 0x020E04c8 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */ -DATA 4 0x020E04cc 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */ -DATA 4 0x020E04d0 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */ -DATA 4 0x020E04d4 0x00003028 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */ -DATA 4 0x020E04d8 0x00003028 - -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ -DATA 4 0x020E0470 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ -DATA 4 0x020E0474 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */ -DATA 4 0x020E0478 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */ -DATA 4 0x020E047c 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */ -DATA 4 0x020E0480 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */ -DATA 4 0x020E0484 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */ -DATA 4 0x020E0488 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */ -DATA 4 0x020E048c 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ -DATA 4 0x020E0464 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ -DATA 4 0x020E0490 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ -DATA 4 0x020E04ac 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */ -DATA 4 0x020E04b0 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ -DATA 4 0x020E0494 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */ -DATA 4 0x020E04a4 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */ -DATA 4 0x020E04a8 0x00000038 -/* - * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - * DSE can be configured using Group Control Register: - * IOMUXC_SW_PAD_CTL_GRP_CTLDS - */ -DATA 4 0x020E04a0 0x00000000 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */ -DATA 4 0x020E04b4 0x00000038 -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */ -DATA 4 0x020E04b8 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B0DS */ -DATA 4 0x020E0764 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B1DS */ -DATA 4 0x020E0770 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B2DS */ -DATA 4 0x020E0778 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B3DS */ -DATA 4 0x020E077c 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B4DS */ -DATA 4 0x020E0780 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B5DS */ -DATA 4 0x020E0784 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B6DS */ -DATA 4 0x020E078c 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_B7DS */ -DATA 4 0x020E0748 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ -DATA 4 0x020E074c 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ -DATA 4 0x020E076c 0x00000038 -/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ -DATA 4 0x020E0750 0x00020000 -/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ -DATA 4 0x020E0754 0x00000000 -/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ -DATA 4 0x020E0760 0x00020000 -/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ -DATA 4 0x020E0774 0x00080000 - -/* - * DDR Controller Registers - * - * Manufacturer: Mocron - * Device Part Number: MT42L64M64D2KH-18 - * Clock Freq.: 528MHz - * MMDC channels: Both MMDC0, MMDC1 - *Density per CS in Gb: 256M - * Chip Selects used: 2 - * Number of Banks: 8 - * Row address: 14 - * Column address: 9 - * Data bus width 32 - */ - -/* MMDC_P0_BASE_ADDR = 0x021b0000 */ -/* MMDC_P1_BASE_ADDR = 0x021b4000 */ - -/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ -DATA 4 0x021b001c 0x00008000 - -/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ -DATA 4 0x021b401c 0x00008000 - -/*LPDDR2 ZQ params */ -DATA 4 0x021b085c 0x1b5f01ff -DATA 4 0x021b485c 0x1b5f01ff - -/* Calibration setup. */ -/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */ -DATA 4 0x021b0800 0xa1390003 - -/*ca bus abs delay */ -DATA 4 0x021b0890 0x00400000 -/*ca bus abs delay */ -DATA 4 0x021b4890 0x00400000 -/* values of 20,40,50,60,7f tried. no difference seen */ - -/* DDR_PHY_P1_MPWRCADL */ -DATA 4 0x021b48bc 0x00055555 - -/*frc_msr.*/ -DATA 4 0x021b08b8 0x00000800 -/*frc_msr.*/ -DATA 4 0x021b48b8 0x00000800 - -/* DDR_PHY_P0_MPREDQBY0DL3 */ -DATA 4 0x021b081c 0x33333333 -/* DDR_PHY_P0_MPREDQBY1DL3 */ -DATA 4 0x021b0820 0x33333333 -/* DDR_PHY_P0_MPREDQBY2DL3 */ -DATA 4 0x021b0824 0x33333333 -/* DDR_PHY_P0_MPREDQBY3DL3 */ -DATA 4 0x021b0828 0x33333333 -/* DDR_PHY_P1_MPREDQBY0DL3 */ -DATA 4 0x021b481c 0x33333333 -/* DDR_PHY_P1_MPREDQBY1DL3 */ -DATA 4 0x021b4820 0x33333333 -/* DDR_PHY_P1_MPREDQBY2DL3 */ -DATA 4 0x021b4824 0x33333333 -/* DDR_PHY_P1_MPREDQBY3DL3 */ -DATA 4 0x021b4828 0x33333333 - -/* - * Read and write data delay, per byte. - * For optimized DDR operation it is recommended to run mmdc_calibration - * on your board, and replace 4 delay register assigns with resulted values - * Note: - * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section - * should be skipped, or the write/read calibration comming after that - * will stall - * b. The calibration code that runs for both MMDC0 & MMDC1 should be used. - */ - -DATA 4 0x021b0848 0x4b4b524f -DATA 4 0x021b4848 0x494f4c44 - -DATA 4 0x021b0850 0x3c3d303c -DATA 4 0x021b4850 0x3c343d38 - -/*dqs gating dis */ -DATA 4 0x021b083c 0x20000000 -DATA 4 0x021b0840 0x0 -DATA 4 0x021b483c 0x20000000 -DATA 4 0x021b4840 0x0 - -/*clk delay */ -DATA 4 0x021b0858 0xa00 -/*clk delay */ -DATA 4 0x021b4858 0xa00 - -/*frc_msr */ -DATA 4 0x021b08b8 0x00000800 -/*frc_msr */ -DATA 4 0x021b48b8 0x00000800 -/* Calibration setup end */ - -/* Channel0 - startng address 0x80000000 */ -/* MMDC0_MDCFG0 */ -DATA 4 0x021b000c 0x34386145 - -/* MMDC0_MDPDC */ -DATA 4 0x021b0004 0x00020036 -/* MMDC0_MDCFG1 */ -DATA 4 0x021b0010 0x00100c83 -/* MMDC0_MDCFG2 */ -DATA 4 0x021b0014 0x000000Dc -/* MMDC0_MDMISC */ -DATA 4 0x021b0018 0x0000174C -/* MMDC0_MDRWD;*/ -DATA 4 0x021b002c 0x0f9f26d2 -/* MMDC0_MDOR */ -DATA 4 0x021b0030 0x009f0e10 -/* MMDC0_MDCFG3LP */ -DATA 4 0x021b0038 0x00190778 -/* MMDC0_MDOTC */ -DATA 4 0x021b0008 0x00000000 - -/* CS0_END */ -DATA 4 0x021b0040 0x0000005f -/* ROC */ -DATA 4 0x021b0404 0x0000000f - -/* MMDC0_MDCTL */ -DATA 4 0x021b0000 0xc3010000 - -/* Channel1 - starting address 0x10000000 */ -/* MMDC1_MDCFG0 */ -DATA 4 0x021b400c 0x34386145 - -/* MMDC1_MDPDC */ -DATA 4 0x021b4004 0x00020036 -/* MMDC1_MDCFG1 */ -DATA 4 0x021b4010 0x00100c83 -/* MMDC1_MDCFG2 */ -DATA 4 0x021b4014 0x000000Dc -/* MMDC1_MDMISC */ -DATA 4 0x021b4018 0x0000174C -/* MMDC1_MDRWD;*/ -DATA 4 0x021b402c 0x0f9f26d2 -/* MMDC1_MDOR */ -DATA 4 0x021b4030 0x009f0e10 -/* MMDC1_MDCFG3LP */ -DATA 4 0x021b4038 0x00190778 -/* MMDC1_MDOTC */ -DATA 4 0x021b4008 0x00000000 - -/* CS0_END */ -DATA 4 0x021b4040 0x0000003f - -/* MMDC1_MDCTL */ -DATA 4 0x021b4000 0xc3010000 - -/* Channel0 : Configure DDR device:*/ -/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ -DATA 4 0x021b001c 0x003f8030 -/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ -DATA 4 0x021b001c 0xff0a8030 -/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ -DATA 4 0x021b001c 0xa2018030 -/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ -DATA 4 0x021b001c 0x06028030 -/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ -DATA 4 0x021b001c 0x01038030 - -/* Channel1 : Configure DDR device:*/ -/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ -DATA 4 0x021b401c 0x003f8030 -/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ -DATA 4 0x021b401c 0xff0a8030 -/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ -DATA 4 0x021b401c 0xa2018030 -/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ -DATA 4 0x021b401c 0x06028030 -/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ -DATA 4 0x021b401c 0x01038030 - -/* MMDC0_MDREF */ -DATA 4 0x021b0020 0x00005800 -/* MMDC1_MDREF */ -DATA 4 0x021b4020 0x00005800 - -/* DDR_PHY_P0_MPODTCTRL */ -DATA 4 0x021b0818 0x0 -/* DDR_PHY_P1_MPODTCTRL */ -DATA 4 0x021b4818 0x0 - -/* - * calibration values based on calibration compare of 0x00ffff00: - * Note, these calibration values are based on Freescale's board - * May need to run calibration on target board to fine tune these - */ - -/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */ -DATA 4 0x021b0800 0xa1310003 - -/* DDR_PHY_P0_MPMUR0, frc_msr */ -DATA 4 0x021b08b8 0x00000800 -/* DDR_PHY_P1_MPMUR0, frc_msr */ -DATA 4 0x021b48b8 0x00000800 - -/* - * MMDC0_MDSCR, clear this register - * (especially the configuration bit as initialization is complete) - */ -DATA 4 0x021b001c 0x00000000 -/* - * MMDC0_MDSCR, clear this register - * (especially the configuration bit as initialization is complete) - */ -DATA 4 0x021b401c 0x00000000 - -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -DATA 4 0x020e0010 0xF00000CF -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F - -#else /* CONFIG_MX6DL_LPDDR2 */ - -DATA 4 0x020e0798 0x000c0000 -DATA 4 0x020e0758 0x00000000 -DATA 4 0x020e0588 0x00000030 -DATA 4 0x020e0594 0x00000030 -DATA 4 0x020e056c 0x00000030 -DATA 4 0x020e0578 0x00000030 -DATA 4 0x020e074c 0x00000030 -DATA 4 0x020e057c 0x00000030 -DATA 4 0x020e0590 0x00003000 -DATA 4 0x020e0598 0x00003000 -DATA 4 0x020e058c 0x00000000 -DATA 4 0x020e059c 0x00003030 -DATA 4 0x020e05a0 0x00003030 -DATA 4 0x020e078c 0x00000030 -DATA 4 0x020e0750 0x00020000 -DATA 4 0x020e05a8 0x00000030 -DATA 4 0x020e05b0 0x00000030 -DATA 4 0x020e0524 0x00000030 -DATA 4 0x020e051c 0x00000030 -DATA 4 0x020e0518 0x00000030 -DATA 4 0x020e050c 0x00000030 -DATA 4 0x020e05b8 0x00000030 -DATA 4 0x020e05c0 0x00000030 -DATA 4 0x020e0774 0x00020000 -DATA 4 0x020e0784 0x00000030 -DATA 4 0x020e0788 0x00000030 -DATA 4 0x020e0794 0x00000030 -DATA 4 0x020e079c 0x00000030 -DATA 4 0x020e07a0 0x00000030 -DATA 4 0x020e07a4 0x00000030 -DATA 4 0x020e07a8 0x00000030 -DATA 4 0x020e0748 0x00000030 -DATA 4 0x020e05ac 0x00000030 -DATA 4 0x020e05b4 0x00000030 -DATA 4 0x020e0528 0x00000030 -DATA 4 0x020e0520 0x00000030 -DATA 4 0x020e0514 0x00000030 -DATA 4 0x020e0510 0x00000030 -DATA 4 0x020e05bc 0x00000030 -DATA 4 0x020e05c4 0x00000030 - -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b4800 0xa1390003 -DATA 4 0x021b080c 0x001F001F -DATA 4 0x021b0810 0x001F001F -DATA 4 0x021b480c 0x00370037 -DATA 4 0x021b4810 0x00370037 -DATA 4 0x021b083c 0x422f0220 -DATA 4 0x021b0840 0x021f0219 -DATA 4 0x021b483C 0x422f0220 -DATA 4 0x021b4840 0x022d022f -DATA 4 0x021b0848 0x47494b49 -DATA 4 0x021b4848 0x48484c47 -DATA 4 0x021b0850 0x39382b2f -DATA 4 0x021b4850 0x2f35312c -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 -DATA 4 0x021b481c 0x33333333 -DATA 4 0x021b4820 0x33333333 -DATA 4 0x021b4824 0x33333333 -DATA 4 0x021b4828 0x33333333 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b48b8 0x00000800 -DATA 4 0x021b0004 0x0002002d -DATA 4 0x021b0008 0x00333030 - -DATA 4 0x021b000c 0x40445323 -DATA 4 0x021b0010 0xb66e8c63 - -DATA 4 0x021b0014 0x01ff00db -DATA 4 0x021b0018 0x00081740 -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b002c 0x000026d2 -DATA 4 0x021b0030 0x00440e21 -#ifdef CONFIG_DDR_32BIT -DATA 4 0x021b0040 0x00000017 -DATA 4 0x021b0000 0xc3190000 -#else -DATA 4 0x021b0040 0x00000027 -DATA 4 0x021b0000 0xc31a0000 -#endif -DATA 4 0x021b001c 0x04008032 -DATA 4 0x021b001c 0x0400803a -DATA 4 0x021b001c 0x00008033 -DATA 4 0x021b001c 0x0000803b -DATA 4 0x021b001c 0x00428031 -DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x07208030 -DATA 4 0x021b001c 0x07208038 -DATA 4 0x021b001c 0x04008040 -DATA 4 0x021b001c 0x04008048 -DATA 4 0x021b0020 0x00005800 -DATA 4 0x021b0818 0x00000007 -DATA 4 0x021b4818 0x00000007 -DATA 4 0x021b0004 0x0002556d -DATA 4 0x021b4004 0x00011006 -DATA 4 0x021b001c 0x00000000 - -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -DATA 4 0x020e0010 0xF00000CF -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F -#endif /* CONFIG_MX6DL_LPDDR2 */ diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c deleted file mode 100644 index c06fd64367..0000000000 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ /dev/null @@ -1,290 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/clock.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <miiphy.h> -#include <netdev.h> -#include <usb.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -int dram_init(void) -{ -#if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \ - defined(CONFIG_DDR_32BIT) - gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2; -#else - gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; -#endif - - return 0; -} - -iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); -} - -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); -} - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -int board_mmc_get_env_dev(int devno) -{ - return devno - 2; -} - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; - - if (cfg->esdhc_base == USDHC3_BASE_ADDR) { - gpio_direction_input(IMX_GPIO_NR(6, 11)); - ret = !gpio_get_value(IMX_GPIO_NR(6, 11)); - } else /* Don't have the CD GPIO pin on board */ - ret = 1; - - return ret; -} - -int board_mmc_init(struct bd_info *bis) -{ - int ret; - u32 index = 0; - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} -#endif - -#define MII_MMD_ACCESS_CTRL_REG 0xd -#define MII_MMD_ACCESS_ADDR_DATA_REG 0xe -#define MII_DBG_PORT_REG 0x1d -#define MII_DBG_PORT2_REG 0x1e - -int fecmxc_mii_postcall(int phy) -{ - unsigned short val; - - /* - * Due to the i.MX6Q Armadillo2 board HW design,there is - * no 125Mhz clock input from SOC. In order to use RGMII, - * We need enable AR8031 ouput a 125MHz clk from CLK_25M - */ - miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7); - miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016); - miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007); - miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val); - val &= 0xffe3; - val |= 0x18; - miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val); - - /* For the RGMII phy, we need enable tx clock delay */ - miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5); - miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val); - val |= 0x0100; - miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val); - - miiphy_write("FEC", phy, MII_BMCR, 0xa100); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - struct eth_device *dev; - int ret = cpu_eth_init(bis); - - if (ret) - return ret; - - dev = eth_get_dev_by_name("FEC"); - if (!dev) { - printf("FEC MXC: Unable to get FEC device entry\n"); - return -EINVAL; - } - - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - printf("FEC MXC: Unable to register FEC mii postcall\n"); - return ret; - } - - return 0; -} - -#ifdef CONFIG_USB_EHCI_MX6 -#define USB_OTHERREGS_OFFSET 0x800 -#define UCTRL_PWR_POL (1 << 9) - -static iomux_v3_cfg_t const usb_otg_pads[] = { - MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_usb(void) -{ - imx_iomux_v3_setup_multiple_pads(usb_otg_pads, - ARRAY_SIZE(usb_otg_pads)); - - /* - * set daisy chain for otg_pin_id on 6q. - * for 6dl, this bit is reserved - */ - imx_iomux_set_gpr_register(1, 13, 1, 1); -} - -int board_ehci_hcd_init(int port) -{ - u32 *usbnc_usb_ctrl; - - if (port > 0) - return -EINVAL; - - usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + - port * 4); - - setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); - - return 0; -} -#endif - -int board_early_init_f(void) -{ - setup_iomux_uart(); - setup_iomux_enet(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifdef CONFIG_USB_EHCI_MX6 - setup_usb(); -#endif - - return 0; -} - -int checkboard(void) -{ -#ifdef CONFIG_MX6DL - puts("Board: MX6DL-Armadillo2\n"); -#else - puts("Board: MX6Q-Armadillo2\n"); -#endif - - return 0; -} diff --git a/board/freescale/s32v234evb/Kconfig b/board/freescale/s32v234evb/Kconfig deleted file mode 100644 index e71dfc4ab2..0000000000 --- a/board/freescale/s32v234evb/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -if TARGET_S32V234EVB - -config SYS_CPU - string - default "armv8" - -config SYS_BOARD - string - default "s32v234evb" - -config SYS_VENDOR - string - default "freescale" - -config SYS_SOC - string - default "s32v234" - -config SYS_CONFIG_NAME - string - default "s32v234evb" - -endif diff --git a/board/freescale/s32v234evb/MAINTAINERS b/board/freescale/s32v234evb/MAINTAINERS deleted file mode 100644 index 62b2e1b264..0000000000 --- a/board/freescale/s32v234evb/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -S32V234 Evaluation BOARD -M: Eddy PetriČ™or <eddy.petrisor@gmail.com> -S: Maintained -F: arch/arm/cpu/armv8/s32v234/ -F: arch/arm/include/asm/arch-s32v234/ -F: board/freescale/s32v234evb/ -F: include/configs/s32v234evb.h -F: configs/s32v234evb_defconfig diff --git a/board/freescale/s32v234evb/Makefile b/board/freescale/s32v234evb/Makefile deleted file mode 100644 index f6028e1277..0000000000 --- a/board/freescale/s32v234evb/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2013-2015, Freescale Semiconductor, Inc. - -obj-y := clock.o -obj-y += lpddr2.o -obj-y += s32v234evb.o - -######################################################################### diff --git a/board/freescale/s32v234evb/clock.c b/board/freescale/s32v234evb/clock.c deleted file mode 100644 index 21c619fa1a..0000000000 --- a/board/freescale/s32v234evb/clock.c +++ /dev/null @@ -1,343 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mc_cgm_regs.h> -#include <asm/arch/mc_me_regs.h> -#include <asm/arch/clock.h> - -/* - * Select the clock reference for required pll. - * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL. - * refclk_freq - input referece clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ) - */ -static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq) -{ - u32 clk_src; - u32 pll_idx; - volatile struct src *src = (struct src *)SRC_SOC_BASE_ADDR; - - /* select the pll clock source */ - switch (refclk_freq) { - case FIRC_CLK_FREQ: - clk_src = SRC_GPR1_FIRC_CLK_SOURCE; - break; - case XOSC_CLK_FREQ: - clk_src = SRC_GPR1_XOSC_CLK_SOURCE; - break; - default: - /* The clock frequency for the source clock is unknown */ - return -1; - } - /* - * The hardware definition is not uniform, it has to calculate again - * the recurrence formula. - */ - switch (pll) { - case PERIPH_PLL: - pll_idx = 3; - break; - case ENET_PLL: - pll_idx = 1; - break; - case DDR_PLL: - pll_idx = 2; - break; - default: - pll_idx = pll; - } - - writel(readl(&src->gpr1) | SRC_GPR1_PLL_SOURCE(pll_idx, clk_src), - &src->gpr1); - - return 0; -} - -static void entry_to_target_mode(u32 mode) -{ - writel(mode | MC_ME_MCTL_KEY, MC_ME_MCTL); - writel(mode | MC_ME_MCTL_INVERTEDKEY, MC_ME_MCTL); - while ((readl(MC_ME_GS) & MC_ME_GS_S_MTRANS) != 0x00000000) ; -} - -/* - * Program the pll according to the input parameters. - * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL. - * refclk_freq - input reference clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ) - * freq - expected output frequency for PHY0 - * freq1 - expected output frequency for PHY1 - * dfs_nr - number of DFS modules for current PLL - * dfs - array with the activation dfs field, mfn and mfi - * plldv_prediv - divider of clkfreq_ref - * plldv_mfd - loop multiplication factor divider - * pllfd_mfn - numerator loop multiplication factor divider - * Please consult the PLLDIG chapter of platform manual - * before to use this function. - *) - */ -static int program_pll(enum pll_type pll, u32 refclk_freq, u32 freq0, u32 freq1, - u32 dfs_nr, u32 dfs[][DFS_PARAMS_Nr], u32 plldv_prediv, - u32 plldv_mfd, u32 pllfd_mfn) -{ - u32 i, rfdphi1, rfdphi, dfs_on = 0, fvco; - - /* - * This formula is from platform reference manual (Rev. 1, 6/2015), PLLDIG chapter. - */ - fvco = - (refclk_freq / plldv_prediv) * (plldv_mfd + - pllfd_mfn / (float)20480); - - /* - * VCO should have value in [ PLL_MIN_FREQ, PLL_MAX_FREQ ]. Please consult - * the platform DataSheet in order to determine the allowed values. - */ - - if (fvco < PLL_MIN_FREQ || fvco > PLL_MAX_FREQ) { - return -1; - } - - if (select_pll_source_clk(pll, refclk_freq) < 0) { - return -1; - } - - rfdphi = fvco / freq0; - - rfdphi1 = (freq1 == 0) ? 0 : fvco / freq1; - - writel(PLLDIG_PLLDV_RFDPHI1_SET(rfdphi1) | - PLLDIG_PLLDV_RFDPHI_SET(rfdphi) | - PLLDIG_PLLDV_PREDIV_SET(plldv_prediv) | - PLLDIG_PLLDV_MFD(plldv_mfd), PLLDIG_PLLDV(pll)); - - writel(readl(PLLDIG_PLLFD(pll)) | PLLDIG_PLLFD_MFN_SET(pllfd_mfn) | - PLLDIG_PLLFD_SMDEN, PLLDIG_PLLFD(pll)); - - /* switch on the pll in current mode */ - writel(readl(MC_ME_RUNn_MC(0)) | MC_ME_RUNMODE_MC_PLL(pll), - MC_ME_RUNn_MC(0)); - - entry_to_target_mode(MC_ME_MCTL_RUN0); - - /* Only ARM_PLL, ENET_PLL and DDR_PLL */ - if ((pll == ARM_PLL) || (pll == ENET_PLL) || (pll == DDR_PLL)) { - /* DFS clk enable programming */ - writel(DFS_CTRL_DLL_RESET, DFS_CTRL(pll)); - - writel(DFS_DLLPRG1_CPICTRL_SET(0x5) | - DFS_DLLPRG1_VSETTLCTRL_SET(0x1) | - DFS_DLLPRG1_CALBYPEN_SET(0x0) | - DFS_DLLPRG1_DACIN_SET(0x1) | DFS_DLLPRG1_LCKWT_SET(0x0) | - DFS_DLLPRG1_V2IGC_SET(0x5), DFS_DLLPRG1(pll)); - - for (i = 0; i < dfs_nr; i++) { - if (dfs[i][0]) { - writel(DFS_DVPORTn_MFI_SET(dfs[i][2]) | - DFS_DVPORTn_MFN_SET(dfs[i][1]), - DFS_DVPORTn(pll, i)); - dfs_on |= (dfs[i][0] << i); - } - } - - writel(readl(DFS_CTRL(pll)) & ~DFS_CTRL_DLL_RESET, - DFS_CTRL(pll)); - writel(readl(DFS_PORTRESET(pll)) & - ~DFS_PORTRESET_PORTRESET_SET(dfs_on), - DFS_PORTRESET(pll)); - while ((readl(DFS_PORTSR(pll)) & dfs_on) != dfs_on) ; - } - - entry_to_target_mode(MC_ME_MCTL_RUN0); - - return 0; - -} - -static void aux_source_clk_config(uintptr_t cgm_addr, u8 ac, u32 source) -{ - /* select the clock source */ - writel(MC_CGM_ACn_SEL_SET(source), CGM_ACn_SC(cgm_addr, ac)); -} - -static void aux_div_clk_config(uintptr_t cgm_addr, u8 ac, u8 dc, u32 divider) -{ - /* set the divider */ - writel(MC_CGM_ACn_DCm_DE | MC_CGM_ACn_DCm_PREDIV(divider), - CGM_ACn_DCm(cgm_addr, ac, dc)); -} - -static void setup_sys_clocks(void) -{ - - /* set ARM PLL DFS 1 as SYSCLK */ - writel((readl(MC_ME_RUNn_MC(0)) & ~MC_ME_RUNMODE_MC_SYSCLK_MASK) | - MC_ME_RUNMODE_MC_SYSCLK(0x2), MC_ME_RUNn_MC(0)); - - entry_to_target_mode(MC_ME_MCTL_RUN0); - - /* select sysclks ARMPLL, ARMPLLDFS2, ARMPLLDFS3 */ - writel(MC_ME_RUNMODE_SEC_CC_I_SYSCLK - (0x2, - MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET) | - MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2, - MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET) - | MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2, - MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET), - MC_ME_RUNn_SEC_CC_I(0)); - - /* setup the sys clock divider for CORE_CLK (1000MHz) */ - writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0), - CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)); - - /* setup the sys clock divider for CORE2_CLK (500MHz) */ - writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1), - CGM_SC_DCn(MC_CGM1_BASE_ADDR, 1)); - /* setup the sys clock divider for SYS3_CLK (266 MHz) */ - writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0), - CGM_SC_DCn(MC_CGM0_BASE_ADDR, 0)); - - /* setup the sys clock divider for SYS6_CLK (133 Mhz) */ - writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1), - CGM_SC_DCn(MC_CGM0_BASE_ADDR, 1)); - - entry_to_target_mode(MC_ME_MCTL_RUN0); - -} - -static void setup_aux_clocks(void) -{ - /* - * setup the aux clock divider for PERI_CLK - * (source: PERIPH_PLL_PHI_0/5, PERI_CLK - 80 MHz) - */ - aux_source_clk_config(MC_CGM0_BASE_ADDR, 5, MC_CGM_ACn_SEL_PERPLLDIVX); - aux_div_clk_config(MC_CGM0_BASE_ADDR, 5, 0, 4); - - /* setup the aux clock divider for LIN_CLK (40MHz) */ - aux_source_clk_config(MC_CGM0_BASE_ADDR, 3, MC_CGM_ACn_SEL_PERPLLDIVX); - aux_div_clk_config(MC_CGM0_BASE_ADDR, 3, 0, 1); - - /* setup the aux clock divider for ENET_TIME_CLK (50MHz) */ - aux_source_clk_config(MC_CGM0_BASE_ADDR, 7, MC_CGM_ACn_SEL_ENETPLL); - aux_div_clk_config(MC_CGM0_BASE_ADDR, 7, 1, 9); - - /* setup the aux clock divider for ENET_CLK (50MHz) */ - aux_source_clk_config(MC_CGM2_BASE_ADDR, 2, MC_CGM_ACn_SEL_ENETPLL); - aux_div_clk_config(MC_CGM2_BASE_ADDR, 2, 0, 9); - - /* setup the aux clock divider for SDHC_CLK (50 MHz). */ - aux_source_clk_config(MC_CGM0_BASE_ADDR, 15, MC_CGM_ACn_SEL_ENETPLL); - aux_div_clk_config(MC_CGM0_BASE_ADDR, 15, 0, 9); - - /* setup the aux clock divider for DDR_CLK (533MHz) and APEX_SYS_CLK (266MHz) */ - aux_source_clk_config(MC_CGM0_BASE_ADDR, 8, MC_CGM_ACn_SEL_DDRPLL); - aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 0, 0); - /* setup the aux clock divider for DDR4_CLK (133,25MHz) */ - aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 1, 3); - - entry_to_target_mode(MC_ME_MCTL_RUN0); - -} - -static void enable_modules_clock(void) -{ - /* PIT0 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL58); - /* PIT1 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL170); - /* LINFLEX0 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL83); - /* LINFLEX1 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL188); - /* ENET */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL50); - /* SDHC */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL93); - /* IIC0 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL81); - /* IIC1 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL184); - /* IIC2 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL186); - /* MMDC0 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL54); - /* MMDC1 */ - writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL162); - - entry_to_target_mode(MC_ME_MCTL_RUN0); -} - -void clock_init(void) -{ - unsigned int arm_dfs[ARM_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = { - {ARM_PLL_PHI1_DFS1_EN, ARM_PLL_PHI1_DFS1_MFN, - ARM_PLL_PHI1_DFS1_MFI}, - {ARM_PLL_PHI1_DFS2_EN, ARM_PLL_PHI1_DFS2_MFN, - ARM_PLL_PHI1_DFS2_MFI}, - {ARM_PLL_PHI1_DFS3_EN, ARM_PLL_PHI1_DFS3_MFN, - ARM_PLL_PHI1_DFS3_MFI} - }; - - unsigned int enet_dfs[ENET_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = { - {ENET_PLL_PHI1_DFS1_EN, ENET_PLL_PHI1_DFS1_MFN, - ENET_PLL_PHI1_DFS1_MFI}, - {ENET_PLL_PHI1_DFS2_EN, ENET_PLL_PHI1_DFS2_MFN, - ENET_PLL_PHI1_DFS2_MFI}, - {ENET_PLL_PHI1_DFS3_EN, ENET_PLL_PHI1_DFS3_MFN, - ENET_PLL_PHI1_DFS3_MFI}, - {ENET_PLL_PHI1_DFS4_EN, ENET_PLL_PHI1_DFS4_MFN, - ENET_PLL_PHI1_DFS4_MFI} - }; - - unsigned int ddr_dfs[DDR_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = { - {DDR_PLL_PHI1_DFS1_EN, DDR_PLL_PHI1_DFS1_MFN, - DDR_PLL_PHI1_DFS1_MFI}, - {DDR_PLL_PHI1_DFS2_EN, DDR_PLL_PHI1_DFS2_MFN, - DDR_PLL_PHI1_DFS2_MFI}, - {DDR_PLL_PHI1_DFS3_EN, DDR_PLL_PHI1_DFS3_MFN, - DDR_PLL_PHI1_DFS3_MFI} - }; - - writel(MC_ME_RUN_PCn_DRUN | MC_ME_RUN_PCn_RUN0 | MC_ME_RUN_PCn_RUN1 | - MC_ME_RUN_PCn_RUN2 | MC_ME_RUN_PCn_RUN3, MC_ME_RUN_PCn(0)); - - /* turn on FXOSC */ - writel(MC_ME_RUNMODE_MC_MVRON | MC_ME_RUNMODE_MC_XOSCON | - MC_ME_RUNMODE_MC_FIRCON | MC_ME_RUNMODE_MC_SYSCLK(0x1), - MC_ME_RUNn_MC(0)); - - entry_to_target_mode(MC_ME_MCTL_RUN0); - - program_pll(ARM_PLL, XOSC_CLK_FREQ, ARM_PLL_PHI0_FREQ, - ARM_PLL_PHI1_FREQ, ARM_PLL_PHI1_DFS_Nr, arm_dfs, - ARM_PLL_PLLDV_PREDIV, ARM_PLL_PLLDV_MFD, ARM_PLL_PLLDV_MFN); - - setup_sys_clocks(); - - program_pll(PERIPH_PLL, XOSC_CLK_FREQ, PERIPH_PLL_PHI0_FREQ, - PERIPH_PLL_PHI1_FREQ, PERIPH_PLL_PHI1_DFS_Nr, NULL, - PERIPH_PLL_PLLDV_PREDIV, PERIPH_PLL_PLLDV_MFD, - PERIPH_PLL_PLLDV_MFN); - - program_pll(ENET_PLL, XOSC_CLK_FREQ, ENET_PLL_PHI0_FREQ, - ENET_PLL_PHI1_FREQ, ENET_PLL_PHI1_DFS_Nr, enet_dfs, - ENET_PLL_PLLDV_PREDIV, ENET_PLL_PLLDV_MFD, - ENET_PLL_PLLDV_MFN); - - program_pll(DDR_PLL, XOSC_CLK_FREQ, DDR_PLL_PHI0_FREQ, - DDR_PLL_PHI1_FREQ, DDR_PLL_PHI1_DFS_Nr, ddr_dfs, - DDR_PLL_PLLDV_PREDIV, DDR_PLL_PLLDV_MFD, DDR_PLL_PLLDV_MFN); - - program_pll(VIDEO_PLL, XOSC_CLK_FREQ, VIDEO_PLL_PHI0_FREQ, - VIDEO_PLL_PHI1_FREQ, VIDEO_PLL_PHI1_DFS_Nr, NULL, - VIDEO_PLL_PLLDV_PREDIV, VIDEO_PLL_PLLDV_MFD, - VIDEO_PLL_PLLDV_MFN); - - setup_aux_clocks(); - - enable_modules_clock(); - -} diff --git a/board/freescale/s32v234evb/lpddr2.c b/board/freescale/s32v234evb/lpddr2.c deleted file mode 100644 index b3775d3763..0000000000 --- a/board/freescale/s32v234evb/lpddr2.c +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015, Freescale Semiconductor, Inc. - */ - -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/siul.h> -#include <asm/arch/lpddr2.h> -#include <asm/arch/mmdc.h> - -volatile int mscr_offset_ck0; - -void lpddr2_config_iomux(uint8_t module) -{ - int i; - - switch (module) { - case DDR0: - mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0); - writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0)); - - writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0)); - writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1)); - - writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0)); - writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1)); - - for (i = _DDR0_DM0; i <= _DDR0_DM3; i++) - writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR0_DQS0; i <= _DDR0_DQS3; i++) - writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR0_A0; i <= _DDR0_A9; i++) - writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR0_D0; i <= _DDR0_D31; i++) - writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); - break; - case DDR1: - writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0)); - - writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0)); - writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1)); - - writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0)); - writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1)); - - for (i = _DDR1_DM0; i <= _DDR1_DM3; i++) - writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR1_DQS0; i <= _DDR1_DQS3; i++) - writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR1_A0; i <= _DDR1_A9; i++) - writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); - - for (i = _DDR1_D0; i <= _DDR1_D31; i++) - writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); - break; - } -} - -void config_mmdc(uint8_t module) -{ - unsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR; - - writel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR); - - writel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0); - writel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1); - writel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2); - writel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP); - writel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC); - writel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC); - writel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR); - writel(_MDCTL, mmdc_addr + MMDC_MDCTL); - - writel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0); - - while (readl(mmdc_addr + MMDC_MPMUR0) & MMDC_MPMUR0_FRC_MSR) { - } - - writel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR); - - /* Perform ZQ calibration */ - writel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL); - writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL); - while (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) { - } - - /* Enable MMDC with CS0 */ - writel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL); - - /* Complete the initialization sequence as defined by JEDEC */ - writel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR); - writel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR); - writel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR); - writel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR); - - /* Set the amount of DRAM */ - /* Set DQS settings based on board type */ - - switch (module) { - case MMDC0: - writel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP); - writel(MMDC_MPRDDLCTL_MODULE0_VALUE, - mmdc_addr + MMDC_MPRDDLCTL); - writel(MMDC_MPWRDLCTL_MODULE0_VALUE, - mmdc_addr + MMDC_MPWRDLCTL); - writel(MMDC_MPDGCTRL0_MODULE0_VALUE, - mmdc_addr + MMDC_MPDGCTRL0); - writel(MMDC_MPDGCTRL1_MODULE0_VALUE, - mmdc_addr + MMDC_MPDGCTRL1); - break; - case MMDC1: - writel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP); - writel(MMDC_MPRDDLCTL_MODULE1_VALUE, - mmdc_addr + MMDC_MPRDDLCTL); - writel(MMDC_MPWRDLCTL_MODULE1_VALUE, - mmdc_addr + MMDC_MPWRDLCTL); - writel(MMDC_MPDGCTRL0_MODULE1_VALUE, - mmdc_addr + MMDC_MPDGCTRL0); - writel(MMDC_MPDGCTRL1_MODULE1_VALUE, - mmdc_addr + MMDC_MPDGCTRL1); - break; - } - - writel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD); - writel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC); - writel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF); - writel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL); - writel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR); - -} diff --git a/board/freescale/s32v234evb/s32v234evb.c b/board/freescale/s32v234evb/s32v234evb.c deleted file mode 100644 index 304f5acf3b..0000000000 --- a/board/freescale/s32v234evb/s32v234evb.c +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013-2015, Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/siul.h> -#include <asm/arch/lpddr2.h> -#include <asm/arch/clock.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <miiphy.h> -#include <netdev.h> -#include <i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -void setup_iomux_ddr(void) -{ - lpddr2_config_iomux(DDR0); - lpddr2_config_iomux(DDR1); - -} - -void ddr_phy_init(void) -{ -} - -void ddr_ctrl_init(void) -{ - config_mmdc(0); - config_mmdc(1); -} - -int dram_init(void) -{ - setup_iomux_ddr(); - - ddr_ctrl_init(); - - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - - return 0; -} - -static void setup_iomux_uart(void) -{ - /* Muxing for linflex */ - /* Replace the magic values after bringup */ - - /* set TXD - MSCR[12] PA12 */ - writel(SIUL2_UART_TXD, SIUL2_MSCRn(SIUL2_UART0_TXD_PAD)); - - /* set RXD - MSCR[11] - PA11 */ - writel(SIUL2_UART_MSCR_RXD, SIUL2_MSCRn(SIUL2_UART0_MSCR_RXD_PAD)); - - /* set RXD - IMCR[200] - 200 */ - writel(SIUL2_UART_IMCR_RXD, SIUL2_IMCRn(SIUL2_UART0_IMCR_RXD_PAD)); -} - -static void setup_iomux_enet(void) -{ -} - -static void setup_iomux_i2c(void) -{ -} - -#ifdef CONFIG_SYS_USE_NAND -void setup_iomux_nfc(void) -{ -} -#endif - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {USDHC_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - /* eSDHC1 is always present */ - return 1; -} - -int board_mmc_init(struct bd_info * bis) -{ - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_USDHC_CLK); - - /* Set iomux PADS for USDHC */ - - /* PK6 pad: uSDHC clk */ - writel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150)); - writel(0x3, SIUL2_MSCRn(902)); - - /* PK7 pad: uSDHC CMD */ - writel(SIUL2_USDHC_PAD_CTRL_CMD, SIUL2_MSCRn(151)); - writel(0x3, SIUL2_MSCRn(901)); - - /* PK8 pad: uSDHC DAT0 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(152)); - writel(0x3, SIUL2_MSCRn(903)); - - /* PK9 pad: uSDHC DAT1 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(153)); - writel(0x3, SIUL2_MSCRn(904)); - - /* PK10 pad: uSDHC DAT2 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(154)); - writel(0x3, SIUL2_MSCRn(905)); - - /* PK11 pad: uSDHC DAT3 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(155)); - writel(0x3, SIUL2_MSCRn(906)); - - /* PK15 pad: uSDHC DAT4 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(159)); - writel(0x3, SIUL2_MSCRn(907)); - - /* PL0 pad: uSDHC DAT5 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(160)); - writel(0x3, SIUL2_MSCRn(908)); - - /* PL1 pad: uSDHC DAT6 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(161)); - writel(0x3, SIUL2_MSCRn(909)); - - /* PL2 pad: uSDHC DAT7 */ - writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(162)); - writel(0x3, SIUL2_MSCRn(910)); - - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} -#endif - -static void mscm_init(void) -{ - struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR; - int i; - - for (i = 0; i < MSCM_IRSPRC_NUM; i++) - writew(MSCM_IRSPRC_CPn_EN, &mscmir->irsprc[i]); -} - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_early_init_f(void) -{ - clock_init(); - mscm_init(); - - setup_iomux_uart(); - setup_iomux_enet(); - setup_iomux_i2c(); -#ifdef CONFIG_SYS_USE_NAND - setup_iomux_nfc(); -#endif - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int checkboard(void) -{ - puts("Board: s32v234evb\n"); - - return 0; -} diff --git a/board/freescale/s32v234evb/s32v234evb.cfg b/board/freescale/s32v234evb/s32v234evb.cfg deleted file mode 100644 index d7f7220063..0000000000 --- a/board/freescale/s32v234evb/s32v234evb.cfg +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015, Freescale Semiconductor, Inc. - */ - -/* - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ -#include <asm/mach-imx/imximage.cfg> - -/* image version */ -IMAGE_VERSION 2 -BOOT_FROM sd - - -/* - * Boot Device : one of qspi, sd: - * qspi: flash_offset: 0x1000 - * sd/mmc: flash_offset: 0x1000 - */ - - -#ifdef CONFIG_IMX_HAB -SECURE_BOOT -#endif diff --git a/board/freescale/t208xqds/Kconfig b/board/freescale/t208xqds/Kconfig index 5a435c2695..f65d8eed54 100644 --- a/board/freescale/t208xqds/Kconfig +++ b/board/freescale/t208xqds/Kconfig @@ -1,4 +1,4 @@ -if TARGET_T2080QDS || TARGET_T2081QDS +if TARGET_T2080QDS config SYS_BOARD default "t208xqds" diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile index 587903a623..55b1e7390a 100644 --- a/board/freescale/t208xqds/Makefile +++ b/board/freescale/t208xqds/Makefile @@ -8,7 +8,6 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o -obj-$(CONFIG_TARGET_T2081QDS) += t208xqds.o eth_t208xqds.o obj-$(CONFIG_PCI) += pci.o endif diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index aaa3490aaa..705387af3c 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -42,13 +42,6 @@ #define EMI1_SLOT4 4 #define EMI1_SLOT5 5 #define EMI2 7 -#elif defined(CONFIG_TARGET_T2081QDS) -#define EMI1_SLOT2 3 -#define EMI1_SLOT3 4 -#define EMI1_SLOT5 5 -#define EMI1_SLOT6 6 -#define EMI1_SLOT7 7 -#define EMI2 8 #endif #define PCCR1_SGMIIA_KX_MASK 0x00008000 @@ -72,24 +65,12 @@ static const char * const mdio_names[] = { "T2080QDS_MDIO_SLOT5", "T2080QDS_MDIO_SLOT2", "T2080QDS_MDIO_10GC", -#elif defined(CONFIG_TARGET_T2081QDS) - "T2081QDS_MDIO_RGMII1", - "T2081QDS_MDIO_RGMII2", - "T2081QDS_MDIO_SLOT1", - "T2081QDS_MDIO_SLOT2", - "T2081QDS_MDIO_SLOT3", - "T2081QDS_MDIO_SLOT5", - "T2081QDS_MDIO_SLOT6", - "T2081QDS_MDIO_SLOT7", - "T2081QDS_MDIO_10GC", #endif }; /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ #if defined(CONFIG_TARGET_T2080QDS) static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; -#elif defined(CONFIG_TARGET_T2081QDS) -static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1}; #endif static const char *t208xqds_mdio_name_for_muxval(u8 muxval) @@ -316,35 +297,6 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_status_okay_by_alias(fdt, "emi1_slot2"); } break; -#elif defined(CONFIG_TARGET_T2081QDS) - case FM1_DTSEC1: - case FM1_DTSEC2: - case FM1_DTSEC5: - case FM1_DTSEC6: - case FM1_DTSEC9: - case FM1_DTSEC10: - if (mdio_mux[port] == EMI1_SLOT2) { - sprintf(alias, "phy_sgmii_s2_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot2"); - } else if (mdio_mux[port] == EMI1_SLOT3) { - sprintf(alias, "phy_sgmii_s3_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot3"); - } else if (mdio_mux[port] == EMI1_SLOT5) { - sprintf(alias, "phy_sgmii_s5_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot5"); - } else if (mdio_mux[port] == EMI1_SLOT6) { - sprintf(alias, "phy_sgmii_s6_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot6"); - } else if (mdio_mux[port] == EMI1_SLOT7) { - sprintf(alias, "phy_sgmii_s7_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot7"); - } - break; #endif default: break; @@ -495,30 +447,6 @@ static void initialize_lane_to_slot(void) lane_to_slot[6] = 3; lane_to_slot[7] = 3; break; -#elif defined(CONFIG_TARGET_T2081QDS) - case 0x6b: - lane_to_slot[4] = 1; - lane_to_slot[5] = 3; - lane_to_slot[6] = 3; - lane_to_slot[7] = 3; - break; - case 0xca: - case 0xcb: - lane_to_slot[1] = 7; - lane_to_slot[2] = 6; - lane_to_slot[3] = 5; - lane_to_slot[5] = 3; - lane_to_slot[6] = 3; - lane_to_slot[7] = 3; - break; - case 0xf2: - lane_to_slot[1] = 7; - lane_to_slot[2] = 7; - lane_to_slot[3] = 7; - lane_to_slot[5] = 4; - lane_to_slot[6] = 3; - lane_to_slot[7] = 7; - break; #endif default: break; @@ -570,10 +498,6 @@ int board_eth_init(struct bd_info *bis) t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); #endif t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); -#if defined(CONFIG_TARGET_T2081QDS) - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); -#endif t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); /* Set the two on-board RGMII PHY address */ @@ -689,19 +613,6 @@ int board_eth_init(struct bd_info *bis) fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; -#elif defined(CONFIG_TARGET_T2081QDS) - case 0xca: - case 0xcb: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - /* SGMII in Slot5 */ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - /* SGMII in Slot6 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); - /* SGMII in Slot7 */ - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); - break; #endif case 0xf2: /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */ @@ -745,23 +656,6 @@ int board_eth_init(struct bd_info *bis) fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; -#if defined(CONFIG_TARGET_T2081QDS) - case 5: - mdio_mux[i] = EMI1_SLOT5; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 6: - mdio_mux[i] = EMI1_SLOT6; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 7: - mdio_mux[i] = EMI1_SLOT7; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; -#endif } break; case PHY_INTERFACE_MODE_RGMII: diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 36bb399293..fd3217f24d 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -209,76 +209,6 @@ int brd_mux_lane_to_slot(void) */ QIXIS_WRITE(brdcfg[12], 0x1a); break; -#elif defined(CONFIG_TARGET_T2081QDS) - case 0x50: - case 0x51: - /* SD1(A:D) => SLOT2 XAUI - * SD1(E) => SLOT1 PCIe4 x1 - * SD1(F:H) => SLOT3 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0x98); - QIXIS_WRITE(brdcfg[13], 0x70); - break; - case 0x6a: - case 0x6b: - /* SD1(A:D) => XFI SFP Module - * SD1(E) => SLOT1 PCIe4 x1 - * SD1(F:H) => SLOT3 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0x80); - QIXIS_WRITE(brdcfg[13], 0x70); - break; - case 0x6c: - case 0x6d: - /* SD1(A:B) => XFI SFP Module - * SD1(C:D) => SLOT2 SGMII - * SD1(E:H) => SLOT1 PCIe4 x4 - */ - QIXIS_WRITE(brdcfg[12], 0xe8); - QIXIS_WRITE(brdcfg[13], 0x0); - break; - case 0xaa: - case 0xab: - /* SD1(A:D) => SLOT2 PCIe3 x4 - * SD1(F:H) => SLOT1 SGMI4 x4 - */ - QIXIS_WRITE(brdcfg[12], 0xf8); - QIXIS_WRITE(brdcfg[13], 0x0); - break; - case 0xca: - case 0xcb: - /* SD1(A) => SLOT2 PCIe3 x1 - * SD1(B) => SLOT7 SGMII - * SD1(C) => SLOT6 SGMII - * SD1(D) => SLOT5 SGMII - * SD1(E) => SLOT1 PCIe4 x1 - * SD1(F:H) => SLOT3 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0x80); - QIXIS_WRITE(brdcfg[13], 0x70); - break; - case 0xde: - case 0xdf: - /* SD1(A:D) => SLOT2 PCIe3 x4 - * SD1(E) => SLOT1 PCIe4 x1 - * SD1(F) => SLOT4 PCIe1 x1 - * SD1(G) => SLOT3 PCIe2 x1 - * SD1(H) => SLOT7 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0x98); - QIXIS_WRITE(brdcfg[13], 0x25); - break; - case 0xf2: - /* SD1(A) => SLOT2 PCIe3 x1 - * SD1(B:D) => SLOT7 SGMII - * SD1(E) => SLOT1 PCIe4 x1 - * SD1(F) => SLOT4 PCIe1 x1 - * SD1(G) => SLOT3 PCIe2 x1 - * SD1(H) => SLOT7 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0x81); - QIXIS_WRITE(brdcfg[13], 0xa5); - break; #endif default: printf("WARNING: unsupported for SerDes1 Protocol %d\n", |