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-rw-r--r--board/amcc/bamboo/Kconfig12
-rw-r--r--board/amcc/bamboo/MAINTAINERS6
-rw-r--r--board/amcc/bamboo/Makefile9
-rw-r--r--board/amcc/bamboo/README77
-rw-r--r--board/amcc/bamboo/bamboo.c1896
-rw-r--r--board/amcc/bamboo/bamboo.h348
-rw-r--r--board/amcc/bamboo/config.mk16
-rw-r--r--board/amcc/bamboo/flash.c155
-rw-r--r--board/amcc/bamboo/init.S55
9 files changed, 0 insertions, 2574 deletions
diff --git a/board/amcc/bamboo/Kconfig b/board/amcc/bamboo/Kconfig
deleted file mode 100644
index c0bd40aee7..0000000000
--- a/board/amcc/bamboo/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_BAMBOO
-
-config SYS_BOARD
- default "bamboo"
-
-config SYS_VENDOR
- default "amcc"
-
-config SYS_CONFIG_NAME
- default "bamboo"
-
-endif
diff --git a/board/amcc/bamboo/MAINTAINERS b/board/amcc/bamboo/MAINTAINERS
deleted file mode 100644
index 4c8929ece7..0000000000
--- a/board/amcc/bamboo/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BAMBOO BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/amcc/bamboo/
-F: include/configs/bamboo.h
-F: configs/bamboo_defconfig
diff --git a/board/amcc/bamboo/Makefile b/board/amcc/bamboo/Makefile
deleted file mode 100644
index 4c0a1253f1..0000000000
--- a/board/amcc/bamboo/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = bamboo.o flash.o
-extra-y += init.o
diff --git a/board/amcc/bamboo/README b/board/amcc/bamboo/README
deleted file mode 100644
index e139c6d129..0000000000
--- a/board/amcc/bamboo/README
+++ /dev/null
@@ -1,77 +0,0 @@
-The 2 important dipswitches are configured as shown below:
-
-SW1 (for 33MHz SysClk)
-----------------------
-S1 S2 S3 S4 S5 S6 S7 S8
-OFF OFF OFF OFF OFF OFF OFF ON
-
-SW7 (for Op-Code Flash and Boot Option H)
------------------------------------------
-S1 S2 S3 S4 S5 S6 S7 S8
-OFF OFF OFF ON OFF OFF OFF OFF
-
-The EEPROM at location 0x52 is loaded with these 16 bytes:
-C47042A6 05D7A190 40082350 0d050000
-
-SDR0_SDSTP0[ENG]: 1 : PLL's VCO is the source for PLL forward divisors
-SDR0_SDSTP0[SRC]: 1 : Feedback originates from PLLOUTB
-SDR0_SDSTP0[SEL]: 0 : Feedback selection is PLL output
-SDR0_SDSTP0[TUNE]: 1000111000 : 10 <= M <= 22, 600MHz < VCO <= 900MHz
-SDR0_SDSTP0[FBDV]: 4 : PLL feedback divisor
-SDR0_SDSTP0[FBDVA]: 2 : PLL forward divisor A
-SDR0_SDSTP0[FBDVB]: 5 : PLL forward divisor B
-SDR0_SDSTP0[PRBDV0]: 1 : PLL primary divisor B
-SDR0_SDSTP0[OPBDV0]: 2 : OPB clock divisor
-SDR0_SDSTP0[LFBDV]: 1 : PLL local feedback divisor
-SDR0_SDSTP0[PERDV0]: 3 : Peripheral clock divisor 0
-SDR0_SDSTP0[MALDV0]: 2 : MAL clock divisor 0
-SDR0_SDSTP0[PCIDV0]: 2 : Sync PCI clock divisor 0
-SDR0_SDSTP0[PLLTIMER]: 7 : PLL locking timer
-SDR0_SDSTP0[RW]: 1 : EBC ROM width: 16-bit
-SDR0_SDSTP0[RL]: 0 : EBC ROM location: EBC
-SDR0_SDSTP0[PAE]: 0 : PCI internal arbiter: disabled
-SDR0_SDSTP0[PHCE]: 0 : PCI host configuration: disabled
-SDR0_SDSTP0[ZM]: 3 : ZMII mode: RMII mode 100
-SDR0_SDSTP0[CTE]: 0 : CPU trace: disabled
-SDR0_SDSTP0[Nto1]: 0 : CPU/PLB ratio N/P: not N to 1
-SDR0_SDSTP0[PAME]: 1 : PCI asynchronous mode: enabled
-SDR0_SDSTP0[MEM]: 1 : Multiplex: EMAC
-SDR0_SDSTP0[NE]: 0 : NDFC: disabled
-SDR0_SDSTP0[NBW]: 0 : NDFC boot width: 8-bit
-SDR0_SDSTP0[NBW]: 0 : NDFC boot page selection
-SDR0_SDSTP0[NBAC]: 0 : NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size)
-SDR0_SDSTP0[NARE]: 0 : NDFC auto read : disabled
-SDR0_SDSTP0[NRB]: 0 : NDFC Ready/Busy : Ready
-SDR0_SDSTP0[NDRSC]: 33333 : NDFC device reset counter
-SDR0_SDSTP0[NCG0]: 0 : NDFC/EBC chip select gating CS0 : EBC
-SDR0_SDSTP0[NCG1]: 0 : NDFC/EBC chip select gating CS1 : EBC
-SDR0_SDSTP0[NCG2]: 0 : NDFC/EBC chip select gating CS2 : EBC
-SDR0_SDSTP0[NCG3]: 0 : NDFC/EBC chip select gating CS3 : EBC
-SDR0_SDSTP0[NCRDC]: 3333 : NDFC device read count
-
-PPC440EP Clocking Configuration
-
-SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz
-OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz
-
-The above information is reported by Eugene O'Brien
-<Eugene.O'Brien@advantechamt.com>. Thanks a lot.
-
-2007-08-06, Stefan Roese <sr@denx.de>
----------------------------------------------------------------------
-
-The configuration for the AMCC 440EP eval board "Bamboo" was changed
-to only use 384 kbytes of FLASH for the U-Boot image. This way the
-redundant environment can be saved in the remaining 2 sectors of the
-same flash chip.
-
-Caution: With an upgrade from an earlier U-Boot version the current
-environment will be erased since the environment is now saved in
-different sectors. By using the following command the environment can
-be saved after upgrading the U-Boot image and *before* resetting the
-board:
-
-setenv recover_env 'prot off FFF80000 FFF9FFFF;era FFF80000 FFF9FFFF;' \
- 'cp.b FFF60000 FFF80000 20000'
-
-2006-07-27, Stefan Roese <sr@denx.de>
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
deleted file mode 100644
index 9f642071cc..0000000000
--- a/board/amcc/bamboo/bamboo.c
+++ /dev/null
@@ -1,1896 +0,0 @@
-/*
- * (C) Copyright 2005-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-gpio.h>
-#include <spd_sdram.h>
-#include <asm/ppc440.h>
-#include "bamboo.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void ext_bus_cntlr_init(void);
-void configure_ppc440ep_pins(void);
-int is_nand_selected(void);
-
-/*************************************************************************
- *
- * Bamboo has one bank onboard sdram (plus DIMM)
- *
- * Fixed memory is composed of :
- * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
- * 13 row add bits, 10 column add bits (but 12 row used only).
- * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
- * 12 row add bits, 10 column add bits.
- * Prepare a subset (only the used ones) of SPD data
- *
- * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
- * the corresponding bank is divided by 2 due to number of Row addresses
- * 12 in the ECC module
- *
- * Assumes: 64 MB, ECC, non-registered
- * PLB @ 133 MHz
- *
- ************************************************************************/
-const unsigned char cfg_simulate_spd_eeprom[128] = {
- 0x80, /* number of SPD bytes used: 128 */
- 0x08, /* total number bytes in SPD device = 256 */
- 0x07, /* DDR ram */
-#ifdef CONFIG_DDR_ECC
- 0x0C, /* num Row Addr: 12 */
-#else
- 0x0D, /* num Row Addr: 13 */
-#endif
- 0x09, /* numColAddr: 9 */
- 0x01, /* numBanks: 1 */
- 0x20, /* Module data width: 32 bits */
- 0x00, /* Module data width continued: +0 */
- 0x04, /* 2.5 Volt */
- 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
- 0x00, /* SDRAM Access from clock */
-#ifdef CONFIG_DDR_ECC
- 0x02, /* ECC ON : 02 OFF : 00 */
-#else
- 0x00, /* ECC ON : 02 OFF : 00 */
-#endif
- 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */
- 0,
- 0,
- 0x01, /* wcsbc = 1 */
- 0,
- 0,
- 0x0C, /* casBit (2,2.5) */
- 0,
- 0,
- 0x00, /* not registered: 0 registered : 0x02*/
- 0,
- 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */
- 0,
- 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */
- 0,
- 0x50, /* tRpNs = 20 ns */
- 0,
- 0x50, /* tRcdNs = 20 ns */
- 45, /* tRasNs */
-#ifdef CONFIG_DDR_ECC
- 0x08, /* bankSizeID: 32MB */
-#else
- 0x10, /* bankSizeID: 64MB */
-#endif
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
-};
-
-#if 0
-{ /* GPIO Alternate1 Alternate2 Alternate3 */
- {
- /* GPIO Core 0 */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
- { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
- { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
- { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
- },
- {
- /* GPIO Core 1 */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
- { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
- }
-};
-#endif
-
-/*----------------------------------------------------------------------------+
- | EBC Devices Characteristics
- | Peripheral Bank Access Parameters - EBC0_BnAP
- | Peripheral Bank Configuration Register - EBC0_BnCR
- +----------------------------------------------------------------------------*/
-/* Small Flash */
-#define EBC0_BNAP_SMALL_FLASH \
- EBC0_BNAP_BME_DISABLED | \
- EBC0_BNAP_TWT_ENCODE(6) | \
- EBC0_BNAP_CSN_ENCODE(0) | \
- EBC0_BNAP_OEN_ENCODE(1) | \
- EBC0_BNAP_WBN_ENCODE(1) | \
- EBC0_BNAP_WBF_ENCODE(3) | \
- EBC0_BNAP_TH_ENCODE(1) | \
- EBC0_BNAP_RE_ENABLED | \
- EBC0_BNAP_SOR_DELAYED | \
- EBC0_BNAP_BEM_WRITEONLY | \
- EBC0_BNAP_PEN_DISABLED
-
-#define EBC0_BNCR_SMALL_FLASH_CS0 \
- EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
- EBC0_BNCR_BS_1MB | \
- EBC0_BNCR_BU_RW | \
- EBC0_BNCR_BW_8BIT
-
-#define EBC0_BNCR_SMALL_FLASH_CS4 \
- EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
- EBC0_BNCR_BS_1MB | \
- EBC0_BNCR_BU_RW | \
- EBC0_BNCR_BW_8BIT
-
-/* Large Flash or SRAM */
-#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
- EBC0_BNAP_BME_DISABLED | \
- EBC0_BNAP_TWT_ENCODE(8) | \
- EBC0_BNAP_CSN_ENCODE(0) | \
- EBC0_BNAP_OEN_ENCODE(1) | \
- EBC0_BNAP_WBN_ENCODE(1) | \
- EBC0_BNAP_WBF_ENCODE(1) | \
- EBC0_BNAP_TH_ENCODE(2) | \
- EBC0_BNAP_SOR_DELAYED | \
- EBC0_BNAP_BEM_RW | \
- EBC0_BNAP_PEN_DISABLED
-
-#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
- EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
- EBC0_BNCR_BS_8MB | \
- EBC0_BNCR_BU_RW | \
- EBC0_BNCR_BW_16BIT
-
-
-#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
- EBC0_BNCR_BAS_ENCODE(0x87800000) | \
- EBC0_BNCR_BS_8MB | \
- EBC0_BNCR_BU_RW | \
- EBC0_BNCR_BW_16BIT
-
-/* NVRAM - FPGA */
-#define EBC0_BNAP_NVRAM_FPGA \
- EBC0_BNAP_BME_DISABLED | \
- EBC0_BNAP_TWT_ENCODE(9) | \
- EBC0_BNAP_CSN_ENCODE(0) | \
- EBC0_BNAP_OEN_ENCODE(1) | \
- EBC0_BNAP_WBN_ENCODE(1) | \
- EBC0_BNAP_WBF_ENCODE(0) | \
- EBC0_BNAP_TH_ENCODE(2) | \
- EBC0_BNAP_RE_ENABLED | \
- EBC0_BNAP_SOR_DELAYED | \
- EBC0_BNAP_BEM_WRITEONLY | \
- EBC0_BNAP_PEN_DISABLED
-
-#define EBC0_BNCR_NVRAM_FPGA_CS5 \
- EBC0_BNCR_BAS_ENCODE(0x80000000) | \
- EBC0_BNCR_BS_1MB | \
- EBC0_BNCR_BU_RW | \
- EBC0_BNCR_BW_8BIT
-
-/* Nand Flash */
-#define EBC0_BNAP_NAND_FLASH \
- EBC0_BNAP_BME_DISABLED | \
- EBC0_BNAP_TWT_ENCODE(3) | \
- EBC0_BNAP_CSN_ENCODE(0) | \
- EBC0_BNAP_OEN_ENCODE(0) | \
- EBC0_BNAP_WBN_ENCODE(0) | \
- EBC0_BNAP_WBF_ENCODE(0) | \
- EBC0_BNAP_TH_ENCODE(1) | \
- EBC0_BNAP_RE_ENABLED | \
- EBC0_BNAP_SOR_NOT_DELAYED | \
- EBC0_BNAP_BEM_RW | \
- EBC0_BNAP_PEN_DISABLED
-
-
-#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
-
-/* NAND0 */
-#define EBC0_BNCR_NAND_FLASH_CS1 \
- EBC0_BNCR_BAS_ENCODE(0x90000000) | \
- EBC0_BNCR_BS_1MB | \
- EBC0_BNCR_BU_RW | \
- EBC0_BNCR_BW_32BIT
-/* NAND1 - Bank2 */
-#define EBC0_BNCR_NAND_FLASH_CS2 \
- EBC0_BNCR_BAS_ENCODE(0x94000000) | \
- EBC0_BNCR_BS_1MB | \
- EBC0_BNCR_BU_RW | \
- EBC0_BNCR_BW_32BIT
-
-/* NAND1 - Bank3 */
-#define EBC0_BNCR_NAND_FLASH_CS3 \
- EBC0_BNCR_BAS_ENCODE(0x94000000) | \
- EBC0_BNCR_BS_1MB | \
- EBC0_BNCR_BU_RW | \
- EBC0_BNCR_BW_32BIT
-
-int board_early_init_f(void)
-{
- ext_bus_cntlr_init();
-
- /*--------------------------------------------------------------------
- * Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
- mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
- mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- /*--------------------------------------------------------------------
- * Setup the GPIO pins
- *-------------------------------------------------------------------*/
- out32(GPIO0_OSRL, 0x00000400);
- out32(GPIO0_OSRH, 0x00000000);
- out32(GPIO0_TSRL, 0x00000400);
- out32(GPIO0_TSRH, 0x00000000);
- out32(GPIO0_ISR1L, 0x00000000);
- out32(GPIO0_ISR1H, 0x00000000);
- out32(GPIO0_ISR2L, 0x00000000);
- out32(GPIO0_ISR2H, 0x00000000);
- out32(GPIO0_ISR3L, 0x00000000);
- out32(GPIO0_ISR3H, 0x00000000);
-
- out32(GPIO1_OSRL, 0x0C380000);
- out32(GPIO1_OSRH, 0x00000000);
- out32(GPIO1_TSRL, 0x0C380000);
- out32(GPIO1_TSRH, 0x00000000);
- out32(GPIO1_ISR1L, 0x0FC30000);
- out32(GPIO1_ISR1H, 0x00000000);
- out32(GPIO1_ISR2L, 0x0C010000);
- out32(GPIO1_ISR2H, 0x00000000);
- out32(GPIO1_ISR3L, 0x01400000);
- out32(GPIO1_ISR3H, 0x00000000);
-
- configure_ppc440ep_pins();
-
- return 0;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return (0);
-}
-
-
-int dram_init(void)
-{
- gd->ram_size = spd_sdram();
-
- return 0;
-}
-
-/*----------------------------------------------------------------------------+
- | is_powerpc440ep_pass1.
- +----------------------------------------------------------------------------*/
-int is_powerpc440ep_pass1(void)
-{
- unsigned long pvr;
-
- pvr = get_pvr();
-
- if (pvr == PVR_POWERPC_440EP_PASS1)
- return true;
- else if (pvr == PVR_POWERPC_440EP_PASS2)
- return false;
- else {
- printf("brdutil error 3\n");
- for (;;)
- ;
- }
-
- return false;
-}
-
-/*----------------------------------------------------------------------------+
- | is_nand_selected.
- +----------------------------------------------------------------------------*/
-int is_nand_selected(void)
-{
-#ifdef CONFIG_BAMBOO_NAND
- return true;
-#else
- return false;
-#endif
-}
-
-/*----------------------------------------------------------------------------+
- | config_on_ebc_cs4_is_small_flash => from EPLD
- +----------------------------------------------------------------------------*/
-unsigned char config_on_ebc_cs4_is_small_flash(void)
-{
- /* Not implemented yet => returns constant value */
- return true;
-}
-
-/*----------------------------------------------------------------------------+
- | Ext_bus_cntlr_init.
- | Initialize the external bus controller
- +----------------------------------------------------------------------------*/
-void ext_bus_cntlr_init(void)
-{
- unsigned long sdr0_pstrp0, sdr0_sdstp1;
- unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
- int computed_boot_device = BOOT_DEVICE_UNKNOWN;
- unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
- unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
- unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
- unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
- unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
-
-
- /*-------------------------------------------------------------------------+
- |
- | PART 1 : Initialize EBC Bank 5
- | ==============================
- | Bank5 is always associated to the NVRAM/EPLD.
- | It has to be initialized prior to other banks settings computation since
- | some board registers values may be needed
- |
- +-------------------------------------------------------------------------*/
- /* NVRAM - FPGA */
- mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA);
- mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5);
-
- /*-------------------------------------------------------------------------+
- |
- | PART 2 : Determine which boot device was selected
- | =========================================
- |
- | Read Pin Strap Register in PPC440EP
- | In case of boot from IIC, read Serial Device Strap Register1
- |
- | Result can either be :
- | - Boot from EBC 8bits => SMALL FLASH
- | - Boot from EBC 16bits => Large Flash or SRAM
- | - Boot from NAND Flash
- | - Boot from PCI
- |
- +-------------------------------------------------------------------------*/
- /* Read Pin Strap Register in PPC440EP */
- mfsdr(SDR0_PINSTP, sdr0_pstrp0);
- bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
-
- /*-------------------------------------------------------------------------+
- | PPC440EP Pass1
- +-------------------------------------------------------------------------*/
- if (is_powerpc440ep_pass1() == true) {
- switch(bootstrap_settings) {
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
- /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
- /* Boot from Small Flash */
- computed_boot_device = BOOT_FROM_SMALL_FLASH;
- break;
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
- /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
- /* Boot from PCI */
- computed_boot_device = BOOT_FROM_PCI;
- break;
-
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
- /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
- /* Boot from Nand Flash */
- computed_boot_device = BOOT_FROM_NAND_FLASH0;
- break;
-
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
- /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
- /* Boot from Small Flash */
- computed_boot_device = BOOT_FROM_SMALL_FLASH;
- break;
-
- case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
- case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
- /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
- /* Read Serial Device Strap Register1 in PPC440EP */
- mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
- boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
- ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
-
- switch(boot_selection) {
- case SDR0_SDSTP1_BOOT_SEL_EBC:
- switch(ebc_boot_size) {
- case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
- computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
- break;
- case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
- computed_boot_device = BOOT_FROM_SMALL_FLASH;
- break;
- }
- break;
-
- case SDR0_SDSTP1_BOOT_SEL_PCI:
- computed_boot_device = BOOT_FROM_PCI;
- break;
-
- case SDR0_SDSTP1_BOOT_SEL_NDFC:
- computed_boot_device = BOOT_FROM_NAND_FLASH0;
- break;
- }
- break;
- }
- }
-
- /*-------------------------------------------------------------------------+
- | PPC440EP Pass2
- +-------------------------------------------------------------------------*/
- else {
- switch(bootstrap_settings) {
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
- /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
- /* Boot from Small Flash */
- computed_boot_device = BOOT_FROM_SMALL_FLASH;
- break;
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
- /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
- /* Boot from PCI */
- computed_boot_device = BOOT_FROM_PCI;
- break;
-
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
- /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
- /* Boot from Nand Flash */
- computed_boot_device = BOOT_FROM_NAND_FLASH0;
- break;
-
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
- /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
- /* Boot from Large Flash or SRAM */
- computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
- break;
-
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
- /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
- /* Boot from Large Flash or SRAM */
- computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
- break;
-
- case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
- /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
- /* Boot from PCI */
- computed_boot_device = BOOT_FROM_PCI;
- break;
-
- case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
- case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
- /* Default Strap Settings 5-7 */
- /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
- /* Read Serial Device Strap Register1 in PPC440EP */
- mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
- boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
- ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
-
- switch(boot_selection) {
- case SDR0_SDSTP1_BOOT_SEL_EBC:
- switch(ebc_boot_size) {
- case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
- computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
- break;
- case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
- computed_boot_device = BOOT_FROM_SMALL_FLASH;
- break;
- }
- break;
-
- case SDR0_SDSTP1_BOOT_SEL_PCI:
- computed_boot_device = BOOT_FROM_PCI;
- break;
-
- case SDR0_SDSTP1_BOOT_SEL_NDFC:
- computed_boot_device = BOOT_FROM_NAND_FLASH0;
- break;
- }
- break;
- }
- }
-
- /*-------------------------------------------------------------------------+
- |
- | PART 3 : Compute EBC settings depending on selected boot device
- | ====== ======================================================
- |
- | Resulting EBC init will be among following configurations :
- |
- | - Boot from EBC 8bits => boot from SMALL FLASH selected
- | EBC-CS0 = Small Flash
- | EBC-CS1,2,3 = NAND Flash or
- | Exp.Slot depending on Soft Config
- | EBC-CS4 = SRAM/Large Flash or
- | Large Flash/SRAM depending on jumpers
- | EBC-CS5 = NVRAM / EPLD
- |
- | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
- | EBC-CS0 = SRAM/Large Flash or
- | Large Flash/SRAM depending on jumpers
- | EBC-CS1,2,3 = NAND Flash or
- | Exp.Slot depending on Software Configuration
- | EBC-CS4 = Small Flash
- | EBC-CS5 = NVRAM / EPLD
- |
- | - Boot from NAND Flash
- | EBC-CS0 = NAND Flash0
- | EBC-CS1,2,3 = NAND Flash1
- | EBC-CS4 = SRAM/Large Flash or
- | Large Flash/SRAM depending on jumpers
- | EBC-CS5 = NVRAM / EPLD
- |
- | - Boot from PCI
- | EBC-CS0 = ...
- | EBC-CS1,2,3 = NAND Flash or
- | Exp.Slot depending on Software Configuration
- | EBC-CS4 = SRAM/Large Flash or
- | Large Flash/SRAM or
- | Small Flash depending on jumpers
- | EBC-CS5 = NVRAM / EPLD
- |
- +-------------------------------------------------------------------------*/
-
- switch(computed_boot_device) {
- /*------------------------------------------------------------------------- */
- case BOOT_FROM_SMALL_FLASH:
- /*------------------------------------------------------------------------- */
- ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
- ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
- if ((is_nand_selected()) == true) {
- /* NAND Flash */
- ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
- ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
- ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
- ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
- ebc0_cs3_bnap_value = 0;
- ebc0_cs3_bncr_value = 0;
- } else {
- /* Expansion Slot */
- ebc0_cs1_bnap_value = 0;
- ebc0_cs1_bncr_value = 0;
- ebc0_cs2_bnap_value = 0;
- ebc0_cs2_bncr_value = 0;
- ebc0_cs3_bnap_value = 0;
- ebc0_cs3_bncr_value = 0;
- }
- ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
- ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
-
- break;
-
- /*------------------------------------------------------------------------- */
- case BOOT_FROM_LARGE_FLASH_OR_SRAM:
- /*------------------------------------------------------------------------- */
- ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
- ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
- if ((is_nand_selected()) == true) {
- /* NAND Flash */
- ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
- ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
- ebc0_cs2_bnap_value = 0;
- ebc0_cs2_bncr_value = 0;
- ebc0_cs3_bnap_value = 0;
- ebc0_cs3_bncr_value = 0;
- } else {
- /* Expansion Slot */
- ebc0_cs1_bnap_value = 0;
- ebc0_cs1_bncr_value = 0;
- ebc0_cs2_bnap_value = 0;
- ebc0_cs2_bncr_value = 0;
- ebc0_cs3_bnap_value = 0;
- ebc0_cs3_bncr_value = 0;
- }
- ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
- ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
-
- break;
-
- /*------------------------------------------------------------------------- */
- case BOOT_FROM_NAND_FLASH0:
- /*------------------------------------------------------------------------- */
- ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
- ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
-
- ebc0_cs1_bnap_value = 0;
- ebc0_cs1_bncr_value = 0;
- ebc0_cs2_bnap_value = 0;
- ebc0_cs2_bncr_value = 0;
- ebc0_cs3_bnap_value = 0;
- ebc0_cs3_bncr_value = 0;
-
- /* Large Flash or SRAM */
- ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
- ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
-
- break;
-
- /*------------------------------------------------------------------------- */
- case BOOT_FROM_PCI:
- /*------------------------------------------------------------------------- */
- ebc0_cs0_bnap_value = 0;
- ebc0_cs0_bncr_value = 0;
-
- if ((is_nand_selected()) == true) {
- /* NAND Flash */
- ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
- ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
- ebc0_cs2_bnap_value = 0;
- ebc0_cs2_bncr_value = 0;
- ebc0_cs3_bnap_value = 0;
- ebc0_cs3_bncr_value = 0;
- } else {
- /* Expansion Slot */
- ebc0_cs1_bnap_value = 0;
- ebc0_cs1_bncr_value = 0;
- ebc0_cs2_bnap_value = 0;
- ebc0_cs2_bncr_value = 0;
- ebc0_cs3_bnap_value = 0;
- ebc0_cs3_bncr_value = 0;
- }
-
- if ((config_on_ebc_cs4_is_small_flash()) == true) {
- /* Small Flash */
- ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
- ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
- } else {
- /* Large Flash or SRAM */
- ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
- ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
- }
-
- break;
-
- /*------------------------------------------------------------------------- */
- case BOOT_DEVICE_UNKNOWN:
- /*------------------------------------------------------------------------- */
- /* Error */
- break;
-
- }
-
-
- /*-------------------------------------------------------------------------+
- | Initialize EBC CONFIG
- +-------------------------------------------------------------------------*/
- mtdcr(EBC0_CFGADDR, EBC0_CFG);
- mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN |
- EBC0_CFG_PTD_ENABLED |
- EBC0_CFG_RTC_2048PERCLK |
- EBC0_CFG_EMPL_LOW |
- EBC0_CFG_EMPH_LOW |
- EBC0_CFG_CSTC_DRIVEN |
- EBC0_CFG_BPF_ONEDW |
- EBC0_CFG_EMS_8BIT |
- EBC0_CFG_PME_DISABLED |
- EBC0_CFG_PMT_ENCODE(0) );
-
- /*-------------------------------------------------------------------------+
- | Initialize EBC Bank 0-4
- +-------------------------------------------------------------------------*/
- /* EBC Bank0 */
- mtebc(PB0AP, ebc0_cs0_bnap_value);
- mtebc(PB0CR, ebc0_cs0_bncr_value);
- /* EBC Bank1 */
- mtebc(PB1AP, ebc0_cs1_bnap_value);
- mtebc(PB1CR, ebc0_cs1_bncr_value);
- /* EBC Bank2 */
- mtebc(PB2AP, ebc0_cs2_bnap_value);
- mtebc(PB2CR, ebc0_cs2_bncr_value);
- /* EBC Bank3 */
- mtebc(PB3AP, ebc0_cs3_bnap_value);
- mtebc(PB3CR, ebc0_cs3_bncr_value);
- /* EBC Bank4 */
- mtebc(PB4AP, ebc0_cs4_bnap_value);
- mtebc(PB4CR, ebc0_cs4_bncr_value);
-
- return;
-}
-
-
-/*----------------------------------------------------------------------------+
- | get_uart_configuration.
- +----------------------------------------------------------------------------*/
-uart_config_nb_t get_uart_configuration(void)
-{
- return (L4);
-}
-
-/*----------------------------------------------------------------------------+
- | set_phy_configuration_through_fpga => to EPLD
- +----------------------------------------------------------------------------*/
-void set_phy_configuration_through_fpga(zmii_config_t config)
-{
-
- unsigned long fpga_selection_reg;
-
- fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
-
- switch(config)
- {
- case ZMII_CONFIGURATION_IS_MII:
- fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
- break;
- case ZMII_CONFIGURATION_IS_RMII:
- fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
- break;
- case ZMII_CONFIGURATION_IS_SMII:
- fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
- break;
- case ZMII_CONFIGURATION_UNKNOWN:
- default:
- break;
- }
- out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
-
-}
-
-/*----------------------------------------------------------------------------+
- | scp_selection_in_fpga.
- +----------------------------------------------------------------------------*/
-void scp_selection_in_fpga(void)
-{
- unsigned long fpga_selection_2_reg;
-
- fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
- fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
- out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | iic1_selection_in_fpga.
- +----------------------------------------------------------------------------*/
-void iic1_selection_in_fpga(void)
-{
- unsigned long fpga_selection_2_reg;
-
- fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
- fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
- out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | dma_a_b_selection_in_fpga.
- +----------------------------------------------------------------------------*/
-void dma_a_b_selection_in_fpga(void)
-{
- unsigned long fpga_selection_2_reg;
-
- fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
- out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | dma_a_b_unselect_in_fpga.
- +----------------------------------------------------------------------------*/
-void dma_a_b_unselect_in_fpga(void)
-{
- unsigned long fpga_selection_2_reg;
-
- fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
- out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | dma_c_d_selection_in_fpga.
- +----------------------------------------------------------------------------*/
-void dma_c_d_selection_in_fpga(void)
-{
- unsigned long fpga_selection_2_reg;
-
- fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
- out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | dma_c_d_unselect_in_fpga.
- +----------------------------------------------------------------------------*/
-void dma_c_d_unselect_in_fpga(void)
-{
- unsigned long fpga_selection_2_reg;
-
- fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
- out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | usb2_device_selection_in_fpga.
- +----------------------------------------------------------------------------*/
-void usb2_device_selection_in_fpga(void)
-{
- unsigned long fpga_selection_1_reg;
-
- fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
- out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | usb2_device_reset_through_fpga.
- +----------------------------------------------------------------------------*/
-void usb2_device_reset_through_fpga(void)
-{
- /* Perform soft Reset pulse */
- unsigned long fpga_reset_reg;
- int i;
-
- fpga_reset_reg = in8(FPGA_RESET_REG);
- out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
- for (i=0; i<500; i++)
- udelay(1000);
- out8(FPGA_RESET_REG,fpga_reset_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | usb2_host_selection_in_fpga.
- +----------------------------------------------------------------------------*/
-void usb2_host_selection_in_fpga(void)
-{
- unsigned long fpga_selection_1_reg;
-
- fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
- out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | ndfc_selection_in_fpga.
- +----------------------------------------------------------------------------*/
-void ndfc_selection_in_fpga(void)
-{
- unsigned long fpga_selection_1_reg;
-
- fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
- fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
- fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
- out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
-}
-
-/*----------------------------------------------------------------------------+
- | uart_selection_in_fpga.
- +----------------------------------------------------------------------------*/
-void uart_selection_in_fpga(uart_config_nb_t uart_config)
-{
- /* FPGA register */
- unsigned char fpga_selection_3_reg;
-
- /* Read FPGA Reagister */
- fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
-
- switch (uart_config)
- {
- case L1:
- /* ----------------------------------------------------------------------- */
- /* L1 configuration: UART0 = 8 pins */
- /* ----------------------------------------------------------------------- */
- /* Configure FPGA */
- fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
- fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
- out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
-
- break;
-
- case L2:
- /* ----------------------------------------------------------------------- */
- /* L2 configuration: UART0 = 4 pins */
- /* UART1 = 4 pins */
- /* ----------------------------------------------------------------------- */
- /* Configure FPGA */
- fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
- fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
- out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
-
- break;
-
- case L3:
- /* ----------------------------------------------------------------------- */
- /* L3 configuration: UART0 = 4 pins */
- /* UART1 = 2 pins */
- /* UART2 = 2 pins */
- /* ----------------------------------------------------------------------- */
- /* Configure FPGA */
- fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
- fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
- out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
- break;
-
- case L4:
- /* Configure FPGA */
- fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
- fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
- out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
-
- break;
-
- default:
- /* Unsupported UART configuration number */
- for (;;)
- ;
- break;
-
- }
-}
-
-
-/*----------------------------------------------------------------------------+
- | init_default_gpio
- +----------------------------------------------------------------------------*/
-void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- int i;
-
- /* Init GPIO0 */
- for(i=0; i<GPIO_MAX; i++)
- {
- gpio_tab[GPIO0][i].add = GPIO0_BASE;
- gpio_tab[GPIO0][i].in_out = GPIO_DIS;
- gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
- }
-
- /* Init GPIO1 */
- for(i=0; i<GPIO_MAX; i++)
- {
- gpio_tab[GPIO1][i].add = GPIO1_BASE;
- gpio_tab[GPIO1][i].in_out = GPIO_DIS;
- gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
- }
-
- /* EBC_CS_N(5) - GPIO0_10 */
- gpio_tab[GPIO0][10].in_out = GPIO_OUT;
- gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
-
- /* EBC_CS_N(4) - GPIO0_9 */
- gpio_tab[GPIO0][9].in_out = GPIO_OUT;
- gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
-}
-
-/*----------------------------------------------------------------------------+
- | update_uart_ios
- +------------------------------------------------------------------------------
- |
- | Set UART Configuration in PowerPC440EP
- |
- | +---------------------------------------------------------------------+
- | | Configuartion | Connector | Nb of pins | Pins | Associated |
- | | Number | Port Name | available | naming | CORE |
- | +-----------------+---------------+------------+--------+-------------+
- | | L1 | Port_A | 8 | UART | UART core 0 |
- | +-----------------+---------------+------------+--------+-------------+
- | | L2 | Port_A | 4 | UART1 | UART core 0 |
- | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
- | +-----------------+---------------+------------+--------+-------------+
- | | L3 | Port_A | 4 | UART1 | UART core 0 |
- | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
- | | | Port_C | 2 | UART3 | UART core 2 |
- | +-----------------+---------------+------------+--------+-------------+
- | | | Port_A | 2 | UART1 | UART core 0 |
- | | L4 | Port_B | 2 | UART2 | UART core 1 |
- | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
- | | | Port_D | 2 | UART4 | UART core 3 |
- | +-----------------+---------------+------------+--------+-------------+
- |
- | Involved GPIOs
- |
- | +------------------------------------------------------------------------------+
- | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
- | +---------+------------------+-----+-----------------+-----+-------------+-----+
- | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
- | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
- | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
- | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
- | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
- | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
- | +------------------------------------------------------------------------------+
- |
- |
- +----------------------------------------------------------------------------*/
-
-void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- switch (uart_config)
- {
- case L1:
- /* ----------------------------------------------------------------------- */
- /* L1 configuration: UART0 = 8 pins */
- /* ----------------------------------------------------------------------- */
- /* Update GPIO Configuration Table */
- gpio_tab[GPIO1][2].in_out = GPIO_IN;
- gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][3].in_out = GPIO_IN;
- gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][4].in_out = GPIO_IN;
- gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][5].in_out = GPIO_OUT;
- gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][6].in_out = GPIO_OUT;
- gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][7].in_out = GPIO_IN;
- gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
-
- break;
-
- case L2:
- /* ----------------------------------------------------------------------- */
- /* L2 configuration: UART0 = 4 pins */
- /* UART1 = 4 pins */
- /* ----------------------------------------------------------------------- */
- /* Update GPIO Configuration Table */
- gpio_tab[GPIO1][2].in_out = GPIO_IN;
- gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][3].in_out = GPIO_OUT;
- gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][4].in_out = GPIO_IN;
- gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][5].in_out = GPIO_OUT;
- gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][6].in_out = GPIO_OUT;
- gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][7].in_out = GPIO_IN;
- gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
-
- break;
-
- case L3:
- /* ----------------------------------------------------------------------- */
- /* L3 configuration: UART0 = 4 pins */
- /* UART1 = 2 pins */
- /* UART2 = 2 pins */
- /* ----------------------------------------------------------------------- */
- /* Update GPIO Configuration Table */
- gpio_tab[GPIO1][2].in_out = GPIO_OUT;
- gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
-
- gpio_tab[GPIO1][3].in_out = GPIO_IN;
- gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
-
- gpio_tab[GPIO1][4].in_out = GPIO_IN;
- gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][5].in_out = GPIO_OUT;
- gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][6].in_out = GPIO_OUT;
- gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][7].in_out = GPIO_IN;
- gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
-
- break;
-
- case L4:
- /* ----------------------------------------------------------------------- */
- /* L4 configuration: UART0 = 2 pins */
- /* UART1 = 2 pins */
- /* UART2 = 2 pins */
- /* UART3 = 2 pins */
- /* ----------------------------------------------------------------------- */
- /* Update GPIO Configuration Table */
- gpio_tab[GPIO1][2].in_out = GPIO_OUT;
- gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
-
- gpio_tab[GPIO1][3].in_out = GPIO_IN;
- gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
-
- gpio_tab[GPIO1][4].in_out = GPIO_IN;
- gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
-
- gpio_tab[GPIO1][5].in_out = GPIO_OUT;
- gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
-
- gpio_tab[GPIO1][6].in_out = GPIO_OUT;
- gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][7].in_out = GPIO_IN;
- gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
-
- break;
-
- default:
- /* Unsupported UART configuration number */
- printf("ERROR - Unsupported UART configuration number.\n\n");
- for (;;)
- ;
- break;
-
- }
-
- /* Set input Selection Register on Alt_Receive for UART Input Core */
- out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
- out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
- out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
-}
-
-/*----------------------------------------------------------------------------+
- | update_ndfc_ios(void).
- +----------------------------------------------------------------------------*/
-void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- /* Update GPIO Configuration Table */
- gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
- gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
- gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
-
-#if 0
- gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
- gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
-#endif
-}
-
-/*----------------------------------------------------------------------------+
- | update_zii_ios(void).
- +----------------------------------------------------------------------------*/
-void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- /* Update GPIO Configuration Table */
- gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
- gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
- gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
- gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
- gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
- gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
- gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
- gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
- gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
- gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
- gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
- gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
- gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
- gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
- gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
-
-}
-
-/*----------------------------------------------------------------------------+
- | update_uic_0_3_irq_ios().
- +----------------------------------------------------------------------------*/
-void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
- gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
- gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
- gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
- gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
-}
-
-/*----------------------------------------------------------------------------+
- | update_uic_4_9_irq_ios().
- +----------------------------------------------------------------------------*/
-void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
- gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
- gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
- gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
- gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
- gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
-}
-
-/*----------------------------------------------------------------------------+
- | update_dma_a_b_ios().
- +----------------------------------------------------------------------------*/
-void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
- gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
- gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
- gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
- gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
- gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
-}
-
-/*----------------------------------------------------------------------------+
- | update_dma_c_d_ios().
- +----------------------------------------------------------------------------*/
-void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
- gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
- gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
- gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
- gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
- gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
- gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
-
-}
-
-/*----------------------------------------------------------------------------+
- | update_ebc_master_ios().
- +----------------------------------------------------------------------------*/
-void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
- gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
- gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
- gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
- gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
-}
-
-/*----------------------------------------------------------------------------+
- | update_usb2_device_ios().
- +----------------------------------------------------------------------------*/
-void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
- gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
- gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
- gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
- gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
- gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
- gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
-
- gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
- gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
-
- gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
- gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
-
-}
-
-/*----------------------------------------------------------------------------+
- | update_pci_patch_ios().
- +----------------------------------------------------------------------------*/
-void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
- gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
-}
-
-/*----------------------------------------------------------------------------+
- | set_chip_gpio_configuration(unsigned char gpio_core,
- | gpio_param_s (*gpio_tab)[GPIO_MAX])
- | Put the core impacted by clock modification and sharing in reset.
- | Config the select registers to resolve the sharing depending of the config.
- | Configure the GPIO registers.
- |
- +----------------------------------------------------------------------------*/
-void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
- unsigned char i=0, j=0, reg_offset = 0;
- unsigned long gpio_reg, gpio_core_add;
-
- /* GPIO config of the GPIOs 0 to 31 */
- for (i=0; i<GPIO_MAX; i++, j++)
- {
- if (i == GPIO_MAX/2)
- {
- reg_offset = 4;
- j = i-16;
- }
-
- gpio_core_add = gpio_tab[gpio_core][i].add;
-
- if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
- (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
- {
- switch (gpio_tab[gpio_core][i].alt_nb)
- {
- case GPIO_SEL:
- break;
-
- case GPIO_ALT1:
- gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
- out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
- break;
-
- case GPIO_ALT2:
- gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
- out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
- break;
-
- case GPIO_ALT3:
- gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
- out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
- break;
- }
- }
- if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
- (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
- {
-
- switch (gpio_tab[gpio_core][i].alt_nb)
- {
- case GPIO_SEL:
- break;
- case GPIO_ALT1:
- gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
- out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
- gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
- out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
- break;
- case GPIO_ALT2:
- gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
- out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
- gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
- out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
- break;
- case GPIO_ALT3:
- gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
- out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
- gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
- gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
- out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
- break;
- }
- }
- }
-}
-
-/*----------------------------------------------------------------------------+
- | force_bup_core_selection.
- +----------------------------------------------------------------------------*/
-void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
-{
- /* Pointer invalid */
- if (core_select_P == NULL)
- {
- printf("Configuration invalid pointer 1\n");
- for (;;)
- ;
- }
-
- /* L4 Selection */
- *(core_select_P+UART_CORE0) = CORE_SELECTED;
- *(core_select_P+UART_CORE1) = CORE_SELECTED;
- *(core_select_P+UART_CORE2) = CORE_SELECTED;
- *(core_select_P+UART_CORE3) = CORE_SELECTED;
-
- /* RMII Selection */
- *(core_select_P+RMII_SEL) = CORE_SELECTED;
-
- /* External Interrupt 0-9 selection */
- *(core_select_P+UIC_0_3) = CORE_SELECTED;
- *(core_select_P+UIC_4_9) = CORE_SELECTED;
-
- *(core_select_P+SCP_CORE) = CORE_SELECTED;
- *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
- *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
- *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
-
- if (is_nand_selected()) {
- *(core_select_P+NAND_FLASH) = CORE_SELECTED;
- }
-
- *config_val_P = CONFIG_IS_VALID;
-
-}
-
-/*----------------------------------------------------------------------------+
- | configure_ppc440ep_pins.
- +----------------------------------------------------------------------------*/
-void configure_ppc440ep_pins(void)
-{
- uart_config_nb_t uart_configuration;
- config_validity_t config_val = CONFIG_IS_INVALID;
-
- /* Create Core Selection Table */
- core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
- {
- CORE_NOT_SELECTED, /* IIC_CORE, */
- CORE_NOT_SELECTED, /* SPC_CORE, */
- CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
- CORE_NOT_SELECTED, /* UIC_4_9, */
- CORE_NOT_SELECTED, /* USB2_HOST, */
- CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
- CORE_NOT_SELECTED, /* USB2_DEVICE, */
- CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
- CORE_NOT_SELECTED, /* USB1_DEVICE, */
- CORE_NOT_SELECTED, /* EBC_MASTER, */
- CORE_NOT_SELECTED, /* NAND_FLASH, */
- CORE_NOT_SELECTED, /* UART_CORE0, */
- CORE_NOT_SELECTED, /* UART_CORE1, */
- CORE_NOT_SELECTED, /* UART_CORE2, */
- CORE_NOT_SELECTED, /* UART_CORE3, */
- CORE_NOT_SELECTED, /* MII_SEL, */
- CORE_NOT_SELECTED, /* RMII_SEL, */
- CORE_NOT_SELECTED, /* SMII_SEL, */
- CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
- CORE_NOT_SELECTED, /* UIC_0_3 */
- CORE_NOT_SELECTED, /* USB1_HOST */
- CORE_NOT_SELECTED /* PCI_PATCH */
- };
-
- gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
-
- /* Table Default Initialisation + FPGA Access */
- init_default_gpio(gpio_tab);
- set_chip_gpio_configuration(GPIO0, gpio_tab);
- set_chip_gpio_configuration(GPIO1, gpio_tab);
-
- /* Update Table */
- force_bup_core_selection(ppc440ep_core_selection, &config_val);
-#if 0 /* test-only */
- /* If we are running PIBS 1, force known configuration */
- update_core_selection_table(ppc440ep_core_selection, &config_val);
-#endif
-
- /*----------------------------------------------------------------------------+
- | SDR + ios table update + fpga initialization
- +----------------------------------------------------------------------------*/
- unsigned long sdr0_pfc1 = 0;
- unsigned long sdr0_usb0 = 0;
- unsigned long sdr0_mfr = 0;
-
- /* PCI Always selected */
-
- /* I2C Selection */
- if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
- {
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
- iic1_selection_in_fpga();
- }
-
- /* SCP Selection */
- if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
- {
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
- scp_selection_in_fpga();
- }
-
- /* UIC 0:3 Selection */
- if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
- {
- update_uic_0_3_irq_ios(gpio_tab);
- dma_a_b_unselect_in_fpga();
- }
-
- /* UIC 4:9 Selection */
- if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
- {
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
- update_uic_4_9_irq_ios(gpio_tab);
- }
-
- /* DMA AB Selection */
- if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
- {
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
- update_dma_a_b_ios(gpio_tab);
- dma_a_b_selection_in_fpga();
- }
-
- /* DMA CD Selection */
- if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
- {
- update_dma_c_d_ios(gpio_tab);
- dma_c_d_selection_in_fpga();
- }
-
- /* EBC Master Selection */
- if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
- {
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
- update_ebc_master_ios(gpio_tab);
- }
-
- /* PCI Patch Enable */
- if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
- {
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
- update_pci_patch_ios(gpio_tab);
- }
-
- /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
- if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
- {
- /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
- printf("Invalid configuration => USB2 Host selected\n");
- for (;;)
- ;
- /*usb2_host_selection_in_fpga(); */
- }
-
- /* USB2.0 Device Selection */
- if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
- {
- update_usb2_device_ios(gpio_tab);
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
-
- mfsdr(SDR0_USB0, sdr0_usb0);
- sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
- sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
- mtsdr(SDR0_USB0, sdr0_usb0);
-
- usb2_device_selection_in_fpga();
- }
-
- /* USB1.1 Device Selection */
- if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
- {
- mfsdr(SDR0_USB0, sdr0_usb0);
- sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
- sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
- mtsdr(SDR0_USB0, sdr0_usb0);
- }
-
- /* USB1.1 Host Selection */
- if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
- {
- mfsdr(SDR0_USB0, sdr0_usb0);
- sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
- sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
- mtsdr(SDR0_USB0, sdr0_usb0);
- }
-
- /* NAND Flash Selection */
- if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
- {
- update_ndfc_ios(gpio_tab);
- mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
- SDR0_CUST0_NDFC_ENABLE |
- SDR0_CUST0_NDFC_BW_8_BIT |
- SDR0_CUST0_NDFC_ARE_MASK |
- SDR0_CUST0_CHIPSELGAT_EN1 |
- SDR0_CUST0_CHIPSELGAT_EN2);
- ndfc_selection_in_fpga();
- }
- else
- {
- /* Set Mux on EMAC */
- mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL);
- }
-
- /* MII Selection */
- if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
- {
- update_zii_ios(gpio_tab);
- mfsdr(SDR0_MFR, sdr0_mfr);
- sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
- mtsdr(SDR0_MFR, sdr0_mfr);
-
- set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
- }
-
- /* RMII Selection */
- if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
- {
- update_zii_ios(gpio_tab);
- mfsdr(SDR0_MFR, sdr0_mfr);
- sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
- mtsdr(SDR0_MFR, sdr0_mfr);
-
- set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
- }
-
- /* SMII Selection */
- if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
- {
- update_zii_ios(gpio_tab);
- mfsdr(SDR0_MFR, sdr0_mfr);
- sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
- mtsdr(SDR0_MFR, sdr0_mfr);
-
- set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
- }
-
- /* UART Selection */
- uart_configuration = get_uart_configuration();
- switch (uart_configuration)
- {
- case L1: /* L1 Selection */
- /* UART0 8 pins Only */
- /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
- break;
- case L2: /* L2 Selection */
- /* UART0 and UART1 4 pins */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
- break;
- case L3: /* L3 Selection */
- /* UART0 4 pins, UART1 and UART2 2 pins */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
- break;
- case L4: /* L4 Selection */
- /* UART0, UART1, UART2 and UART3 2 pins */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
- break;
- }
- update_uart_ios(uart_configuration, gpio_tab);
-
- /* UART Selection in all cases */
- uart_selection_in_fpga(uart_configuration);
-
- /* Packet Reject Function Available */
- if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
- {
- /* Set UPR Bit in SDR0_PFC1 Register */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
- }
-
- /* Packet Reject Function Enable */
- if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
- {
- mfsdr(SDR0_MFR, sdr0_mfr);
- sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;
- mtsdr(SDR0_MFR, sdr0_mfr);
- }
-
- /* Perform effective access to hardware */
- mtsdr(SDR0_PFC1, sdr0_pfc1);
- set_chip_gpio_configuration(GPIO0, gpio_tab);
- set_chip_gpio_configuration(GPIO1, gpio_tab);
-
- /* USB2.0 Device Reset must be done after GPIO setting */
- if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
- usb2_device_reset_through_fpga();
-
-}
diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h
deleted file mode 100644
index 49f200aa0b..0000000000
--- a/board/amcc/bamboo/bamboo.h
+++ /dev/null
@@ -1,348 +0,0 @@
-/*
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*----------------------------------------------------------------------------+
- | FPGA registers and bit definitions
- +----------------------------------------------------------------------------*/
-/*
- * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0.
- * TLB initialization makes it correspond to logical address 0x80001FF0.
- * => Done init_chip.s in bootlib
- */
-#define FPGA_BASE_ADDR 0x80002000
-
-/*----------------------------------------------------------------------------+
- | Board Jumpers Setting Register
- | Board Settings provided by jumpers
- +----------------------------------------------------------------------------*/
-#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3)
-/* Boot from small flash */
-#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80
-/* Operational Flash versus SRAM position in Memory Map */
-#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40
-#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40
-#define FPGA_SET_REG_SRAM_ABOVE 0x00
-/* Boot From NAND Flash */
-#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40
-#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00
-/* On Board PCI Arbiter Select */
-#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10
-#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00
-
-/*----------------------------------------------------------------------------+
- | Functions Selection Register 1
- +----------------------------------------------------------------------------*/
-#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4)
-#define FPGA_SEL_1_REG_PHY_MASK 0xE0
-#define FPGA_SEL_1_REG_MII 0x80
-#define FPGA_SEL_1_REG_RMII 0x40
-#define FPGA_SEL_1_REG_SMII 0x20
-#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */
-#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */
-#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */
-#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */
-#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */
-#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */
-
-/*----------------------------------------------------------------------------+
- | Functions Selection Register 2
- +----------------------------------------------------------------------------*/
-#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5)
-#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */
-#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */
-#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */
-#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */
-#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */
-#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */
-#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */
- /* 1 = TC - output from 440EP */
-#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */
- /* 1 = TC (output from 440EP) */
-#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */
-#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */
-#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */
-
-/*----------------------------------------------------------------------------+
- | Functions Selection Register 3
- +----------------------------------------------------------------------------*/
-#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6)
-#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */
-#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70
-#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */
-#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */
-#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */
-#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */
-#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */
-#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */
-
-/*----------------------------------------------------------------------------+
- | Soft Reset Register
- +----------------------------------------------------------------------------*/
-#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7)
-#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */
-#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */
-#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */
-#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */
-#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */
-#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */
-
-
-/*----------------------------------------------------------------------------+
-| SDR Configuration registers
-+----------------------------------------------------------------------------*/
-#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */
-#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */
-#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */
-#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
-
-#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */
-#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
-#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */
-#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */
-
-/* Serial Device Enabled - Addr = 0xA8 */
-#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
-/* Serial Device Enabled - Addr = 0xA4 */
-#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
-
-/* Pin Straps Reg */
-#define SDR0_PSTRP0 0x0040
-#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
-
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
-
-/*----------------------------------------------------------------------------+
-| EBC Configuration Register - EBC0_CFG
-+----------------------------------------------------------------------------*/
-/* External Bus Three-State Control */
-#define EBC0_CFG_EBTC_DRIVEN 0x80000000
-/* Device-Paced Time-out Disable */
-#define EBC0_CFG_PTD_ENABLED 0x00000000
-/* Ready Timeout Count */
-#define EBC0_CFG_RTC_MASK 0x38000000
-#define EBC0_CFG_RTC_16PERCLK 0x00000000
-#define EBC0_CFG_RTC_32PERCLK 0x08000000
-#define EBC0_CFG_RTC_64PERCLK 0x10000000
-#define EBC0_CFG_RTC_128PERCLK 0x18000000
-#define EBC0_CFG_RTC_256PERCLK 0x20000000
-#define EBC0_CFG_RTC_512PERCLK 0x28000000
-#define EBC0_CFG_RTC_1024PERCLK 0x30000000
-#define EBC0_CFG_RTC_2048PERCLK 0x38000000
-/* External Master Priority Low */
-#define EBC0_CFG_EMPL_LOW 0x00000000
-#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
-#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
-#define EBC0_CFG_EMPL_HIGH 0x06000000
-/* External Master Priority High */
-#define EBC0_CFG_EMPH_LOW 0x00000000
-#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
-#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
-#define EBC0_CFG_EMPH_HIGH 0x01800000
-/* Chip Select Three-State Control */
-#define EBC0_CFG_CSTC_DRIVEN 0x00400000
-/* Burst Prefetch */
-#define EBC0_CFG_BPF_ONEDW 0x00000000
-#define EBC0_CFG_BPF_TWODW 0x00100000
-#define EBC0_CFG_BPF_FOURDW 0x00200000
-/* External Master Size */
-#define EBC0_CFG_EMS_8BIT 0x00000000
-/* Power Management Enable */
-#define EBC0_CFG_PME_DISABLED 0x00000000
-#define EBC0_CFG_PME_ENABLED 0x00020000
-/* Power Management Timer */
-#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
-
-/*----------------------------------------------------------------------------+
-| Peripheral Bank Configuration Register - EBC0_BnCR
-+----------------------------------------------------------------------------*/
-/* BAS - Base Address Select */
-#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
-/* BS - Bank Size */
-#define EBC0_BNCR_BS_MASK 0x000E0000
-#define EBC0_BNCR_BS_1MB 0x00000000
-#define EBC0_BNCR_BS_2MB 0x00020000
-#define EBC0_BNCR_BS_4MB 0x00040000
-#define EBC0_BNCR_BS_8MB 0x00060000
-#define EBC0_BNCR_BS_16MB 0x00080000
-#define EBC0_BNCR_BS_32MB 0x000A0000
-#define EBC0_BNCR_BS_64MB 0x000C0000
-#define EBC0_BNCR_BS_128MB 0x000E0000
-/* BU - Bank Usage */
-#define EBC0_BNCR_BU_MASK 0x00018000
-#define EBC0_BNCR_BU_RO 0x00008000
-#define EBC0_BNCR_BU_WO 0x00010000
-#define EBC0_BNCR_BU_RW 0x00018000
-/* BW - Bus Width */
-#define EBC0_BNCR_BW_MASK 0x00006000
-#define EBC0_BNCR_BW_8BIT 0x00000000
-#define EBC0_BNCR_BW_16BIT 0x00002000
-#define EBC0_BNCR_BW_32BIT 0x00004000
-
-/*----------------------------------------------------------------------------+
-| Peripheral Bank Access Parameters - EBC0_BnAP
-+----------------------------------------------------------------------------*/
-/* Burst Mode Enable */
-#define EBC0_BNAP_BME_ENABLED 0x80000000
-#define EBC0_BNAP_BME_DISABLED 0x00000000
-/* Transfert Wait */
-#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */
-/* Chip Select On Timing */
-#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */
-/* Output Enable On Timing */
-#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */
-/* Write Back Enable On Timing */
-#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */
-/* Write Back Enable Off Timing */
-#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */
-/* Transfert Hold */
-#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */
-/* PerReady Enable */
-#define EBC0_BNAP_RE_ENABLED 0x00000100
-#define EBC0_BNAP_RE_DISABLED 0x00000000
-/* Sample On Ready */
-#define EBC0_BNAP_SOR_DELAYED 0x00000000
-#define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080
-/* Byte Enable Mode */
-#define EBC0_BNAP_BEM_WRITEONLY 0x00000000
-#define EBC0_BNAP_BEM_RW 0x00000040
-/* Parity Enable */
-#define EBC0_BNAP_PEN_DISABLED 0x00000000
-#define EBC0_BNAP_PEN_ENABLED 0x00000020
-
-/*----------------------------------------------------------------------------+
-| Define Boot devices
-+----------------------------------------------------------------------------*/
-/* */
-#define BOOT_FROM_SMALL_FLASH 0x00
-#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
-#define BOOT_FROM_NAND_FLASH0 0x02
-#define BOOT_FROM_PCI 0x03
-#define BOOT_DEVICE_UNKNOWN 0x04
-
-
-#define PVR_POWERPC_440EP_PASS1 0x42221850
-#define PVR_POWERPC_440EP_PASS2 0x422218D3
-
-#define GPIO0 0
-#define GPIO1 1
-
-/*#define MAX_SELECTION_NB CORE_NB */
-#define MAX_CORE_SELECT_NB 22
-
-/*----------------------------------------------------------------------------+
- | PPC440EP GPIOs addresses.
- +----------------------------------------------------------------------------*/
-#define GPIO0_REAL 0xEF600B00
-
-#define GPIO1_REAL 0xEF600C00
-
-/* Offsets */
-#define GPIOx_OR 0x00 /* GPIO Output Register */
-#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
-#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
-#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
-#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
-#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
-#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
-#define GPIOx_IR 0x1C /* GPIO Input Register */
-#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
-#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
-#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
-#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
-#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
-#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
-#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
-#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
-#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
-
-/* GPIO0 */
-#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L)
-#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H)
-#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L)
-#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H)
-#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L)
-#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L)
-
-/* GPIO1 */
-#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L)
-#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H)
-#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L)
-#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H)
-#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L)
-#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L)
-
-#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
-#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
-#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
-#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
-#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
-
-
-/*----------------------------------------------------------------------------+
- | XX XX
- |
- | XXXXXX XXX XX XXX XXX
- | XX XX X XX XX XX
- | XX XX X XX XX XX
- | XX XX XX XX XX
- | XXXXXX XXX XXX XXXX XXXX
- +----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------+
- | Defines
- +----------------------------------------------------------------------------*/
-typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
- ZMII_CONFIGURATION_IS_MII,
- ZMII_CONFIGURATION_IS_RMII,
- ZMII_CONFIGURATION_IS_SMII
-} zmii_config_t;
-
-/*----------------------------------------------------------------------------+
- | Declare Configuration values
- +----------------------------------------------------------------------------*/
-typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
-typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
-typedef enum config_list { IIC_CORE,
- SCP_CORE,
- DMA_CHANNEL_AB,
- UIC_4_9,
- USB2_HOST,
- DMA_CHANNEL_CD,
- USB2_DEVICE,
- PACKET_REJ_FUNC_AVAIL,
- USB1_DEVICE,
- EBC_MASTER,
- NAND_FLASH,
- UART_CORE0,
- UART_CORE1,
- UART_CORE2,
- UART_CORE3,
- MII_SEL,
- RMII_SEL,
- SMII_SEL,
- PACKET_REJ_FUNC_EN,
- UIC_0_3,
- USB1_HOST,
- PCI_PATCH,
- CORE_NB
-} core_list_t;
-
-typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5,
- B3_V6, B3_V7, B3_V8, B3_V9, B3_V10,
- B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
- B3_V16, B3_VALUE_UNKNOWN
-} block3_value_t;
-
-typedef enum config_validity { CONFIG_IS_VALID,
- CONFIG_IS_INVALID
-} config_validity_t;
diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk
deleted file mode 100644
index 9cb071e45b..0000000000
--- a/board/amcc/bamboo/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2002-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c
deleted file mode 100644
index 6dbe09f91d..0000000000
--- a/board/amcc/bamboo/flash.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * (C) Copyright 2004-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
- * Add support for Am29F016D and dynamic switch setting.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/ppc440.h>
-#include "bamboo.h"
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif /* DEBUG */
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*
- * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
- */
-static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
- {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
- {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */
- {0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash */
- {0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
- {0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
- {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */
- {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */
- {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */
- {0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
-};
-
-/*
- * include common flash code (for amcc boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
- unsigned long total_b = 0;
- unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
- unsigned short index = 0;
- int i;
- unsigned long val;
- unsigned long ebc_boot_size;
- unsigned long boot_selection;
-
- mfsdr(SDR0_PINSTP, val);
- index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29;
-
- if ((index == 5) || (index == 7)) {
- /*
- * Boot Settings in IIC EEprom address 0xA8 or 0xA4
- * Read Serial Device Strap Register1 in PPC440EP
- */
- mfsdr(SDR0_SDSTP1, val);
- boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
- ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
-
- switch(boot_selection) {
- case SDR0_SDSTP1_BOOT_SEL_EBC:
- switch(ebc_boot_size) {
- case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
- index = 3;
- break;
- case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
- index = 0;
- break;
- }
- break;
-
- case SDR0_SDSTP1_BOOT_SEL_PCI:
- index = 1;
- break;
-
- case SDR0_SDSTP1_BOOT_SEL_NDFC:
- index = 2;
- break;
- }
- } else if (index == 0) {
- if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) {
- index = 8; /* sram below op code flash -> new index 8 */
- }
- }
-
- DEBUGF("\n");
- DEBUGF("FLASH: Index: %d\n", index);
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
-
- /* check whether the address is 0 */
- if (flash_addr_table[index][i] == 0)
- continue;
-
- DEBUGF("Detection bank %d...\n", i);
- /* call flash_get_size() to initialize sector address */
- size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
- &flash_info[i]);
- flash_info[i].size = size_b[i];
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
- i, size_b[i], size_b[i] << 20);
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
- }
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
- &flash_info[i]);
-#if defined(CONFIG_ENV_IS_IN_FLASH)
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[i]);
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR_REDUND)
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[i]);
-#endif
-#endif
-
- total_b += flash_info[i].size;
- }
-
- return total_b;
-}
diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S
deleted file mode 100644
index 5c7c839079..0000000000
--- a/board/amcc/bamboo/init.S
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
-
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
-
- /* PCI base & peripherals */
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG)
-
- tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I)
- tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I)
-
- /* PCI */
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG)
-
- /* USB 2.0 Device */
- tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
-
- tlbtab_end