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-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/rk3036-sdk.dts2
-rw-r--r--arch/arm/dts/rk3288-miniarm.dts61
-rw-r--r--arch/arm/dts/rk3288-miniarm.dtsi533
-rw-r--r--arch/arm/dts/rk3288-rock2-square.dts2
-rw-r--r--arch/arm/dts/rk3288-veyron.dtsi2
-rw-r--r--arch/arm/dts/rk3399-evb.dts4
-rw-r--r--arch/arm/dts/rk3399.dtsi4
-rw-r--r--arch/arm/include/asm/arch-rockchip/cru_rk3399.h93
-rw-r--r--arch/arm/mach-rockchip/rk3288/Kconfig14
-rw-r--r--arch/arm/mach-rockchip/rk3399/Makefile2
-rw-r--r--arch/arm/mach-rockchip/rk3399/reset_rk3399.c45
-rw-r--r--arch/arm/mach-rockchip/rk3399/syscon_rk3399.c20
13 files changed, 775 insertions, 8 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 639c06db0a..d93fabc76d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-rock2-square.dtb \
rk3288-evb.dtb \
rk3288-fennec.dtb \
+ rk3288-miniarm.dtb \
rk3288-popmetal.dtb \
rk3036-sdk.dtb \
rk3399-evb.dtb
diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/rk3036-sdk.dts
index a83badb59c..1c9ddf9856 100644
--- a/arch/arm/dts/rk3036-sdk.dts
+++ b/arch/arm/dts/rk3036-sdk.dts
@@ -41,6 +41,4 @@
&usb_otg {
status = "okay";
-
- dr_mode = "host";
};
diff --git a/arch/arm/dts/rk3288-miniarm.dts b/arch/arm/dts/rk3288-miniarm.dts
new file mode 100644
index 0000000000..c7410821d3
--- /dev/null
+++ b/arch/arm/dts/rk3288-miniarm.dts
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+#include "rk3288-miniarm.dtsi"
+
+/ {
+ model = "Miniarm-RK3288";
+ compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&dmc {
+ rockchip,num-channels = <2>;
+ rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+ 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+ 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+ 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+ 0x5 0x0>;
+ rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+ 0xa60 0x40 0x10 0x0>;
+ /* Add a dummy value to cause of-platdata think this is bytes */
+ rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
+ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
+};
+
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+ reg-shift = <2>;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio3 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio8 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-miniarm.dtsi b/arch/arm/dts/rk3288-miniarm.dtsi
new file mode 100644
index 0000000000..b88987557a
--- /dev/null
+++ b/arch/arm/dts/rk3288-miniarm.dtsi
@@ -0,0 +1,533 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "rk3288.dtsi"
+
+/ {
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x80000000>;
+ };
+
+ ext_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwrbtn>;
+
+ button@0 {
+ gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+ linux,input-type = <1>;
+ gpio-key,wakeup = <1>;
+ debounce-interval = <100>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ pwr-led {
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ act-led {
+ gpios=<&gpio2 3 GPIO_ACTIVE_LOW>;
+ linux,default-trigger="mmc0";
+ };
+ };
+
+ vcc_sys: vsys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /*
+ * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from
+ * vcc_io directly. Those boards won't be able to power cycle SD cards
+ * but it shouldn't hurt to toggle this pin there anyway.
+ */
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_pwr>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc_io>;
+ };
+};
+
+&cpu0 {
+ cpu0-supply = <&vdd_cpu>;
+};
+
+&emmc {
+ broken-cd;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ disable-wp;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ disable-wp; /* wp not hooked up */
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ status = "okay";
+ supports-sd;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vccio_sd>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&gmac {
+ phy-supply = <&vcc33_lan>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio4 7 0>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ status = "ok";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c5>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int &global_pwroff>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_18>;
+ vcc9-supply = <&vcc_io>;
+ vcc10-supply = <&vcc_io>;
+ vcc11-supply = <&vcc_sys>;
+ vcc12-supply = <&vcc_io>;
+ vddio-supply = <&vcc18_ldo1>;
+
+ regulators {
+ vdd_cpu: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-name = "vdd_arm";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd_gpu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_io";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc18_ldo1: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_ldo1";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc33_mipi: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33_mipi";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd_10";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc18_codec: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_codec";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd10_lcd: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd10_lcd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_18: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_18";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_lcd: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_lcd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc33_sd: SWITCH_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc33_sd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc33_lan: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc33_lan";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+ headset: nau8825@1a {
+ compatible = "nuvoton,nau8825";
+ #sound-dai-cells = <0>;
+ reg = <0x1a>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ nuvoton,jkdet-enable = <1>;
+ nuvoton,jkdet-pull-enable = <1>;
+ nuvoton,jkdet-pull-up = <0>;
+ nuvoton,jkdet-polarity = <1>;
+ nuvoton,vref-impedance = <2>;
+ nuvoton,micbias-voltage = <6>;
+ nuvoton,sar-threshold-num = <4>;
+ nuvoton,sar-threshold = <0xa 0x14 0x26 0x73>;
+ nuvoton,sar-hysteresis = <0>;
+ nuvoton,sar-voltage = <6>;
+ nuvoton,sar-compare-time = <0>;
+ nuvoton,sar-sampling-time = <0>;
+ nuvoton,short-key-debounce = <3>;
+ nuvoton,jack-insert-debounce = <7>;
+ nuvoton,jack-eject-debounce = <7>;
+ clock-names = "mclk";
+ clocks = <&cru SCLK_I2S0_OUT>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc18_ldo1>;
+ status ="okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host1 {
+ status = "okay";
+};
+
+&usb_otg {
+ status= "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
+
+&pinctrl {
+ pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ backlight {
+ bl_en: bl-en {
+ rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ buttons {
+ pwrbtn: pwrbtn {
+ rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ eth_phy {
+ eth_phy_pwr: eth-phy-pwr {
+ rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdmmc {
+ /*
+ * Default drive strength isn't enough to achieve even
+ * high-speed mode on EVB board so bump up to 8ma.
+ */
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+ <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+ <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+ <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+ };
+
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+ };
+
+ sdmmc_pwr: sdmmc-pwr {
+ rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pwr_3g: pwr-3g {
+ rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3288-rock2-square.dts b/arch/arm/dts/rk3288-rock2-square.dts
index 34073c9405..2c30355f06 100644
--- a/arch/arm/dts/rk3288-rock2-square.dts
+++ b/arch/arm/dts/rk3288-rock2-square.dts
@@ -192,7 +192,7 @@
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
- rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
+ rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index 421d21290c..d9d51879f0 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -253,7 +253,7 @@
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
- rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
+ rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index bbcfcd0da9..e92a492545 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -61,6 +61,10 @@
status = "okay";
};
+&sdmmc {
+ status = "okay";
+};
+
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index fb5af54799..a4c6e27b39 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -172,9 +172,9 @@
reg = <0x0 0xfe320000 0x0 0x4000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
status = "disabled";
};
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
new file mode 100644
index 0000000000..c919f47745
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CRU_RK3399_H_
+#define __ASM_ARCH_CRU_RK3399_H_
+
+#include <common.h>
+
+struct rk3399_pmucru {
+ u32 ppll_con[6];
+ u32 reserved[0x1a];
+ u32 pmucru_clksel[6];
+ u32 pmucru_clkfrac_con[2];
+ u32 reserved2[0x18];
+ u32 pmucru_clkgate_con[3];
+ u32 reserved3;
+ u32 pmucru_softrst_con[2];
+ u32 reserved4[2];
+ u32 pmucru_rstnhold_con[2];
+ u32 reserved5[2];
+ u32 pmucru_gatedis_con[2];
+};
+check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
+
+struct rk3399_cru {
+ u32 apll_l_con[6];
+ u32 reserved[2];
+ u32 apll_b_con[6];
+ u32 reserved1[2];
+ u32 dpll_con[6];
+ u32 reserved2[2];
+ u32 cpll_con[6];
+ u32 reserved3[2];
+ u32 gpll_con[6];
+ u32 reserved4[2];
+ u32 npll_con[6];
+ u32 reserved5[2];
+ u32 vpll_con[6];
+ u32 reserved6[0x0a];
+ u32 clksel_con[108];
+ u32 reserved7[0x14];
+ u32 clkgate_con[35];
+ u32 reserved8[0x1d];
+ u32 softrst_con[21];
+ u32 reserved9[0x2b];
+ u32 glb_srst_fst_value;
+ u32 glb_srst_snd_value;
+ u32 glb_cnt_th;
+ u32 misc_con;
+ u32 glb_rst_con;
+ u32 glb_rst_st;
+ u32 reserved10[0x1a];
+ u32 sdmmc_con[2];
+ u32 sdio0_con[2];
+ u32 sdio1_con[2];
+};
+check_member(rk3399_cru, sdio1_con[1], 0x594);
+#define MHz 1000000
+#define KHz 1000
+#define OSC_HZ (24*MHz)
+#define APLL_HZ (600*MHz)
+#define GPLL_HZ (594*MHz)
+#define CPLL_HZ (384*MHz)
+#define PPLL_HZ (594*MHz)
+
+#define PMU_PCLK_HZ (99*MHz)
+
+#define ACLKM_CORE_HZ (300*MHz)
+#define ATCLK_CORE_HZ (300*MHz)
+#define PCLK_DBG_HZ (100*MHz)
+
+#define PERIHP_ACLK_HZ (148500*KHz)
+#define PERIHP_HCLK_HZ (148500*KHz)
+#define PERIHP_PCLK_HZ (37125*KHz)
+
+#define PERILP0_ACLK_HZ (99000*KHz)
+#define PERILP0_HCLK_HZ (99000*KHz)
+#define PERILP0_PCLK_HZ (49500*KHz)
+
+#define PERILP1_HCLK_HZ (99000*KHz)
+#define PERILP1_PCLK_HZ (49500*KHz)
+
+#define PWM_CLOCK_HZ PMU_PCLK_HZ
+
+enum apll_l_frequencies {
+ APLL_L_1600_MHZ,
+ APLL_L_600_MHZ,
+};
+
+#endif /* __ASM_ARCH_CRU_RK3399_H_ */
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index 8ec1920d19..b4113e085b 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -33,6 +33,14 @@ config TARGET_POPMETAL_RK3288
2GB DDR3. Expansion connectors provide access to I2C, SPI, UART,
GPIOs and display interface.
+config TARGET_MINIARM_RK3288
+ bool "miniarm-RK3288"
+ help
+ Miniarm is a RK3288-based development board with 2 USB ports, HDMI,
+ micro-SD card, audio, Gigabit Ethernet. It also includes on-board
+ 8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to
+ I2C, SPI, UART, GPIOs.
+
config TARGET_CHROMEBOOK_JERRY
bool "Google/Rockchip Veyron-Jerry Chromebook"
help
@@ -64,16 +72,18 @@ config SYS_SOC
config SYS_MALLOC_F_LEN
default 0x0800
-source "board/google/chromebook_jerry/Kconfig"
+source "board/chipspark/popmetal_rk3288/Kconfig"
source "board/firefly/firefly-rk3288/Kconfig"
+source "board/google/chromebook_jerry/Kconfig"
+
source "board/radxa/rock2/Kconfig"
source "board/rockchip/evb_rk3288/Kconfig"
source "board/rockchip/fennec_rk3288/Kconfig"
-source "board/chipspark/popmetal_rk3288/Kconfig"
+source "board/rockchip/miniarm_rk3288/Kconfig"
endif
diff --git a/arch/arm/mach-rockchip/rk3399/Makefile b/arch/arm/mach-rockchip/rk3399/Makefile
index 3f219ac6f8..3ca20284ef 100644
--- a/arch/arm/mach-rockchip/rk3399/Makefile
+++ b/arch/arm/mach-rockchip/rk3399/Makefile
@@ -5,3 +5,5 @@
#
obj-y += rk3399.o
+obj-y += reset_rk3399.o
+obj-y += syscon_rk3399.o
diff --git a/arch/arm/mach-rockchip/rk3399/reset_rk3399.c b/arch/arm/mach-rockchip/rk3399/reset_rk3399.c
new file mode 100644
index 0000000000..9a555464c6
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3399/reset_rk3399.c
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3399.h>
+#include <asm/arch/hardware.h>
+#include <linux/err.h>
+
+int rk3399_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct rk3399_cru *cru = rockchip_get_cru();
+
+ if (IS_ERR(cru))
+ return PTR_ERR(cru);
+ switch (type) {
+ case SYSRESET_WARM:
+ writel(0xeca8, &cru->glb_srst_snd_value);
+ break;
+ case SYSRESET_COLD:
+ writel(0xfdb9, &cru->glb_srst_fst_value);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk3399_sysreset = {
+ .request = rk3399_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rk3399) = {
+ .name = "rk3399_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &rk3399_sysreset,
+};
diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
new file mode 100644
index 0000000000..2d81c55cd2
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rk3399_syscon_ids[] = {
+ { .compatible = "rockchip,rk3399-grf", .data = ROCKCHIP_SYSCON_GRF },
+};
+
+U_BOOT_DRIVER(syscon_rk3399) = {
+ .name = "rk3399_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3399_syscon_ids,
+};
generated by cgit (git 2.34.1) at 2024-11-11 07:35:22 +0000