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-rw-r--r--arch/arm/lib/cache.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index b8e1e340a1..3cbed602eb 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -123,6 +123,11 @@ void invalidate_l2_cache(void)
__weak int reserve_mmu(void)
{
+ return arm_reserve_mmu();
+}
+
+__weak int arm_reserve_mmu(void)
+{
#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
/* reserve TLB table */
gd->arch.tlb_size = PGTABLE_SIZE;