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-rw-r--r--MAINTAINERS3
-rw-r--r--arch/arm/include/asm/arch-stm32/gpio.h37
-rw-r--r--arch/arm/mach-stm32mp/Kconfig13
-rw-r--r--arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c3
-rw-r--r--arch/arm/mach-stm32mp/cpu.c3
-rw-r--r--arch/arm/mach-stm32mp/include/mach/gpio.h37
-rw-r--r--arch/arm/mach-stm32mp/spl.c3
-rw-r--r--board/dhelectronics/dh_stm32mp1/board.c40
-rw-r--r--configs/stm32mp15_basic_defconfig3
-rw-r--r--configs/stm32mp15_trusted_defconfig3
-rw-r--r--drivers/gpio/stm32_gpio.c2
-rw-r--r--drivers/mmc/mmc-uclass.c2
-rw-r--r--drivers/mmc/stm32_sdmmc2.c18
13 files changed, 66 insertions, 101 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 5047ec6598..196d635bdd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -433,6 +433,7 @@ F: drivers/power/regulator/stpmic1.c
F: drivers/ram/stm32mp1/
F: drivers/remoteproc/stm32_copro.c
F: drivers/reset/stm32-reset.c
+F: drivers/rng/stm32mp1_rng.c
F: drivers/rtc/stm32_rtc.c
F: drivers/serial/serial_stm32.*
F: drivers/spi/stm32_qspi.c
@@ -446,6 +447,8 @@ F: include/dt-bindings/pinctrl/stm32-pinfunc.h
F: include/dt-bindings/reset/stm32mp1-resets.h
F: include/stm32_rcc.h
F: tools/stm32image.c
+N: stm
+N: stm32
ARM STM STV0991
diff --git a/arch/arm/include/asm/arch-stm32/gpio.h b/arch/arm/include/asm/arch-stm32/gpio.h
index 570e80a6ba..233ce278a7 100644
--- a/arch/arm/include/asm/arch-stm32/gpio.h
+++ b/arch/arm/include/asm/arch-stm32/gpio.h
@@ -7,39 +7,6 @@
#ifndef _GPIO_H_
#define _GPIO_H_
-#define STM32_GPIOS_PER_BANK 16
-
-enum stm32_gpio_port {
- STM32_GPIO_PORT_A = 0,
- STM32_GPIO_PORT_B,
- STM32_GPIO_PORT_C,
- STM32_GPIO_PORT_D,
- STM32_GPIO_PORT_E,
- STM32_GPIO_PORT_F,
- STM32_GPIO_PORT_G,
- STM32_GPIO_PORT_H,
- STM32_GPIO_PORT_I
-};
-
-enum stm32_gpio_pin {
- STM32_GPIO_PIN_0 = 0,
- STM32_GPIO_PIN_1,
- STM32_GPIO_PIN_2,
- STM32_GPIO_PIN_3,
- STM32_GPIO_PIN_4,
- STM32_GPIO_PIN_5,
- STM32_GPIO_PIN_6,
- STM32_GPIO_PIN_7,
- STM32_GPIO_PIN_8,
- STM32_GPIO_PIN_9,
- STM32_GPIO_PIN_10,
- STM32_GPIO_PIN_11,
- STM32_GPIO_PIN_12,
- STM32_GPIO_PIN_13,
- STM32_GPIO_PIN_14,
- STM32_GPIO_PIN_15
-};
-
enum stm32_gpio_mode {
STM32_GPIO_MODE_IN = 0,
STM32_GPIO_MODE_OUT,
@@ -85,8 +52,8 @@ enum stm32_gpio_af {
};
struct stm32_gpio_dsc {
- enum stm32_gpio_port port;
- enum stm32_gpio_pin pin;
+ u8 port;
+ u8 pin;
};
struct stm32_gpio_ctl {
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index 478fd2f17d..f538d7cb83 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -93,6 +93,19 @@ config SYS_TEXT_BASE
config NR_DRAM_BANKS
default 1
+config DDR_CACHEABLE_SIZE
+ hex "Size of the DDR marked cacheable in pre-reloc stage"
+ default 0x10000000 if TFABOOT
+ default 0x40000000
+ help
+ Define the size of the DDR marked as cacheable in U-Boot
+ pre-reloc stage.
+ This option can be useful to avoid speculatif access
+ to secured area of DDR used by TF-A or OP-TEE before U-Boot
+ initialization.
+ The areas marked "no-map" in device tree should be located
+ before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
+
config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
hex "Partition on MMC2 to use to load U-Boot from"
depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
index ec3355d816..a777827c55 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
@@ -768,9 +768,8 @@ static int init_device(struct stm32prog_data *data,
part_found = true;
}
+ /* no partition for this device */
if (!part_found) {
- stm32prog_err("%s (0x%x): Invalid partition",
- part->name, part->id);
pr_debug("\n");
continue;
}
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index f19e5c3f33..6785ab6b58 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -230,7 +230,8 @@ static void early_enable_caches(void)
round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
DCACHE_DEFAULT_OPTION);
else
- mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
+ mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
+ CONFIG_DDR_CACHEABLE_SIZE,
DCACHE_DEFAULT_OPTION);
}
diff --git a/arch/arm/mach-stm32mp/include/mach/gpio.h b/arch/arm/mach-stm32mp/include/mach/gpio.h
index 5ca76d21ff..7a0f293519 100644
--- a/arch/arm/mach-stm32mp/include/mach/gpio.h
+++ b/arch/arm/mach-stm32mp/include/mach/gpio.h
@@ -8,39 +8,6 @@
#define _STM32_GPIO_H_
#include <asm/gpio.h>
-#define STM32_GPIOS_PER_BANK 16
-
-enum stm32_gpio_port {
- STM32_GPIO_PORT_A = 0,
- STM32_GPIO_PORT_B,
- STM32_GPIO_PORT_C,
- STM32_GPIO_PORT_D,
- STM32_GPIO_PORT_E,
- STM32_GPIO_PORT_F,
- STM32_GPIO_PORT_G,
- STM32_GPIO_PORT_H,
- STM32_GPIO_PORT_I
-};
-
-enum stm32_gpio_pin {
- STM32_GPIO_PIN_0 = 0,
- STM32_GPIO_PIN_1,
- STM32_GPIO_PIN_2,
- STM32_GPIO_PIN_3,
- STM32_GPIO_PIN_4,
- STM32_GPIO_PIN_5,
- STM32_GPIO_PIN_6,
- STM32_GPIO_PIN_7,
- STM32_GPIO_PIN_8,
- STM32_GPIO_PIN_9,
- STM32_GPIO_PIN_10,
- STM32_GPIO_PIN_11,
- STM32_GPIO_PIN_12,
- STM32_GPIO_PIN_13,
- STM32_GPIO_PIN_14,
- STM32_GPIO_PIN_15
-};
-
enum stm32_gpio_mode {
STM32_GPIO_MODE_IN = 0,
STM32_GPIO_MODE_OUT,
@@ -86,8 +53,8 @@ enum stm32_gpio_af {
};
struct stm32_gpio_dsc {
- enum stm32_gpio_port port;
- enum stm32_gpio_pin pin;
+ u8 port;
+ u8 pin;
};
struct stm32_gpio_ctl {
diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
index e84bdad7bf..b679b0a645 100644
--- a/arch/arm/mach-stm32mp/spl.c
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -138,7 +138,8 @@ void board_init_f(ulong dummy)
* to avoid speculative access and issue in get_ram_size()
*/
if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
- mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
+ mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
+ CONFIG_DDR_CACHEABLE_SIZE,
DCACHE_DEFAULT_OPTION);
}
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index c9abe3cc6d..f42d395098 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -81,6 +81,11 @@
*/
DECLARE_GLOBAL_DATA_PTR;
+#define KS_CCR 0x08
+#define KS_CCR_EEPROM BIT(9)
+#define KS_BE0 BIT(12)
+#define KS_BE1 BIT(13)
+
int setup_mac_address(void)
{
unsigned char enetaddr[6];
@@ -97,12 +102,39 @@ int setup_mac_address(void)
if (off < 0) {
/* ethernet1 is not present in the system */
skip_eth1 = true;
- } else {
- ret = eth_env_get_enetaddr("eth1addr", enetaddr);
- if (ret) /* eth1addr is already set */
- skip_eth1 = true;
+ goto out_set_ethaddr;
+ }
+
+ ret = eth_env_get_enetaddr("eth1addr", enetaddr);
+ if (ret) {
+ /* eth1addr is already set */
+ skip_eth1 = true;
+ goto out_set_ethaddr;
+ }
+
+ ret = fdt_node_check_compatible(gd->fdt_blob, off, "micrel,ks8851-mll");
+ if (ret)
+ goto out_set_ethaddr;
+
+ /*
+ * KS8851 with EEPROM may use custom MAC from EEPROM, read
+ * out the KS8851 CCR register to determine whether EEPROM
+ * is present. If EEPROM is present, it must contain valid
+ * MAC address.
+ */
+ u32 reg, ccr;
+ reg = fdt_get_base_address(gd->fdt_blob, off);
+ if (!reg)
+ goto out_set_ethaddr;
+
+ writew(KS_BE0 | KS_BE1 | KS_CCR, reg + 2);
+ ccr = readw(reg);
+ if (ccr & KS_CCR_EEPROM) {
+ skip_eth1 = true;
+ goto out_set_ethaddr;
}
+out_set_ethaddr:
if (skip_eth0 && skip_eth1)
return 0;
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index ce7225cee1..d1dbe1a92d 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -30,9 +30,6 @@ CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_CMD_ADTIMG=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 50288fe866..9ff2ee70f0 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -14,9 +14,6 @@ CONFIG_FIT=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_CMD_ADTIMG=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c
index 473e364796..b885cfb57e 100644
--- a/drivers/gpio/stm32_gpio.c
+++ b/drivers/gpio/stm32_gpio.c
@@ -18,6 +18,8 @@
#include <linux/errno.h>
#include <linux/io.h>
+#define STM32_GPIOS_PER_BANK 16
+
#define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
#define MODE_BITS_MASK 3
#define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16))
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index ec59bcd856..285ac48061 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -228,7 +228,7 @@ int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg)
if (dev_read_bool(dev, "cap-sd-highspeed"))
cfg->host_caps |= MMC_CAP(SD_HS);
if (dev_read_bool(dev, "cap-mmc-highspeed"))
- cfg->host_caps |= MMC_CAP(MMC_HS);
+ cfg->host_caps |= MMC_CAP(MMC_HS) | MMC_CAP(MMC_HS_52);
if (dev_read_bool(dev, "sd-uhs-sdr12"))
cfg->host_caps |= MMC_CAP(UHS_SDR12);
if (dev_read_bool(dev, "sd-uhs-sdr25"))
diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c
index 6d50356217..77871d5afc 100644
--- a/drivers/mmc/stm32_sdmmc2.c
+++ b/drivers/mmc/stm32_sdmmc2.c
@@ -676,27 +676,13 @@ static int stm32_sdmmc2_probe(struct udevice *dev)
GPIOD_IS_IN);
cfg->f_min = 400000;
- cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
cfg->name = "STM32 SD/MMC";
cfg->host_caps = 0;
- if (cfg->f_max > 25000000)
- cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
-
- switch (dev_read_u32_default(dev, "bus-width", 1)) {
- case 8:
- cfg->host_caps |= MMC_MODE_8BIT;
- /* fall through */
- case 4:
- cfg->host_caps |= MMC_MODE_4BIT;
- break;
- case 1:
- break;
- default:
- pr_err("invalid \"bus-width\" property, force to 1\n");
- }
+ cfg->f_max = 52000000;
+ mmc_of_parse(dev, cfg);
upriv->mmc = &plat->mmc;
generated by cgit (git 2.34.1) at 2024-05-17 14:05:27 +0000