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-rw-r--r--drivers/mmc/renesas-sdhi.c3
-rw-r--r--drivers/mmc/tmio-common.c3
-rw-r--r--drivers/mmc/tmio-common.h2
3 files changed, 8 insertions, 0 deletions
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 24130e620b..2acb8c6efa 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -862,6 +862,9 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
return;
+ if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL)
+ priv->idma_bus_width = TMIO_SD_DMA_MODE_BUS_WIDTH;
+
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
index 2c528689bd..6c0c840bbb 100644
--- a/drivers/mmc/tmio-common.c
+++ b/drivers/mmc/tmio-common.c
@@ -324,6 +324,8 @@ static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
+ tmp |= priv->idma_bus_width;
+
if (data->flags & MMC_DATA_READ) {
buf = data->dest;
dir = DMA_FROM_DEVICE;
@@ -702,6 +704,7 @@ static void tmio_sd_host_init(struct tmio_sd_priv *priv)
if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
+ tmp |= priv->idma_bus_width;
tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
}
}
diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h
index 9062300c64..59d5a0e22e 100644
--- a/drivers/mmc/tmio-common.h
+++ b/drivers/mmc/tmio-common.h
@@ -90,6 +90,7 @@
#define TMIO_SD_VOLT_180 (2 << 0)/* 1.8V signal */
#define TMIO_SD_DMA_MODE 0x410
#define TMIO_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
+#define TMIO_SD_DMA_MODE_BUS_WIDTH (BIT(5) | BIT(4)) /* RCar, 64bit */
#define TMIO_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
#define TMIO_SD_DMA_CTL 0x414
#define TMIO_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
@@ -121,6 +122,7 @@ struct tmio_sd_priv {
unsigned int version;
u32 caps;
u32 read_poll_flag;
+ u32 idma_bus_width;
#define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
#define TMIO_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
#define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */