summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/mach-uniphier/arm64/arm-cci500.c2
-rw-r--r--arch/arm/mach-uniphier/arm64/smp_kick_cpus.c2
-rw-r--r--arch/arm/mach-uniphier/board_init.c2
-rw-r--r--arch/arm/mach-uniphier/clk/pll-pxs3.c2
-rw-r--r--arch/arm/mach-uniphier/dram/umc-ld11.c14
-rw-r--r--arch/arm/mach-uniphier/dram/umc-pxs2.c2
-rw-r--r--arch/arm/mach-uniphier/dram_init.c1
-rw-r--r--arch/arm/mach-uniphier/init.h2
-rw-r--r--drivers/clk/uniphier/clk-uniphier-core.c2
-rw-r--r--drivers/reset/reset-uniphier.c18
10 files changed, 27 insertions, 20 deletions
diff --git a/arch/arm/mach-uniphier/arm64/arm-cci500.c b/arch/arm/mach-uniphier/arm64/arm-cci500.c
index f18595dc13..bf0fad459b 100644
--- a/arch/arm/mach-uniphier/arm64/arm-cci500.c
+++ b/arch/arm/mach-uniphier/arm64/arm-cci500.c
@@ -11,6 +11,8 @@
#include <linux/io.h>
#include <linux/sizes.h>
+#include "../init.h"
+
#define CCI500_BASE 0x5FD00000
#define CCI500_SLAVE_OFFSET 0x1000
diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
index 4f08963118..8e5b198c96 100644
--- a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
+++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
@@ -8,6 +8,8 @@
#include <linux/io.h>
#include <linux/sizes.h>
+#include "../init.h"
+
#define UNIPHIER_SMPCTRL_ROM_RSV0 0x59801200
void uniphier_smp_setup(void);
diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c
index e05d6bffd5..ca910f6d72 100644
--- a/arch/arm/mach-uniphier/board_init.c
+++ b/arch/arm/mach-uniphier/board_init.c
@@ -21,7 +21,7 @@ static void uniphier_setup_xirq(void)
{
const void *fdt = gd->fdt_blob;
int soc_node, aidet_node;
- const u32 *val;
+ const fdt32_t *val;
unsigned long aidet_base;
u32 tmp;
diff --git a/arch/arm/mach-uniphier/clk/pll-pxs3.c b/arch/arm/mach-uniphier/clk/pll-pxs3.c
index e29d9d0001..201d3517a8 100644
--- a/arch/arm/mach-uniphier/clk/pll-pxs3.c
+++ b/arch/arm/mach-uniphier/clk/pll-pxs3.c
@@ -2,6 +2,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include "../init.h"
+
void uniphier_pxs3_pll_init(void)
{
}
diff --git a/arch/arm/mach-uniphier/dram/umc-ld11.c b/arch/arm/mach-uniphier/dram/umc-ld11.c
index 69aa4f2eeb..9e2021a627 100644
--- a/arch/arm/mach-uniphier/dram/umc-ld11.c
+++ b/arch/arm/mach-uniphier/dram/umc-ld11.c
@@ -28,11 +28,11 @@ enum dram_size {
};
/* PHY */
-const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
-const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
-const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} };
-const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} };
-const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} };
+static const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
+static const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
+static const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} };
+static const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} };
+static const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} };
/* Register address */
#define PHY_ZQ0CR1 0x00000184
@@ -65,7 +65,7 @@ const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} };
#define PHY_DSWBD_MASK 0x3F000000 /* bit[29:24] */
#define PHY_DSDQOE_MASK 0x00000FFF
-static void ddrphy_maskwritel(u32 data, u32 mask, void *addr)
+static void ddrphy_maskwritel(u32 data, u32 mask, void __iomem *addr)
{
u32 value;
@@ -73,7 +73,7 @@ static void ddrphy_maskwritel(u32 data, u32 mask, void *addr)
writel(value, addr);
}
-static u32 ddrphy_maskreadl(u32 mask, void *addr)
+static u32 ddrphy_maskreadl(u32 mask, void __iomem *addr)
{
return readl(addr) & mask;
}
diff --git a/arch/arm/mach-uniphier/dram/umc-pxs2.c b/arch/arm/mach-uniphier/dram/umc-pxs2.c
index 7fa29f119d..8068ef1388 100644
--- a/arch/arm/mach-uniphier/dram/umc-pxs2.c
+++ b/arch/arm/mach-uniphier/dram/umc-pxs2.c
@@ -436,7 +436,7 @@ static void umc_set_system_latency(void __iomem *dc_base, int phy_latency)
}
/* enable/disable auto refresh */
-void umc_refresh_ctrl(void __iomem *dc_base, int enable)
+static void umc_refresh_ctrl(void __iomem *dc_base, int enable)
{
u32 tmp;
diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c
index f79b7cf3ca..6eb8d26504 100644
--- a/arch/arm/mach-uniphier/dram_init.c
+++ b/arch/arm/mach-uniphier/dram_init.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <fdt_support.h>
#include <fdtdec.h>
#include <linux/errno.h>
#include <linux/sizes.h>
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index d413d00f95..56f514e297 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -126,7 +126,7 @@ int uniphier_have_internal_stm(void);
int uniphier_boot_from_backend(void);
int uniphier_pin_init(const char *pinconfig_name);
void uniphier_smp_kick_all_cpus(void);
-void cci500_init(int nr_slaves);
+void cci500_init(unsigned int nr_slaves);
#undef pr_warn
#define pr_warn(fmt, args...) printf(fmt, ##args)
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index d88bd62812..0fb48541b9 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -121,7 +121,7 @@ static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate)
return best_rate;
}
-const struct clk_ops uniphier_clk_ops = {
+static const struct clk_ops uniphier_clk_ops = {
.enable = uniphier_clk_enable,
.get_rate = uniphier_clk_get_rate,
.set_rate = uniphier_clk_set_rate,
diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c
index e98df43bdb..17e971a427 100644
--- a/drivers/reset/reset-uniphier.c
+++ b/drivers/reset/reset-uniphier.c
@@ -56,12 +56,12 @@ struct uniphier_reset_data {
#define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \
UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17)
-const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = {
+static const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = {
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */
UNIPHIER_RESET_END,
};
-const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
+static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */
UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */
UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
@@ -69,7 +69,7 @@ const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
UNIPHIER_RESET_END,
};
-const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
+static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */
UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */
UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
@@ -77,7 +77,7 @@ const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
UNIPHIER_RESET_END,
};
-const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
+static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */
UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
@@ -91,12 +91,12 @@ const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
UNIPHIER_RESET_END,
};
-const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
+static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */
UNIPHIER_RESET_END,
};
-const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
+static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */
UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */
UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
@@ -125,7 +125,7 @@ const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
#define UNIPHIER_MIO_RESET_DMAC(id) \
UNIPHIER_RESETX((id), 0x110, 17)
-const struct uniphier_reset_data uniphier_mio_reset_data[] = {
+static const struct uniphier_reset_data uniphier_mio_reset_data[] = {
UNIPHIER_MIO_RESET_SD(0, 0),
UNIPHIER_MIO_RESET_SD(1, 1),
UNIPHIER_MIO_RESET_SD(2, 2),
@@ -155,7 +155,7 @@ const struct uniphier_reset_data uniphier_mio_reset_data[] = {
#define UNIPHIER_PERI_RESET_FI2C(id, ch) \
UNIPHIER_RESETX((id), 0x114, 24 + (ch))
-const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
+static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
UNIPHIER_PERI_RESET_UART(0, 0),
UNIPHIER_PERI_RESET_UART(1, 1),
UNIPHIER_PERI_RESET_UART(2, 2),
@@ -168,7 +168,7 @@ const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
UNIPHIER_RESET_END,
};
-const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
+static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
UNIPHIER_PERI_RESET_UART(0, 0),
UNIPHIER_PERI_RESET_UART(1, 1),
UNIPHIER_PERI_RESET_UART(2, 2),
generated by cgit (git 2.34.1) at 2024-12-24 17:49:51 +0000