diff options
48 files changed, 624 insertions, 307 deletions
diff --git a/arch/arm/include/asm/arch-meson/axg.h b/arch/arm/include/asm/arch-meson/axg.h index 91c87696e0..12042de935 100644 --- a/arch/arm/include/asm/arch-meson/axg.h +++ b/arch/arm/include/asm/arch-meson/axg.h @@ -31,26 +31,4 @@ #define AXG_AO_BL31_RSVMEM_SIZE_SHIFT 16 #define AXG_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF -/* Peripherals registers */ -#define AXG_PERIPHS_ADDR(off) (AXG_PERIPHS_BASE + ((off) << 2)) - -#define AXG_ETH_REG_0 AXG_PERIPHS_ADDR(0x50) -#define AXG_ETH_REG_1 AXG_PERIPHS_ADDR(0x51) - -#define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0) -#define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2) -#define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) -#define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) -#define AXG_ETH_REG_0_PHY_CLK_EN BIT(10) -#define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11) -#define AXG_ETH_REG_0_CLK_EN BIT(12) - -/* HIU registers */ -#define AXG_HIU_ADDR(off) (AXG_HIU_BASE + ((off) << 2)) - -#define AXG_MEM_PD_REG_0 AXG_HIU_ADDR(0x40) - -/* Ethernet memory power domain */ -#define AXG_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) - #endif /* __AXG_H__ */ diff --git a/arch/arm/include/asm/arch-meson/eth.h b/arch/arm/include/asm/arch-meson/eth.h index f765cd7c4c..c0070615c2 100644 --- a/arch/arm/include/asm/arch-meson/eth.h +++ b/arch/arm/include/asm/arch-meson/eth.h @@ -7,18 +7,6 @@ #ifndef __MESON_ETH_H__ #define __MESON_ETH_H__ -#include <phy.h> - -enum { - /* Use Internal RMII PHY */ - MESON_USE_INTERNAL_RMII_PHY = 1, -}; - -/* Configure the Ethernet MAC with the requested interface mode - * with some optional flags. - */ -void meson_eth_init(phy_interface_t mode, unsigned int flags); - /* Generate an unique MAC address based on the HW serial */ int meson_generate_serial_ethaddr(void); diff --git a/arch/arm/include/asm/arch-meson/g12a.h b/arch/arm/include/asm/arch-meson/g12a.h index db29cc3a00..ef4f301f7d 100644 --- a/arch/arm/include/asm/arch-meson/g12a.h +++ b/arch/arm/include/asm/arch-meson/g12a.h @@ -32,39 +32,4 @@ #define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16 #define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF -/* Peripherals registers */ -#define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2)) - -#define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50) -#define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51) - -#define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0) -#define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2) -#define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) -#define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) -#define G12A_ETH_REG_0_PHY_CLK_EN BIT(10) -#define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11) -#define G12A_ETH_REG_0_CLK_EN BIT(12) - -#define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2)) -#define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11) -#define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12) -#define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13) -#define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14) -#define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15) -#define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16) -#define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17) -#define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18) -#define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20) -#define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21) -#define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22) - -/* HIU registers */ -#define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2)) - -#define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40) - -/* Ethernet memory power domain */ -#define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) - #endif /* __G12A_H__ */ diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h index 743d2e8bb9..26ec5d0bc3 100644 --- a/arch/arm/include/asm/arch-meson/gx.h +++ b/arch/arm/include/asm/arch-meson/gx.h @@ -41,24 +41,4 @@ #define GX_GPIO_IN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1) #define GX_GPIO_OUT(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2) -#define GX_ETH_REG_0 GX_PERIPHS_ADDR(0x50) -#define GX_ETH_REG_1 GX_PERIPHS_ADDR(0x51) -#define GX_ETH_REG_2 GX_PERIPHS_ADDR(0x56) -#define GX_ETH_REG_3 GX_PERIPHS_ADDR(0x57) - -#define GX_ETH_REG_0_PHY_INTF BIT(0) -#define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) -#define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) -#define GX_ETH_REG_0_PHY_CLK_EN BIT(10) -#define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11) -#define GX_ETH_REG_0_CLK_EN BIT(12) - -/* HIU registers */ -#define GX_HIU_ADDR(off) (GX_HIU_BASE + ((off) << 2)) - -#define GX_MEM_PD_REG_0 GX_HIU_ADDR(0x40) - -/* Ethernet memory power domain */ -#define GX_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) - #endif /* __GX_H__ */ diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c index 3b14bc9989..71ac65c636 100644 --- a/arch/arm/mach-meson/board-axg.c +++ b/arch/arm/mach-meson/board-axg.c @@ -91,40 +91,6 @@ static struct mm_region axg_mem_map[] = { struct mm_region *mem_map = axg_mem_map; -/* Configure the Ethernet MAC with the requested interface mode - * with some optional flags. - */ -void meson_eth_init(phy_interface_t mode, unsigned int flags) -{ - switch (mode) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: - /* Set RGMII mode */ - setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII | - AXG_ETH_REG_0_TX_PHASE(1) | - AXG_ETH_REG_0_TX_RATIO(4) | - AXG_ETH_REG_0_PHY_CLK_EN | - AXG_ETH_REG_0_CLK_EN); - break; - - case PHY_INTERFACE_MODE_RMII: - /* Set RMII mode */ - out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII | - AXG_ETH_REG_0_INVERT_RMII_CLK | - AXG_ETH_REG_0_CLK_EN); - break; - - default: - printf("Invalid Ethernet interface mode\n"); - return; - } - - /* Enable power gate */ - clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK); -} - #if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \ CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG) static struct dwc2_plat_otg_data meson_gx_dwc2_data; diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c index bb75d4f8ad..2e59eee8f7 100644 --- a/arch/arm/mach-meson/board-g12a.c +++ b/arch/arm/mach-meson/board-g12a.c @@ -97,73 +97,6 @@ static struct mm_region g12a_mem_map[] = { struct mm_region *mem_map = g12a_mem_map; -static void g12a_enable_external_mdio(void) -{ - writel(0x0, ETH_PHY_CNTL2); -} - -static void g12a_enable_internal_mdio(void) -{ - /* Fire up the PHY PLL */ - writel(0x29c0040a, ETH_PLL_CNTL0); - writel(0x927e0000, ETH_PLL_CNTL1); - writel(0xac5f49e5, ETH_PLL_CNTL2); - writel(0x00000000, ETH_PLL_CNTL3); - writel(0x00000000, ETH_PLL_CNTL4); - writel(0x20200000, ETH_PLL_CNTL5); - writel(0x0000c002, ETH_PLL_CNTL6); - writel(0x00000023, ETH_PLL_CNTL7); - writel(0x39c0040a, ETH_PLL_CNTL0); - writel(0x19c0040a, ETH_PLL_CNTL0); - - /* Select the internal MDIO */ - writel(0x33000180, ETH_PHY_CNTL0); - writel(0x00074043, ETH_PHY_CNTL1); - writel(0x00000260, ETH_PHY_CNTL2); -} - -/* Configure the Ethernet MAC with the requested interface mode - * with some optional flags. - */ -void meson_eth_init(phy_interface_t mode, unsigned int flags) -{ - switch (mode) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: - /* Set RGMII mode */ - setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII | - G12A_ETH_REG_0_TX_PHASE(1) | - G12A_ETH_REG_0_TX_RATIO(4) | - G12A_ETH_REG_0_PHY_CLK_EN | - G12A_ETH_REG_0_CLK_EN); - g12a_enable_external_mdio(); - break; - - case PHY_INTERFACE_MODE_RMII: - /* Set RMII mode */ - out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII | - G12A_ETH_REG_0_INVERT_RMII_CLK | - G12A_ETH_REG_0_CLK_EN); - - /* Use G12A RMII Internal PHY */ - if (flags & MESON_USE_INTERNAL_RMII_PHY) - g12a_enable_internal_mdio(); - else - g12a_enable_external_mdio(); - - break; - - default: - printf("Invalid Ethernet interface mode\n"); - return; - } - - /* Enable power gate */ - clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK); -} - #if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \ CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG) static struct dwc2_plat_otg_data meson_g12a_dwc2_data; diff --git a/arch/arm/mach-meson/board-gx.c b/arch/arm/mach-meson/board-gx.c index f5273f42af..01fafd81c4 100644 --- a/arch/arm/mach-meson/board-gx.c +++ b/arch/arm/mach-meson/board-gx.c @@ -109,54 +109,6 @@ static struct mm_region gx_mem_map[] = { struct mm_region *mem_map = gx_mem_map; -/* Configure the Ethernet MAC with the requested interface mode - * with some optional flags. - */ -void meson_eth_init(phy_interface_t mode, unsigned int flags) -{ - switch (mode) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: - /* Set RGMII mode */ - setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF | - GX_ETH_REG_0_TX_PHASE(1) | - GX_ETH_REG_0_TX_RATIO(4) | - GX_ETH_REG_0_PHY_CLK_EN | - GX_ETH_REG_0_CLK_EN); - - /* Reset to external PHY */ - if(!IS_ENABLED(CONFIG_MESON_GXBB)) - writel(0x2009087f, GX_ETH_REG_3); - - break; - - case PHY_INTERFACE_MODE_RMII: - /* Set RMII mode */ - out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK | - GX_ETH_REG_0_CLK_EN); - - /* Use GXL RMII Internal PHY (also on GXM) */ - if (!IS_ENABLED(CONFIG_MESON_GXBB)) { - if ((flags & MESON_USE_INTERNAL_RMII_PHY)) { - writel(0x10110181, GX_ETH_REG_2); - writel(0xe40908ff, GX_ETH_REG_3); - } else - writel(0x2009087f, GX_ETH_REG_3); - } - - break; - - default: - printf("Invalid Ethernet interface mode\n"); - return; - } - - /* Enable power gate */ - clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK); -} - #if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \ CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG) static struct dwc2_plat_otg_data meson_gx_dwc2_data; diff --git a/board/amlogic/beelink-s922x/beelink-s922x.c b/board/amlogic/beelink-s922x/beelink-s922x.c index dc0d933a39..bb74426266 100644 --- a/board/amlogic/beelink-s922x/beelink-s922x.c +++ b/board/amlogic/beelink-s922x/beelink-s922x.c @@ -28,8 +28,6 @@ int misc_init_r(void) meson_get_soc_rev(tmp, sizeof(tmp)) > 0) env_set("soc_rev", tmp); - meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0); - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, efuse_mac_addr, EFUSE_MAC_SIZE); diff --git a/board/amlogic/odroid-n2/odroid-n2.c b/board/amlogic/odroid-n2/odroid-n2.c index 863975e51b..88a60f34fe 100644 --- a/board/amlogic/odroid-n2/odroid-n2.c +++ b/board/amlogic/odroid-n2/odroid-n2.c @@ -115,8 +115,6 @@ int misc_init_r(void) meson_get_soc_rev(tmp, sizeof(tmp)) > 0) env_set("soc_rev", tmp); - meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0); - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, efuse_mac_addr, EFUSE_MAC_SIZE); diff --git a/board/amlogic/p200/p200.c b/board/amlogic/p200/p200.c index 8f1bf8bfda..7c432f9d28 100644 --- a/board/amlogic/p200/p200.c +++ b/board/amlogic/p200/p200.c @@ -25,8 +25,6 @@ int misc_init_r(void) char serial[EFUSE_SN_SIZE]; ssize_t len; - meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0); - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, mac_addr, EFUSE_MAC_SIZE); diff --git a/board/amlogic/p201/p201.c b/board/amlogic/p201/p201.c index 597bb71cbf..7c432f9d28 100644 --- a/board/amlogic/p201/p201.c +++ b/board/amlogic/p201/p201.c @@ -25,8 +25,6 @@ int misc_init_r(void) char serial[EFUSE_SN_SIZE]; ssize_t len; - meson_eth_init(PHY_INTERFACE_MODE_RMII, 0); - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, mac_addr, EFUSE_MAC_SIZE); diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c index fbc49e9565..fcef90bce5 100644 --- a/board/amlogic/p212/p212.c +++ b/board/amlogic/p212/p212.c @@ -26,9 +26,6 @@ int misc_init_r(void) char serial[EFUSE_SN_SIZE]; ssize_t len; - meson_eth_init(PHY_INTERFACE_MODE_RMII, - MESON_USE_INTERNAL_RMII_PHY); - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, mac_addr, EFUSE_MAC_SIZE); diff --git a/board/amlogic/q200/q200.c b/board/amlogic/q200/q200.c index 62e6fa3d19..3aa6d8f200 100644 --- a/board/amlogic/q200/q200.c +++ b/board/amlogic/q200/q200.c @@ -26,8 +26,6 @@ int misc_init_r(void) char serial[EFUSE_SN_SIZE]; ssize_t len; - meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0); - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, mac_addr, EFUSE_MAC_SIZE); diff --git a/board/amlogic/s400/s400.c b/board/amlogic/s400/s400.c index b081942dcc..06a9044fd8 100644 --- a/board/amlogic/s400/s400.c +++ b/board/amlogic/s400/s400.c @@ -16,8 +16,6 @@ int misc_init_r(void) { - meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0); - meson_generate_serial_ethaddr(); return 0; diff --git a/board/amlogic/sei510/sei510.c b/board/amlogic/sei510/sei510.c index 5a5148ea68..bb188c21f7 100644 --- a/board/amlogic/sei510/sei510.c +++ b/board/amlogic/sei510/sei510.c @@ -18,9 +18,6 @@ int misc_init_r(void) { - meson_eth_init(PHY_INTERFACE_MODE_RMII, - MESON_USE_INTERNAL_RMII_PHY); - meson_generate_serial_ethaddr(); env_set("serial#", "AMLG12ASEI510"); diff --git a/board/amlogic/sei610/sei610.c b/board/amlogic/sei610/sei610.c index 27dba93582..6490bac9eb 100644 --- a/board/amlogic/sei610/sei610.c +++ b/board/amlogic/sei610/sei610.c @@ -18,9 +18,6 @@ int misc_init_r(void) { - meson_eth_init(PHY_INTERFACE_MODE_RMII, - MESON_USE_INTERNAL_RMII_PHY); - meson_generate_serial_ethaddr(); env_set("serial#", "AMLG12ASEI610"); diff --git a/board/amlogic/u200/u200.c b/board/amlogic/u200/u200.c index 373235d77a..06a9044fd8 100644 --- a/board/amlogic/u200/u200.c +++ b/board/amlogic/u200/u200.c @@ -16,8 +16,7 @@ int misc_init_r(void) { - meson_eth_init(PHY_INTERFACE_MODE_RMII, - MESON_USE_INTERNAL_RMII_PHY); + meson_generate_serial_ethaddr(); return 0; } diff --git a/board/amlogic/vim3/vim3.c b/board/amlogic/vim3/vim3.c index 7b09617cdc..6cd5f2e115 100644 --- a/board/amlogic/vim3/vim3.c +++ b/board/amlogic/vim3/vim3.c @@ -149,8 +149,6 @@ int misc_init_r(void) char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3]; ssize_t len; - meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0); - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, efuse_mac_addr, EFUSE_MAC_SIZE); diff --git a/board/amlogic/w400/w400.c b/board/amlogic/w400/w400.c index 47a51710dc..4199198496 100644 --- a/board/amlogic/w400/w400.c +++ b/board/amlogic/w400/w400.c @@ -14,7 +14,7 @@ int misc_init_r(void) { - meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0); + meson_generate_serial_ethaddr(); return 0; } diff --git a/configs/beelink-gtking_defconfig b/configs/beelink-gtking_defconfig index 6270c23bb0..12caa58697 100644 --- a/configs/beelink-gtking_defconfig +++ b/configs/beelink-gtking_defconfig @@ -30,9 +30,12 @@ CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MESON_G12A=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_G12A_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_G12A=y diff --git a/configs/beelink-gtkingpro_defconfig b/configs/beelink-gtkingpro_defconfig index 310654e353..2b022e42ed 100644 --- a/configs/beelink-gtkingpro_defconfig +++ b/configs/beelink-gtkingpro_defconfig @@ -30,9 +30,12 @@ CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MESON_G12A=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_G12A_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_G12A=y diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig index c26c0ca45c..0aaa6c0db3 100644 --- a/configs/khadas-vim2_defconfig +++ b/configs/khadas-vim2_defconfig @@ -36,9 +36,12 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MMIOREG=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig index bc17430569..cd0327c06b 100644 --- a/configs/khadas-vim3_defconfig +++ b/configs/khadas-vim3_defconfig @@ -41,9 +41,12 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MESON_G12A=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_G12A_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_G12A=y diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig index c1877922c7..ef85f00dd8 100644 --- a/configs/khadas-vim3l_defconfig +++ b/configs/khadas-vim3l_defconfig @@ -41,9 +41,12 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MESON_G12A=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_G12A_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_G12A=y diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig index e7e5c42035..60cdfffe39 100644 --- a/configs/khadas-vim_defconfig +++ b/configs/khadas-vim_defconfig @@ -30,11 +30,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SARADC_MESON=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_PHY_ADDR=8 +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MMIOREG=y CONFIG_PHY_MESON_GXL=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig index ca61591bd7..b383dfb654 100644 --- a/configs/libretech-ac_defconfig +++ b/configs/libretech-ac_defconfig @@ -37,16 +37,17 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SARADC_MESON=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MMIOREG=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_PHY_ADDR=8 CONFIG_PHY_MESON_GXL=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig index fb4bf4c929..ba59dee637 100644 --- a/configs/libretech-cc_defconfig +++ b/configs/libretech-cc_defconfig @@ -29,11 +29,12 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SARADC_MESON=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_PHY_ADDR=8 +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MMIOREG=y CONFIG_PHY_MESON_GXL=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig index 86f88dbc6e..50ae3e16ae 100644 --- a/configs/libretech-cc_v2_defconfig +++ b/configs/libretech-cc_v2_defconfig @@ -37,11 +37,12 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_PHY_ADDR=8 +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MMIOREG=y CONFIG_PHY_MESON_GXL=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_PHY=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig index 85dfd9c730..9ef638598d 100644 --- a/configs/libretech-s905d-pc_defconfig +++ b/configs/libretech-s905d-pc_defconfig @@ -38,9 +38,12 @@ CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MMIOREG=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig index a515833cc5..a14ac20985 100644 --- a/configs/libretech-s912-pc_defconfig +++ b/configs/libretech-s912-pc_defconfig @@ -37,9 +37,12 @@ CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MMIOREG=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig index c2dc488171..4332271779 100644 --- a/configs/nanopi-k2_defconfig +++ b/configs/nanopi-k2_defconfig @@ -29,7 +29,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXBB=y CONFIG_DM_REGULATOR=y diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig index 5c02fa1e62..7ce65b1376 100644 --- a/configs/odroid-c2_defconfig +++ b/configs/odroid-c2_defconfig @@ -32,7 +32,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_PHY=y CONFIG_MESON_GXBB_USB_PHY=y CONFIG_PINCTRL=y diff --git a/configs/odroid-c4_defconfig b/configs/odroid-c4_defconfig index 8a9b8b0c02..48fb8915a0 100644 --- a/configs/odroid-c4_defconfig +++ b/configs/odroid-c4_defconfig @@ -30,9 +30,12 @@ CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MESON_G12A=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_G12A_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_G12A=y diff --git a/configs/odroid-n2_defconfig b/configs/odroid-n2_defconfig index b82bd78f2d..d2a8c342c2 100644 --- a/configs/odroid-n2_defconfig +++ b/configs/odroid-n2_defconfig @@ -30,9 +30,12 @@ CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MESON_G12A=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_G12A_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_G12A=y diff --git a/configs/p200_defconfig b/configs/p200_defconfig index 6efc7bc92d..c61e974321 100644 --- a/configs/p200_defconfig +++ b/configs/p200_defconfig @@ -28,7 +28,7 @@ CONFIG_SYS_I2C_MESON=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXBB=y CONFIG_DM_REGULATOR=y diff --git a/configs/p201_defconfig b/configs/p201_defconfig index a1d3f04b4f..34dc154d69 100644 --- a/configs/p201_defconfig +++ b/configs/p201_defconfig @@ -29,7 +29,7 @@ CONFIG_SYS_I2C_MESON=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXBB=y CONFIG_DM_REGULATOR=y diff --git a/configs/p212_defconfig b/configs/p212_defconfig index da66c50ea0..c36a674eab 100644 --- a/configs/p212_defconfig +++ b/configs/p212_defconfig @@ -27,11 +27,12 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_PHY_ADDR=8 +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MMIOREG=y CONFIG_PHY_MESON_GXL=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/s400_defconfig b/configs/s400_defconfig index a15ac32986..39e44c0c44 100644 --- a/configs/s400_defconfig +++ b/configs/s400_defconfig @@ -29,7 +29,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_AXG=y diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig index 7b97a2f6f3..2c84abf591 100644 --- a/configs/sei510_defconfig +++ b/configs/sei510_defconfig @@ -45,10 +45,11 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y # CONFIG_INPUT is not set CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_PHY_ADDR=8 +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MESON_G12A=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_G12A_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_G12A=y diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig index 0ed17091b5..392ab64642 100644 --- a/configs/sei610_defconfig +++ b/configs/sei610_defconfig @@ -45,10 +45,11 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y # CONFIG_INPUT is not set CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_PHY_ADDR=8 +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MESON_G12A=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_G12A_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_G12A=y diff --git a/configs/u200_defconfig b/configs/u200_defconfig index b0b822b9cb..4da02f1598 100644 --- a/configs/u200_defconfig +++ b/configs/u200_defconfig @@ -27,10 +27,11 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_PHY_ADDR=8 +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MESON_G12A=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_G12A_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_G12A=y diff --git a/configs/wetek-core2_defconfig b/configs/wetek-core2_defconfig index cbe747b63e..098e2493e3 100644 --- a/configs/wetek-core2_defconfig +++ b/configs/wetek-core2_defconfig @@ -31,9 +31,12 @@ CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_MDIO_MUX_MMIOREG=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_MESON8B=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 0e84c22b50..cf062fad4d 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -271,6 +271,14 @@ config ETH_DESIGNWARE 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to provide the PHY (physical media interface). +config ETH_DESIGNWARE_MESON8B + bool "Amlogic Meson8b and later glue driver for Synopsys Designware Ethernet MAC" + depends on DM_ETH + select ETH_DESIGNWARE + help + This provides glue layer to use Synopsys Designware Ethernet MAC + present on the Amlogic Meson8b, GX, AXG & G12A SoCs. + config ETH_DESIGNWARE_SOCFPGA select REGMAP select SYSCON @@ -790,4 +798,18 @@ config FSL_LS_MDIO This driver supports the MDIO bus found on the Fman 10G Ethernet MACs and on the mEMAC (which supports both Clauses 22 and 45). +config MDIO_MUX_MMIOREG + bool "MDIO MUX accessed as a MMIO register access" + depends on DM_MDIO_MUX + help + This driver is used for MDIO muxes driven by writing to a register in + the MMIO physical memory. + +config MDIO_MUX_MESON_G12A + bool "MDIO MUX for Amlogic Meson G12A SoCs" + depends on DM_MDIO_MUX + help + This driver is used for the MDIO mux found on the Amlogic G12A & compatible + SoCs. + endif # NETDEVICES diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a19511aaa7..ce7b9e3478 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_CORTINA_NI_ENET) += cortina_ni.o obj-$(CONFIG_CS8900) += cs8900.o obj-$(CONFIG_TULIP) += dc2114x.o obj-$(CONFIG_ETH_DESIGNWARE) += designware.o +obj-$(CONFIG_ETH_DESIGNWARE_MESON8B) += dwmac_meson8b.o obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o obj-$(CONFIG_ETH_DESIGNWARE_S700) += dwmac_s700.o obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o @@ -43,6 +44,8 @@ obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o +obj-$(CONFIG_MDIO_MUX_MESON_G12A) += mdio_mux_meson_g12a.o +obj-$(CONFIG_MDIO_MUX_MMIOREG) += mdio_mux_mmioreg.o obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o obj-$(CONFIG_MT7620_ETH) += mt7620-eth.o diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 9dba55adaa..b8ba00b7c0 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -21,7 +21,9 @@ #include <reset.h> #include <asm/cache.h> #include <dm/device_compat.h> +#include <dm/device-internal.h> #include <dm/devres.h> +#include <dm/lists.h> #include <linux/compiler.h> #include <linux/delay.h> #include <linux/err.h> @@ -122,6 +124,55 @@ static int dw_mdio_reset(struct mii_dev *bus) } #endif +#if IS_ENABLED(CONFIG_DM_MDIO) +int designware_eth_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg) +{ + struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev); + + return dw_mdio_read(pdata->mii_bus, addr, devad, reg); +} + +int designware_eth_mdio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val) +{ + struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev); + + return dw_mdio_write(pdata->mii_bus, addr, devad, reg, val); +} + +#if CONFIG_IS_ENABLED(DM_GPIO) +int designware_eth_mdio_reset(struct udevice *mdio_dev) +{ + struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev); + + return dw_mdio_reset(pdata->mii_bus); +} +#endif + +static const struct mdio_ops designware_eth_mdio_ops = { + .read = designware_eth_mdio_read, + .write = designware_eth_mdio_write, +#if CONFIG_IS_ENABLED(DM_GPIO) + .reset = designware_eth_mdio_reset, +#endif +}; + +static int designware_eth_mdio_probe(struct udevice *dev) +{ + /* Use the priv data of parent */ + dev_set_priv(dev, dev_get_priv(dev->parent)); + + return 0; +} + +U_BOOT_DRIVER(designware_eth_mdio) = { + .name = "eth_designware_mdio", + .id = UCLASS_MDIO, + .probe = designware_eth_mdio_probe, + .ops = &designware_eth_mdio_ops, + .plat_auto = sizeof(struct mdio_perdev_priv), +}; +#endif + static int dw_mdio_init(const char *name, void *priv) { struct mii_dev *bus = mdio_alloc(); @@ -143,6 +194,34 @@ static int dw_mdio_init(const char *name, void *priv) return mdio_register(bus); } +#if IS_ENABLED(CONFIG_DM_MDIO) +static int dw_dm_mdio_init(const char *name, void *priv) +{ + struct udevice *dev = priv; + ofnode node; + int ret; + + ofnode_for_each_subnode(node, dev_ofnode(dev)) { + const char *subnode_name = ofnode_get_name(node); + struct udevice *mdiodev; + + if (strcmp(subnode_name, "mdio")) + continue; + + ret = device_bind_driver_to_node(dev, "eth_designware_mdio", + subnode_name, node, &mdiodev); + if (ret) + debug("%s: not able to bind mdio device node\n", __func__); + + return 0; + } + + printf("%s: mdio node is missing, registering legacy mdio bus", __func__); + + return dw_mdio_init(name, priv); +} +#endif + static void tx_descs_init(struct dw_eth_dev *priv) { struct eth_dma_regs *dma_p = priv->dma_regs_p; @@ -487,7 +566,14 @@ static int _dw_free_pkt(struct dw_eth_dev *priv) static int dw_phy_init(struct dw_eth_dev *priv, void *dev) { struct phy_device *phydev; - int phy_addr = -1, ret; + int ret; + +#if IS_ENABLED(CONFIG_DM_MDIO) && IS_ENABLED(CONFIG_DM_ETH) + phydev = dm_eth_phy_connect(dev); + if (!phydev) + return -ENODEV; +#else + int phy_addr = -1; #ifdef CONFIG_PHY_ADDR phy_addr = CONFIG_PHY_ADDR; @@ -496,6 +582,7 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface); if (!phydev) return -ENODEV; +#endif phydev->supported &= PHY_GBIT_FEATURES; if (priv->max_speed) { @@ -759,7 +846,11 @@ int designware_eth_probe(struct udevice *dev) priv->interface = pdata->phy_interface; priv->max_speed = pdata->max_speed; +#if IS_ENABLED(CONFIG_DM_MDIO) + ret = dw_dm_mdio_init(dev->name, dev); +#else ret = dw_mdio_init(dev->name, dev); +#endif if (ret) { err = ret; goto mdio_err; @@ -856,9 +947,6 @@ int designware_eth_of_to_plat(struct udevice *dev) static const struct udevice_id designware_eth_ids[] = { { .compatible = "allwinner,sun7i-a20-gmac" }, { .compatible = "amlogic,meson6-dwmac" }, - { .compatible = "amlogic,meson-gx-dwmac" }, - { .compatible = "amlogic,meson-gxbb-dwmac" }, - { .compatible = "amlogic,meson-axg-dwmac" }, { .compatible = "st,stm32-dwmac" }, { .compatible = "snps,arc-dwmac-3.70a" }, { } diff --git a/drivers/net/dwmac_meson8b.c b/drivers/net/dwmac_meson8b.c new file mode 100644 index 0000000000..c0b6ef4994 --- /dev/null +++ b/drivers/net/dwmac_meson8b.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 BayLibre, SAS + */ + +#include <common.h> +#include <asm/io.h> +#include <dm.h> +#include <phy.h> +#include "designware.h" +#include <dm/device_compat.h> +#include <linux/err.h> + +#define ETH_REG_0 0x0 +#define ETH_REG_1 0x4 +#define ETH_REG_2 0x18 +#define ETH_REG_3 0x1c + +#define GX_ETH_REG_0_PHY_INTF BIT(0) +#define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) +#define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) +#define GX_ETH_REG_0_PHY_CLK_EN BIT(10) +#define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11) +#define GX_ETH_REG_0_CLK_EN BIT(12) + +#define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0) +#define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2) +#define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) +#define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) +#define AXG_ETH_REG_0_PHY_CLK_EN BIT(10) +#define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11) +#define AXG_ETH_REG_0_CLK_EN BIT(12) + +struct dwmac_meson8b_plat { + struct dw_eth_pdata dw_eth_pdata; + int (*dwmac_setup)(struct udevice *dev, struct eth_pdata *edata); + void *regs; +}; + +static int dwmac_meson8b_of_to_plat(struct udevice *dev) +{ + struct dwmac_meson8b_plat *pdata = dev_get_plat(dev); + + pdata->regs = (void *)dev_read_addr_index(dev, 1); + if ((fdt_addr_t)pdata->regs == FDT_ADDR_T_NONE) + return -EINVAL; + + pdata->dwmac_setup = (void *)dev_get_driver_data(dev); + if (!pdata->dwmac_setup) + return -EINVAL; + + return designware_eth_of_to_plat(dev); +} + +static int dwmac_setup_axg(struct udevice *dev, struct eth_pdata *edata) +{ + struct dwmac_meson8b_plat *plat = dev_get_plat(dev); + + switch (edata->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set RGMII mode */ + setbits_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII | + AXG_ETH_REG_0_TX_PHASE(1) | + AXG_ETH_REG_0_TX_RATIO(4) | + AXG_ETH_REG_0_PHY_CLK_EN | + AXG_ETH_REG_0_CLK_EN); + break; + + case PHY_INTERFACE_MODE_RMII: + /* Set RMII mode */ + out_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII | + AXG_ETH_REG_0_INVERT_RMII_CLK | + AXG_ETH_REG_0_CLK_EN); + break; + default: + dev_err(dev, "Unsupported PHY mode\n"); + return -EINVAL; + } + + return 0; +} + +static int dwmac_setup_gx(struct udevice *dev, struct eth_pdata *edata) +{ + struct dwmac_meson8b_plat *plat = dev_get_plat(dev); + + switch (edata->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set RGMII mode */ + setbits_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_PHY_INTF | + GX_ETH_REG_0_TX_PHASE(1) | + GX_ETH_REG_0_TX_RATIO(4) | + GX_ETH_REG_0_PHY_CLK_EN | + GX_ETH_REG_0_CLK_EN); + + break; + + case PHY_INTERFACE_MODE_RMII: + /* Set RMII mode */ + out_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK | + GX_ETH_REG_0_CLK_EN); + + if (!IS_ENABLED(CONFIG_MESON_GXBB)) + writel(0x10110181, plat->regs + ETH_REG_2); + + break; + default: + dev_err(dev, "Unsupported PHY mode\n"); + return -EINVAL; + } + + return 0; +} + +static int dwmac_meson8b_probe(struct udevice *dev) +{ + struct dwmac_meson8b_plat *pdata = dev_get_plat(dev); + struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata; + int ret; + + ret = pdata->dwmac_setup(dev, edata); + if (ret) + return ret; + + return designware_eth_probe(dev); +} + +static const struct udevice_id dwmac_meson8b_ids[] = { + { .compatible = "amlogic,meson-gxbb-dwmac", .data = (ulong)dwmac_setup_gx }, + { .compatible = "amlogic,meson-axg-dwmac", .data = (ulong)dwmac_setup_axg }, + { } +}; + +U_BOOT_DRIVER(dwmac_meson8b) = { + .name = "dwmac_meson8b", + .id = UCLASS_ETH, + .of_match = dwmac_meson8b_ids, + .of_to_plat = dwmac_meson8b_of_to_plat, + .probe = dwmac_meson8b_probe, + .ops = &designware_eth_ops, + .priv_auto = sizeof(struct dw_eth_dev), + .plat_auto = sizeof(struct dwmac_meson8b_plat), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/net/mdio_mux_meson_g12a.c b/drivers/net/mdio_mux_meson_g12a.c new file mode 100644 index 0000000000..b520bf98f0 --- /dev/null +++ b/drivers/net/mdio_mux_meson_g12a.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2021 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <dm.h> +#include <errno.h> +#include <log.h> +#include <miiphy.h> +#include <asm/io.h> +#include <linux/bitfield.h> + +#define ETH_PLL_STS 0x40 +#define ETH_PLL_CTL0 0x44 +#define PLL_CTL0_LOCK_DIG BIT(30) +#define PLL_CTL0_RST BIT(29) +#define PLL_CTL0_EN BIT(28) +#define PLL_CTL0_SEL BIT(23) +#define PLL_CTL0_N GENMASK(14, 10) +#define PLL_CTL0_M GENMASK(8, 0) +#define PLL_LOCK_TIMEOUT 1000000 +#define PLL_MUX_NUM_PARENT 2 +#define ETH_PLL_CTL1 0x48 +#define ETH_PLL_CTL2 0x4c +#define ETH_PLL_CTL3 0x50 +#define ETH_PLL_CTL4 0x54 +#define ETH_PLL_CTL5 0x58 +#define ETH_PLL_CTL6 0x5c +#define ETH_PLL_CTL7 0x60 + +#define ETH_PHY_CNTL0 0x80 +#define EPHY_G12A_ID 0x33010180 +#define ETH_PHY_CNTL1 0x84 +#define PHY_CNTL1_ST_MODE GENMASK(2, 0) +#define PHY_CNTL1_ST_PHYADD GENMASK(7, 3) +#define EPHY_DFLT_ADD 8 +#define PHY_CNTL1_MII_MODE GENMASK(15, 14) +#define EPHY_MODE_RMII 0x1 +#define PHY_CNTL1_CLK_EN BIT(16) +#define PHY_CNTL1_CLKFREQ BIT(17) +#define PHY_CNTL1_PHY_ENB BIT(18) +#define ETH_PHY_CNTL2 0x88 +#define PHY_CNTL2_USE_INTERNAL BIT(5) +#define PHY_CNTL2_SMI_SRC_MAC BIT(6) +#define PHY_CNTL2_RX_CLK_EPHY BIT(9) + +#define MESON_G12A_MDIO_EXTERNAL_ID 0 +#define MESON_G12A_MDIO_INTERNAL_ID 1 + +struct mdio_mux_meson_g12a_priv { + struct udevice *chip; + phys_addr_t phys; +}; + +static int meson_g12a_ephy_pll_init(struct mdio_mux_meson_g12a_priv *priv) +{ + /* Fire up the PHY PLL */ + writel(0x29c0040a, priv->phys + ETH_PLL_CTL0); + writel(0x927e0000, priv->phys + ETH_PLL_CTL1); + writel(0xac5f49e5, priv->phys + ETH_PLL_CTL2); + writel(0x00000000, priv->phys + ETH_PLL_CTL3); + writel(0x00000000, priv->phys + ETH_PLL_CTL4); + writel(0x20200000, priv->phys + ETH_PLL_CTL5); + writel(0x0000c002, priv->phys + ETH_PLL_CTL6); + writel(0x00000023, priv->phys + ETH_PLL_CTL7); + writel(0x39c0040a, priv->phys + ETH_PLL_CTL0); + writel(0x19c0040a, priv->phys + ETH_PLL_CTL0); + + return 0; +} + +static int meson_g12a_enable_internal_mdio(struct mdio_mux_meson_g12a_priv *priv) +{ + /* Initialize ephy control */ + writel(EPHY_G12A_ID, priv->phys + ETH_PHY_CNTL0); + writel(FIELD_PREP(PHY_CNTL1_ST_MODE, 3) | + FIELD_PREP(PHY_CNTL1_ST_PHYADD, EPHY_DFLT_ADD) | + FIELD_PREP(PHY_CNTL1_MII_MODE, EPHY_MODE_RMII) | + PHY_CNTL1_CLK_EN | + PHY_CNTL1_CLKFREQ | + PHY_CNTL1_PHY_ENB, + priv->phys + ETH_PHY_CNTL1); + writel(PHY_CNTL2_USE_INTERNAL | + PHY_CNTL2_SMI_SRC_MAC | + PHY_CNTL2_RX_CLK_EPHY, + priv->phys + ETH_PHY_CNTL2); + + return 0; +} + +static int meson_g12a_enable_external_mdio(struct mdio_mux_meson_g12a_priv *priv) +{ + /* Reset the mdio bus mux */ + writel(0x0, priv->phys + ETH_PHY_CNTL2); + + return 0; +} + +static int mdio_mux_meson_g12a_select(struct udevice *mux, int cur, int sel) +{ + struct mdio_mux_meson_g12a_priv *priv = dev_get_priv(mux); + + debug("%s: %x -> %x\n", __func__, (u32)cur, (u32)sel); + + /* if last selection didn't change we're good to go */ + if (cur == sel) + return 0; + + switch (sel) { + case MESON_G12A_MDIO_EXTERNAL_ID: + return meson_g12a_enable_external_mdio(priv); + case MESON_G12A_MDIO_INTERNAL_ID: + return meson_g12a_enable_internal_mdio(priv); + default: + return -EINVAL; + } + + return 0; +} + +static const struct mdio_mux_ops mdio_mux_meson_g12a_ops = { + .select = mdio_mux_meson_g12a_select, +}; + +static int mdio_mux_meson_g12a_probe(struct udevice *dev) +{ + struct mdio_mux_meson_g12a_priv *priv = dev_get_priv(dev); + + priv->phys = dev_read_addr(dev); + + meson_g12a_ephy_pll_init(priv); + + return 0; +} + +static const struct udevice_id mdio_mux_meson_g12a_ids[] = { + { .compatible = "amlogic,g12a-mdio-mux" }, + { } +}; + +U_BOOT_DRIVER(mdio_mux_meson_g12a) = { + .name = "mdio_mux_meson_g12a", + .id = UCLASS_MDIO_MUX, + .of_match = mdio_mux_meson_g12a_ids, + .probe = mdio_mux_meson_g12a_probe, + .ops = &mdio_mux_meson_g12a_ops, + .priv_auto = sizeof(struct mdio_mux_meson_g12a_priv), +}; diff --git a/drivers/net/mdio_mux_mmioreg.c b/drivers/net/mdio_mux_mmioreg.c new file mode 100644 index 0000000000..e1a23e40a2 --- /dev/null +++ b/drivers/net/mdio_mux_mmioreg.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2021 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * Based on linux/drivers/net/phy/mdio-mux-mmioreg.c : + * Copyright 2012 Freescale Semiconductor, Inc. + */ + +#include <dm.h> +#include <errno.h> +#include <log.h> +#include <miiphy.h> +#include <linux/io.h> + +struct mdio_mux_mmioreg_priv { + struct udevice *chip; + phys_addr_t phys; + unsigned int iosize; + unsigned int mask; +}; + +static int mdio_mux_mmioreg_select(struct udevice *mux, int cur, int sel) +{ + struct mdio_mux_mmioreg_priv *priv = dev_get_priv(mux); + + debug("%s: %x -> %x\n", __func__, (u32)cur, (u32)sel); + + /* if last selection didn't change we're good to go */ + if (cur == sel) + return 0; + + switch (priv->iosize) { + case sizeof(u8): { + u8 x, y; + + x = ioread8((void *)priv->phys); + y = (x & ~priv->mask) | (u32)sel; + if (x != y) { + iowrite8((x & ~priv->mask) | sel, (void *)priv->phys); + debug("%s: %02x -> %02x\n", __func__, x, y); + } + + break; + } + case sizeof(u16): { + u16 x, y; + + x = ioread16((void *)priv->phys); + y = (x & ~priv->mask) | (u32)sel; + if (x != y) { + iowrite16((x & ~priv->mask) | sel, (void *)priv->phys); + debug("%s: %04x -> %04x\n", __func__, x, y); + } + + break; + } + case sizeof(u32): { + u32 x, y; + + x = ioread32((void *)priv->phys); + y = (x & ~priv->mask) | (u32)sel; + if (x != y) { + iowrite32((x & ~priv->mask) | sel, (void *)priv->phys); + debug("%s: %08x -> %08x\n", __func__, x, y); + } + + break; + } + } + + return 0; +} + +static const struct mdio_mux_ops mdio_mux_mmioreg_ops = { + .select = mdio_mux_mmioreg_select, +}; + +static int mdio_mux_mmioreg_probe(struct udevice *dev) +{ + struct mdio_mux_mmioreg_priv *priv = dev_get_priv(dev); + phys_addr_t reg_base, reg_size; + u32 reg_mask; + int err; + + reg_base = ofnode_get_addr_size_index(dev_ofnode(dev), 0, ®_size); + if (reg_base == FDT_ADDR_T_NONE) + return -EINVAL; + + if (reg_size != sizeof(u8) && + reg_size != sizeof(u16) && + reg_size != sizeof(u32)) { + printf("%s: only 8/16/32-bit registers are supported\n", __func__); + return -EINVAL; + } + + err = dev_read_u32(dev, "mux-mask", ®_mask); + if (err) { + debug("%s: error reading mux-mask property\n", __func__); + return err; + } + + if (reg_mask >= BIT(reg_size * 8)) { + printf("%s: mask doesn't fix in register width\n", __func__); + return -EINVAL; + } + + priv->phys = reg_base; + priv->iosize = reg_size; + priv->mask = reg_mask; + + debug("%s: %llx@%lld / %x\n", __func__, reg_base, reg_size, reg_mask); + + return 0; +} + +static const struct udevice_id mdio_mux_mmioreg_ids[] = { + { .compatible = "mdio-mux-mmioreg" }, + { } +}; + +U_BOOT_DRIVER(mdio_mux_mmioreg) = { + .name = "mdio_mux_mmioreg", + .id = UCLASS_MDIO_MUX, + .of_match = mdio_mux_mmioreg_ids, + .probe = mdio_mux_mmioreg_probe, + .ops = &mdio_mux_mmioreg_ops, + .priv_auto = sizeof(struct mdio_mux_mmioreg_priv), +}; |