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-rw-r--r--arch/arm/dts/stm32mp15-pinctrl.dtsi263
-rw-r--r--arch/arm/dts/stm32mp151.dtsi4
-rw-r--r--arch/arm/dts/stm32mp157a-dk1.dts2
-rw-r--r--arch/arm/dts/stm32mp157c-dk2.dts11
-rw-r--r--arch/arm/dts/stm32mp157c-ed1.dts4
-rw-r--r--arch/arm/dts/stm32mp157c-ev1.dts15
-rw-r--r--arch/arm/dts/stm32mp15xx-dkx.dtsi38
-rw-r--r--drivers/gpio/stm32_gpio.c15
-rw-r--r--drivers/mailbox/stm32-ipcc.c9
-rw-r--r--drivers/pinctrl/pinctrl_stm32.c48
-rw-r--r--drivers/video/stm32/stm32_dsi.c3
-rw-r--r--drivers/video/stm32/stm32_ltdc.c3
12 files changed, 360 insertions, 55 deletions
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index e9525b5d06..154832983c 100644
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
@@ -1573,6 +1573,20 @@
};
};
+ spi4_pins_a: spi4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
+ <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
+ bias-disable;
+ };
+ };
+
stusb1600_pins_a: stusb1600-0 {
pins {
pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
@@ -1580,6 +1594,133 @@
};
};
+ uart4_pins_a: uart4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_idle_pins_a: uart4-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_sleep_pins_a: uart4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
+ <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
+ };
+ };
+
+ uart4_pins_b: uart4-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_pins_c: uart4-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart7_pins_a: uart7-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */
+ <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */
+ <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */
+ bias-disable;
+ };
+ };
+
+ uart7_pins_b: uart7-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
+ bias-disable;
+ };
+ };
+
+ uart7_pins_c: uart7-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
+ bias-disable;
+ };
+ };
+
+ uart7_idle_pins_c: uart7-idle-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
+ bias-disable;
+ };
+ };
+
+ uart7_sleep_pins_c: uart7-sleep-2 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */
+ <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */
+ };
+ };
+
+ uart8_pins_a: uart8-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
+ bias-disable;
+ };
+ };
+
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
@@ -1628,6 +1769,42 @@
};
};
+ usart2_pins_c: usart2-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
+ <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart2_idle_pins_c: usart2-idle-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
+ <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_sleep_pins_c: usart2-sleep-2 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
+ <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
+ <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ };
+
usart3_pins_a: usart3-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
@@ -1641,6 +1818,78 @@
};
};
+ usart3_pins_b: usart3-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
+ <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart3_idle_pins_b: usart3-idle-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
+ <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
+ bias-disable;
+ };
+ };
+
+ usart3_sleep_pins_b: usart3-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
+ <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */
+ <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
+ };
+ };
+
+ usart3_pins_c: usart3-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
+ <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart3_idle_pins_c: usart3-idle-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
+ <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
+ bias-disable;
+ };
+ };
+
+ usart3_sleep_pins_c: usart3-sleep-2 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
+ <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */
+ <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
+ };
+ };
+
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
@@ -1782,18 +2031,4 @@
bias-disable;
};
};
-
- spi4_pins_a: spi4-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
- <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
- bias-disable;
- };
- };
};
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index 39d9e545ed..206d3d3c78 100644
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -1153,7 +1153,7 @@
};
pwr_mcu: pwr_mcu@50001014 {
- compatible = "syscon";
+ compatible = "st,stm32mp151-pwr-mcu", "syscon";
reg = <0x50001014 0x4>;
};
@@ -1372,6 +1372,8 @@
dma-names = "tx", "rx";
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index d03d4cd260..4c8be9c8eb 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -18,6 +18,8 @@
aliases {
ethernet0 = &ethernet0;
serial0 = &uart4;
+ serial1 = &usart3;
+ serial2 = &uart7;
};
chosen {
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
index 9a8a26710a..045636555d 100644
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/dts/stm32mp157c-dk2.dts
@@ -19,6 +19,9 @@
aliases {
ethernet0 = &ethernet0;
serial0 = &uart4;
+ serial1 = &usart3;
+ serial2 = &uart7;
+ serial3 = &usart2;
};
chosen {
@@ -84,3 +87,11 @@
};
};
};
+
+&usart2 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart2_pins_c>;
+ pinctrl-1 = <&usart2_sleep_pins_c>;
+ pinctrl-2 = <&usart2_idle_pins_c>;
+ status = "disabled";
+};
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index 072d646379..dd911c9932 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -361,8 +361,10 @@
};
&uart4 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-1 = <&uart4_sleep_pins_a>;
+ pinctrl-2 = <&uart4_idle_pins_a>;
status = "okay";
};
diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
index 46f81ce92e..a55e80ce26 100644
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/dts/stm32mp157c-ev1.dts
@@ -19,6 +19,7 @@
aliases {
serial0 = &uart4;
+ serial1 = &usart3;
ethernet0 = &ethernet0;
};
@@ -343,6 +344,20 @@
};
};
+&usart3 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart3_pins_b>;
+ pinctrl-1 = <&usart3_sleep_pins_b>;
+ pinctrl-2 = <&usart3_idle_pins_b>;
+ /*
+ * HW flow control USART3_RTS is optional, and isn't default wired to
+ * the connector. SB23 needs to be soldered in order to use it, and R77
+ * (ETH_CLK) should be removed.
+ */
+ uart-has-rtscts;
+ status = "disabled";
+};
+
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi
index d660dfb74e..aa4aa83e05 100644
--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi
@@ -62,7 +62,7 @@
led {
compatible = "gpio-leds";
- blue {
+ led-blue {
label = "heartbeat";
gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@@ -391,6 +391,19 @@
};
};
+&i2c5 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_pins_a>;
+ pinctrl-1 = <&i2c5_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ clock-frequency = <400000>;
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+};
+
&i2s2 {
clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
clock-names = "pclk", "i2sclk", "x8k", "x11k";
@@ -610,20 +623,39 @@
};
&uart4 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-1 = <&uart4_sleep_pins_a>;
+ pinctrl-2 = <&uart4_idle_pins_a>;
status = "okay";
};
+&uart7 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart7_pins_c>;
+ pinctrl-1 = <&uart7_sleep_pins_c>;
+ pinctrl-2 = <&uart7_idle_pins_c>;
+ status = "disabled";
+};
+
+&usart3 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart3_pins_c>;
+ pinctrl-1 = <&usart3_sleep_pins_c>;
+ pinctrl-2 = <&usart3_idle_pins_c>;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbotg_hs {
- dr_mode = "peripheral";
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
+ usb-role-switch;
status = "okay";
};
diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c
index 5bff27f75b..473e364796 100644
--- a/drivers/gpio/stm32_gpio.c
+++ b/drivers/gpio/stm32_gpio.c
@@ -273,9 +273,12 @@ static const struct dm_gpio_ops gpio_stm32_ops = {
static int gpio_stm32_probe(struct udevice *dev)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct ofnode_phandle_args args;
+ const char *name;
struct clk clk;
fdt_addr_t addr;
- int ret;
+ int ret, i;
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
@@ -283,11 +286,6 @@ static int gpio_stm32_probe(struct udevice *dev)
priv->regs = (struct stm32_gpio_regs *)addr;
- struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct ofnode_phandle_args args;
- const char *name;
- int i;
-
name = dev_read_string(dev, "st,bank-name");
if (!name)
return -EINVAL;
@@ -297,6 +295,9 @@ static int gpio_stm32_probe(struct udevice *dev)
ret = dev_read_phandle_with_args(dev, "gpio-ranges",
NULL, 3, i, &args);
+ if (!ret && args.args_count < 3)
+ return -EINVAL;
+
if (ret == -ENOENT) {
uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
@@ -310,6 +311,8 @@ static int gpio_stm32_probe(struct udevice *dev)
ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
++i, &args);
+ if (!ret && args.args_count < 3)
+ return -EINVAL;
}
dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c
index b8bf356b4a..81a4115986 100644
--- a/drivers/mailbox/stm32-ipcc.c
+++ b/drivers/mailbox/stm32-ipcc.c
@@ -101,9 +101,8 @@ static int stm32_ipcc_probe(struct udevice *dev)
{
struct stm32_ipcc *ipcc = dev_get_priv(dev);
fdt_addr_t addr;
- const fdt32_t *cell;
struct clk clk;
- int len, ret;
+ int ret;
debug("%s(dev=%p)\n", __func__, dev);
@@ -114,14 +113,12 @@ static int stm32_ipcc_probe(struct udevice *dev)
ipcc->reg_base = (void __iomem *)addr;
/* proc_id */
- cell = dev_read_prop(dev, "st,proc_id", &len);
- if (len < sizeof(fdt32_t)) {
+ ret = dev_read_u32_index(dev, "st,proc_id", 1, &ipcc->proc_id);
+ if (ret) {
dev_dbg(dev, "Missing st,proc_id\n");
return -EINVAL;
}
- ipcc->proc_id = fdtdec_get_number(cell, 1);
-
if (ipcc->proc_id >= STM32_MAX_PROCS) {
dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
return -EINVAL;
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 71fa29a389..dbea99532c 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2020 STMicroelectronics - All Rights Reserved
+ */
+
#include <common.h>
#include <dm.h>
#include <hwspinlock.h>
@@ -13,8 +18,6 @@
#include <linux/err.h>
#include <linux/libfdt.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MAX_PINS_ONE_IP 70
#define MODE_BITS_MASK 3
#define OSPEED_MASK 3
@@ -308,7 +311,8 @@ static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
return 0;
}
-static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
+static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn,
+ ofnode node)
{
gpio_fn &= 0x00FF;
gpio_ctl->af = 0;
@@ -329,16 +333,16 @@ static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
break;
}
- gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
+ gpio_ctl->speed = ofnode_read_u32_default(node, "slew-rate", 0);
- if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
+ if (ofnode_read_bool(node, "drive-open-drain"))
gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
else
gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
- if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
+ if (ofnode_read_bool(node, "bias-pull-up"))
gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
- else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
+ else if (ofnode_read_bool(node, "bias-pull-down"))
gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
else
gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
@@ -350,32 +354,37 @@ static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
return 0;
}
-static int stm32_pinctrl_config(int offset)
+static int stm32_pinctrl_config(ofnode node)
{
u32 pin_mux[MAX_PINS_ONE_IP];
int rv, len;
+ ofnode subnode;
/*
* check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
* usart1) of pin controller phandle "pinctrl-0"
* */
- fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
+ ofnode_for_each_subnode(subnode, node) {
struct stm32_gpio_dsc gpio_dsc;
struct stm32_gpio_ctl gpio_ctl;
int i;
- len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
- "pinmux", pin_mux,
- ARRAY_SIZE(pin_mux));
+ rv = ofnode_read_size(subnode, "pinmux");
+ if (rv < 0)
+ return rv;
+ len = rv / sizeof(pin_mux[0]);
debug("%s: no of pinmux entries= %d\n", __func__, len);
- if (len < 0)
+ if (len > MAX_PINS_ONE_IP)
return -EINVAL;
+ rv = ofnode_read_u32_array(subnode, "pinmux", pin_mux, len);
+ if (rv < 0)
+ return rv;
for (i = 0; i < len; i++) {
struct gpio_desc desc;
debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
- prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
+ prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), subnode);
rv = uclass_get_device_by_seq(UCLASS_GPIO,
gpio_dsc.port,
&desc.dev);
@@ -424,19 +433,18 @@ static int stm32_pinctrl_bind(struct udevice *dev)
#if CONFIG_IS_ENABLED(PINCTRL_FULL)
static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
- return stm32_pinctrl_config(dev_of_offset(config));
+ return stm32_pinctrl_config(dev_ofnode(config));
}
#else /* PINCTRL_FULL */
static int stm32_pinctrl_set_state_simple(struct udevice *dev,
struct udevice *periph)
{
- const void *fdt = gd->fdt_blob;
const fdt32_t *list;
uint32_t phandle;
- int config_node;
+ ofnode config_node;
int size, i, ret;
- list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
+ list = ofnode_get_property(dev_ofnode(periph), "pinctrl-0", &size);
if (!list)
return -EINVAL;
@@ -446,8 +454,8 @@ static int stm32_pinctrl_set_state_simple(struct udevice *dev,
for (i = 0; i < size; i++) {
phandle = fdt32_to_cpu(*list++);
- config_node = fdt_node_offset_by_phandle(fdt, phandle);
- if (config_node < 0) {
+ config_node = ofnode_get_by_phandle(phandle);
+ if (!ofnode_valid(config_node)) {
pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
return -EINVAL;
}
diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
index 283151398b..9d5abacc2b 100644
--- a/drivers/video/stm32/stm32_dsi.c
+++ b/drivers/video/stm32/stm32_dsi.c
@@ -359,8 +359,7 @@ static int stm32_dsi_attach(struct udevice *dev)
ret = panel_get_display_timing(priv->panel, &timings);
if (ret) {
- ret = fdtdec_decode_display_timing(gd->fdt_blob,
- dev_of_offset(priv->panel),
+ ret = ofnode_decode_display_timing(dev_ofnode(priv->panel),
0, &timings);
if (ret) {
dev_err(dev, "decode display timing error %d\n", ret);
diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index 2f3427a32e..7fff735930 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -366,8 +366,7 @@ static int stm32_ltdc_probe(struct udevice *dev)
ret = panel_get_display_timing(panel, &timings);
if (ret) {
- ret = fdtdec_decode_display_timing(gd->fdt_blob,
- dev_of_offset(panel),
+ ret = ofnode_decode_display_timing(dev_ofnode(panel),
0, &timings);
if (ret) {
dev_err(dev, "decode display timing error %d\n", ret);
generated by cgit (git 2.34.1) at 2024-06-14 17:30:58 +0000