diff options
40 files changed, 1 insertions, 4142 deletions
diff --git a/.travis.yml b/.travis.yml index 7e90bc9b36..7b0eb6e4f6 100644 --- a/.travis.yml +++ b/.travis.yml @@ -157,8 +157,6 @@ matrix: - env: - BUILDMAN="atmel" - env: - - BUILDMAN="aries" - - env: BUILDMAN="boundary engicam toradex" - env: - JOB="Freescale ARM32" @@ -192,7 +190,7 @@ matrix: - BUILDMAN="sun50i" - env: - JOB="Catch-all ARM" - BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,aries,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,pxa,rockchip,toradex,socfpga,k2,xilinx" + BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,pxa,rockchip,toradex,socfpga,k2,xilinx" - env: - BUILDMAN="sandbox x86" TOOLCHAIN="x86_64" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index baad87d4d7..64f6d21c3c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -189,7 +189,6 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_is1.dtb \ - socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_dbm_soc1.dtb \ socfpga_cyclone5_de0_nano_soc.dtb \ @@ -511,9 +510,6 @@ dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \ dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \ at91-sama5d3_xplained.dtb -dtb-$(CONFIG_TARGET_MA5D4EK) += \ - at91-sama5d4_ma5d4evk.dts.dtb - dtb-$(CONFIG_TARGET_SAMA5D4EK) += \ at91-sama5d4ek.dtb diff --git a/arch/arm/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/dts/at91-sama5d4_ma5d4.dtsi deleted file mode 100644 index d3e79fbf19..0000000000 --- a/arch/arm/dts/at91-sama5d4_ma5d4.dtsi +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (C) 2015 Marek Vasut <marex@denx.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "sama5d4.dtsi" - -/ { - model = "Aries/DENX MA5D4"; - compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5"; - - memory { - reg = <0x20000000 0x10000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <12000000>; - }; - - clk20m: clk20m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <20000000>; - clock-output-names = "clk20m"; - }; - }; - - ahb { - apb { - mmc0: mmc@f8000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; - vmmc-supply = <&vcc_mmc0_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <8>; - broken-cd; - }; - }; - - spi0: spi@f8010000 { - cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; - status = "okay"; - - m25p80@0 { - compatible = "atmel,at25df321a"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - }; - - i2c0: i2c@f8014000 { - status = "okay"; - }; - - spi1: spi@fc018000 { - cs-gpios = <&pioB 22 0>, <&pioB 23 0>, <0>, <0>; - status = "okay"; - - can0: can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk20m>; - interrupt-parent = <&pioE>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; - spi-max-frequency = <10000000>; - }; - - can1: can@1 { - compatible = "microchip,mcp2515"; - reg = <1>; - clocks = <&clk20m>; - interrupt-parent = <&pioE>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - spi-max-frequency = <10000000>; - }; - }; - - tcb2: timer@fc024000 { - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>; - }; - - timer@1 { - compatible = "atmel,tcb-timer"; - reg = <1>; - }; - }; - - adc0: adc@fc034000 { - pinctrl-names = "default"; - pinctrl-0 = < - /* external trigger conflicts with USBA_VBUS */ - &pinctrl_adc0_ad0 - &pinctrl_adc0_ad1 - &pinctrl_adc0_ad2 - &pinctrl_adc0_ad3 - &pinctrl_adc0_ad4 - >; - atmel,adc-vref = <3300>; - status = "okay"; - }; - - watchdog@fc068640 { - status = "okay"; - }; - }; - }; - - vcc_3v3_reg: fixedregulator_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC 3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_mmc0_reg: fixedregulator_mmc0 { - compatible = "regulator-fixed"; - gpio = <&pioE 15 GPIO_ACTIVE_HIGH>; - regulator-name = "RST_n MCI0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_reg>; - regulator-boot-on; - }; -}; diff --git a/arch/arm/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/dts/at91-sama5d4_ma5d4evk.dts deleted file mode 100644 index f65a67b751..0000000000 --- a/arch/arm/dts/at91-sama5d4_ma5d4evk.dts +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (C) 2015 Marek Vasut <marex@denx.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "at91-sama5d4_ma5d4.dtsi" - -/ { - model = "Aries/DENX MA5D4EVK"; - compatible = "aries,ma5d4evk", "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5"; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - ahb { - apb { - hlcdc: hlcdc@f0000000 { - status = "okay"; - - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - - port@0 { - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; - - }; - - macb0: ethernet@f8020000 { - phy-mode = "rmii"; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - usart0: serial@f802c000 { - status = "okay"; - }; - - usart1: serial@f8030000 { - status = "okay"; - }; - - mmc1: mmc@fc000000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; - vmmc-supply = <&vcc_mmc1_reg>; - vqmmc-supply = <&vcc_3v3_reg>; - status = "okay"; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioE 5 0>; - }; - }; - - adc0: adc@fc034000 { - atmel,adc-ts-wires = <4>; - atmel,adc-ts-pressure-threshold = <10000>; - }; - - - pinctrl@fc06a000 { - board { - pinctrl_mmc1_cd: mmc1_cd { - atmel,pins = <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; - }; - pinctrl_usba_vbus: usba_vbus { - atmel,pins = - <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; - }; - }; - }; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - status = "okay"; - - user1 { - label = "user1"; - gpios = <&pioD 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "user2"; - gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - user3 { - label = "user3"; - gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - panel: panel { - /* Actually Ampire 800480R2 */ - compatible = "foxlink,fl500wvr00-a0t", "simple-panel"; - backlight = <&backlight>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - panel_input: endpoint@0 { - reg = <0>; - remote-endpoint = <&hlcdc_panel_output>; - }; - }; - }; - - vcc_mmc1_reg: fixedregulator_mmc1 { - compatible = "regulator-fixed"; - gpio = <&pioE 17 GPIO_ACTIVE_LOW>; - regulator-name = "VDD MCI1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_reg>; - }; -}; diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts deleted file mode 100644 index 65bec1536f..0000000000 --- a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Marek Vasut <marex@denx.de> - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Aries MCVEVK"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - aliases { - ethernet0 = &gmac0; - udc0 = &usb1; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - soc { - u-boot,dm-pre-reloc; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&mmc0 { - status = "okay"; - bus-width = <8>; - u-boot,dm-pre-reloc; -}; - -&usb1 { - disable-over-current; - status = "okay"; -}; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 79c84a5d7b..ce6be3829a 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -197,14 +197,6 @@ config TARGET_SAMA5D4EK select BOARD_EARLY_INIT_F select BOARD_LATE_INIT -config TARGET_MA5D4EVK - bool "Aries MA5D4EVK Evaluation Kit" - select SAMA5D4 - select SUPPORT_SPL - select DM - select DM_SPI - select SPI - config TARGET_MEESC bool "Support meesc" select AT91SAM9263 @@ -263,7 +255,6 @@ endchoice config SYS_SOC default "at91" -source "board/aries/ma5d4evk/Kconfig" source "board/atmel/at91rm9200ek/Kconfig" source "board/atmel/at91sam9260ek/Kconfig" source "board/atmel/at91sam9261ek/Kconfig" diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig index 100257b8e4..3654670442 100644 --- a/arch/arm/mach-imx/mx5/Kconfig +++ b/arch/arm/mach-imx/mx5/Kconfig @@ -29,11 +29,6 @@ config TARGET_KP_IMX53 select DM_GPIO select DM_PMIC -config TARGET_M53EVK - bool "Support m53evk" - select MX53 - select SUPPORT_SPL - config TARGET_MX51EVK bool "Support mx51evk" select BOARD_LATE_INIT @@ -83,7 +78,6 @@ endchoice config SYS_SOC default "mx5" -source "board/aries/m53evk/Kconfig" source "board/beckhoff/mx53cx9020/Kconfig" source "board/freescale/mx51evk/Kconfig" source "board/freescale/mx53ard/Kconfig" diff --git a/arch/arm/mach-imx/mx5/Makefile b/arch/arm/mach-imx/mx5/Makefile index 1fc9c96aaa..40d1998637 100644 --- a/arch/arm/mach-imx/mx5/Makefile +++ b/arch/arm/mach-imx/mx5/Makefile @@ -9,6 +9,5 @@ obj-y := soc.o clock.o obj-y += lowlevel_init.o # common files for mx53 dram initialization -obj-$(CONFIG_TARGET_M53EVK) += mx53_dram.o obj-$(CONFIG_TARGET_MX53CX9020) += mx53_dram.o obj-$(CONFIG_TARGET_MX53LOCO) += mx53_dram.o diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index 684d49e5db..68072d5a1f 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -50,9 +50,6 @@ config TARGET_APX4DEVKIT config TARGET_BG0900 bool "Support bg0900" -config TARGET_M28EVK - bool "Support m28evk" - config TARGET_MX28EVK bool "Support mx28evk" select BOARD_EARLY_INIT_F @@ -68,7 +65,6 @@ endchoice config SYS_SOC default "mxs" -source "board/aries/m28evk/Kconfig" source "board/bluegiga/apx4devkit/Kconfig" source "board/freescale/mx28evk/Kconfig" source "board/ppcag/bg0900/Kconfig" diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index b8fc81b20c..30b475254c 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -36,10 +36,6 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK bool "Altera SOCFPGA SoCDK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 -config TARGET_SOCFPGA_ARIES_MCVEVK - bool "Aries MCVEVK (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 - config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 bool "Devboards DBM-SoC1 (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -88,7 +84,6 @@ config SYS_BOARD default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "is1" if TARGET_SOCFPGA_IS1 - default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 @@ -98,7 +93,6 @@ config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK - default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA @@ -119,7 +113,6 @@ config SYS_CONFIG_NAME default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "socfpga_is1" if TARGET_SOCFPGA_IS1 - default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 diff --git a/board/aries/m28evk/Kconfig b/board/aries/m28evk/Kconfig deleted file mode 100644 index ab5577cf74..0000000000 --- a/board/aries/m28evk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M28EVK - -config SYS_BOARD - default "m28evk" - -config SYS_VENDOR - default "aries" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "m28evk" - -endif diff --git a/board/aries/m28evk/MAINTAINERS b/board/aries/m28evk/MAINTAINERS deleted file mode 100644 index aad6313dbe..0000000000 --- a/board/aries/m28evk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -M28EVK BOARD -#M: Marek Vasut <marek.vasut@gmail.com> -S: Orphan (since 2017-07) -F: board/aries/m28evk/ -F: include/configs/m28evk.h -F: configs/m28evk_defconfig diff --git a/board/aries/m28evk/Makefile b/board/aries/m28evk/Makefile deleted file mode 100644 index fc642e0836..0000000000 --- a/board/aries/m28evk/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := m28evk.o -else -obj-y := spl_boot.o -endif diff --git a/board/aries/m28evk/README b/board/aries/m28evk/README deleted file mode 100644 index 9f0d995452..0000000000 --- a/board/aries/m28evk/README +++ /dev/null @@ -1,13 +0,0 @@ -Aries M28EVK -============ - -Files of the M28/M28EVK port ----------------------------- - -arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28 -arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28 -board/aries/m28evk/ - M28EVK board specific files -include/configs/m28evk.h - M28EVK configuration file - -Follow the instructions from doc/README.mxs to generate a bootable SD card or to -boot from NAND flash. diff --git a/board/aries/m28evk/m28evk.c b/board/aries/m28evk/m28evk.c deleted file mode 100644 index ba8cc90217..0000000000 --- a/board/aries/m28evk/m28evk.c +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Aries M28 module - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <linux/mii.h> -#include <miiphy.h> -#include <netdev.h> -#include <errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Functions - */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - /* IO1 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK1, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - /* SSP2 clock at 160MHz */ - mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); - -#ifdef CONFIG_CMD_USB - mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); - mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 | - MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP); - gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0); - - mxs_iomux_setup_pad(MX28_PAD_AUART3_RX__GPIO_3_12 | - MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP); - gpio_direction_output(MX28_PAD_AUART3_RX__GPIO_3_12, 0); -#endif - - return 0; -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -#ifdef CONFIG_CMD_MMC -static int m28_mmc_wp(int id) -{ - if (id != 0) { - printf("MXS MMC: Invalid card selected (card id = %d)\n", id); - return 1; - } - - return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10); -} - -int board_mmc_init(bd_t *bis) -{ - /* Configure WP as input. */ - gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10); - /* Turn on the power to the card. */ - gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); - - return mxsmmc_initialize(bis, 0, m28_mmc_wp, NULL); -} -#endif - -#ifdef CONFIG_CMD_NET - -#define MII_OPMODE_STRAP_OVERRIDE 0x16 -#define MII_PHY_CTRL1 0x1e -#define MII_PHY_CTRL2 0x1f - -int fecmxc_mii_postcall(int phy) -{ -#if defined(CONFIG_ARIES_M28_V11) || defined(CONFIG_ARIES_M28_V10) - /* KZ8031 PHY on old boards. */ - const uint32_t freq = 0x0080; -#else - /* KZ8021 PHY on new boards. */ - const uint32_t freq = 0x0000; -#endif - - miiphy_write("FEC1", phy, MII_BMCR, 0x9000); - miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202); - if (phy == 3) - miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8100 | freq); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - struct eth_device *dev; - int ret; - - ret = cpu_eth_init(bis); - if (ret) - return ret; - - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, - CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, - CLKCTRL_ENET_TIME_SEL_RMII_CLK); - -#if !defined(CONFIG_ARIES_M28_V11) && !defined(CONFIG_ARIES_M28_V10) - /* Reset the new PHY */ - gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0); - udelay(10000); - gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1); - udelay(10000); -#endif - - ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); - if (ret) { - printf("FEC MXS: Unable to init FEC0\n"); - return ret; - } - - ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE); - if (ret) { - printf("FEC MXS: Unable to init FEC1\n"); - return ret; - } - - dev = eth_get_dev_by_name("FEC0"); - if (!dev) { - printf("FEC MXS: Unable to get FEC0 device entry\n"); - return -EINVAL; - } - - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - printf("FEC MXS: Unable to register FEC0 mii postcall\n"); - return ret; - } - - dev = eth_get_dev_by_name("FEC1"); - if (!dev) { - printf("FEC MXS: Unable to get FEC1 device entry\n"); - return -EINVAL; - } - - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - printf("FEC MXS: Unable to register FEC1 mii postcall\n"); - return ret; - } - - return ret; -} - -#endif diff --git a/board/aries/m28evk/spl_boot.c b/board/aries/m28evk/spl_boot.c deleted file mode 100644 index ddec8dca6e..0000000000 --- a/board/aries/m28evk/spl_boot.c +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * ARIES M28 Boot setup - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_GPMI (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* LED */ - MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED, - - /* framebuffer */ - MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD, - MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, - - /* UART1 */ -#ifdef CONFIG_ARIES_M28_V10 - MX28_PAD_AUART0_CTS__DUART_RX, - MX28_PAD_AUART0_RTS__DUART_TX, -#else - MX28_PAD_PWM0__DUART_RX, - MX28_PAD_PWM1__DUART_TX, -#endif - MX28_PAD_AUART0_TX__DUART_RTS, - MX28_PAD_AUART0_RX__DUART_CTS, - - /* UART2 */ - MX28_PAD_AUART1_RX__AUART1_RX, - MX28_PAD_AUART1_TX__AUART1_TX, - MX28_PAD_AUART1_RTS__AUART1_RTS, - MX28_PAD_AUART1_CTS__AUART1_CTS, - - /* CAN */ - MX28_PAD_GPMI_RDY2__CAN0_TX, - MX28_PAD_GPMI_RDY3__CAN0_RX, - - /* TSC2007 */ - MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC, - - /* MMC0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), - MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0 | - (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), /* Power */ - MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP */ - - /* GPMI NAND */ - MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDN__GPMI_RDN | - (MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP), - MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, - - /* FEC Ethernet */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, - - MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, -#if !defined(CONFIG_ARIES_M28_V11) && !defined(CONFIG_ARIES_M28_V10) - MX28_PAD_AUART2_RTS__GPIO_3_11, /* PHY reset */ -#endif - - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - - /* EMI */ - MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, - MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, - - MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - - /* SPI2 (for flash) */ - MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_SS0__SSP2_D3 | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), -}; - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} diff --git a/board/aries/m53evk/Kconfig b/board/aries/m53evk/Kconfig deleted file mode 100644 index 2d49b40912..0000000000 --- a/board/aries/m53evk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M53EVK - -config SYS_BOARD - default "m53evk" - -config SYS_VENDOR - default "aries" - -config SYS_SOC - default "mx5" - -config SYS_CONFIG_NAME - default "m53evk" - -endif diff --git a/board/aries/m53evk/MAINTAINERS b/board/aries/m53evk/MAINTAINERS deleted file mode 100644 index 73a68cf5aa..0000000000 --- a/board/aries/m53evk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -M53EVK BOARD -#M: Marek Vasut <marek.vasut@gmail.com> -S: Orphan (since 2017-07) -F: board/aries/m53evk/ -F: include/configs/m53evk.h -F: configs/m53evk_defconfig diff --git a/board/aries/m53evk/Makefile b/board/aries/m53evk/Makefile deleted file mode 100644 index c0a400416a..0000000000 --- a/board/aries/m53evk/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Aries M53EVK -# Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> - -obj-y := m53evk.o diff --git a/board/aries/m53evk/imximage.cfg b/board/aries/m53evk/imximage.cfg deleted file mode 100644 index 91649ec5d8..0000000000 --- a/board/aries/m53evk/imximage.cfg +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Aries M53 DRAM init values - * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ -#include <asm/mach-imx/imximage.cfg> - -/* image version */ -IMAGE_VERSION 2 - - -/* Boot Offset 0x400, valid for both SD and NAND boot. */ -BOOT_OFFSET FLASH_OFFSET_STANDARD - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */ -DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */ -DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */ -DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */ - -DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */ -DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */ -DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */ - -DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */ -DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */ -DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */ - -DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */ -DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */ -DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */ - -DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */ -DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */ -DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */ - -DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */ -DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */ - -DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */ -DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */ -DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */ -DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */ - -DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */ -DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */ - -/* ESDCTL */ -DATA 4 0x63fd9088 0x32383535 -DATA 4 0x63fd9090 0x40383538 -DATA 4 0x63fd907c 0x0136014d -DATA 4 0x63fd9080 0x01510141 - -DATA 4 0x63fd9018 0x00011740 -DATA 4 0x63fd9000 0xc3190000 -DATA 4 0x63fd900c 0x555952e3 -DATA 4 0x63fd9010 0xb68e8b63 -DATA 4 0x63fd9014 0x01ff00db -DATA 4 0x63fd902c 0x000026d2 -DATA 4 0x63fd9030 0x009f0e21 -DATA 4 0x63fd9008 0x12273030 -DATA 4 0x63fd9004 0x0002002d -DATA 4 0x63fd901c 0x00008032 -DATA 4 0x63fd901c 0x00008033 -DATA 4 0x63fd901c 0x00028031 -DATA 4 0x63fd901c 0x092080b0 -DATA 4 0x63fd901c 0x04008040 -DATA 4 0x63fd901c 0x0000803a -DATA 4 0x63fd901c 0x0000803b -DATA 4 0x63fd901c 0x00028039 -DATA 4 0x63fd901c 0x09208138 -DATA 4 0x63fd901c 0x04008048 -DATA 4 0x63fd9020 0x00001800 -DATA 4 0x63fd9040 0x04b80003 -DATA 4 0x63fd9058 0x00022227 -DATA 4 0x63fd901c 0x00000000 diff --git a/board/aries/m53evk/m53evk.c b/board/aries/m53evk/m53evk.c deleted file mode 100644 index 77ba69c705..0000000000 --- a/board/aries/m53evk/m53evk.c +++ /dev/null @@ -1,364 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Aries M53 module - * - * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux-mx53.h> -#include <asm/mach-imx/mx5_video.h> -#include <asm/spl.h> -#include <linux/errno.h> -#include <netdev.h> -#include <i2c.h> -#include <mmc.h> -#include <spl.h> -#include <fsl_esdhc.h> -#include <asm/gpio.h> -#include <usb/ehci-ci.h> -#include <linux/fb.h> -#include <ipu_pixfmt.h> - -/* Special MXCFB sync flags are here. */ -#include "../drivers/video/mxcfb.h" - -DECLARE_GLOBAL_DATA_PTR; - -static void setup_iomux_uart(void) -{ - static const iomux_v3_cfg_t uart_pads[] = { - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - }; - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); -} - -#ifdef CONFIG_USB_EHCI_MX5 -int board_ehci_hcd_init(int port) -{ - if (port == 0) { - /* USB OTG PWRON */ - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH)); - gpio_direction_output(IMX_GPIO_NR(1, 4), 0); - - /* USB OTG Over Current */ - imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13); - } else if (port == 1) { - /* USB Host PWRON */ - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, - PAD_CTL_PKE | PAD_CTL_DSE_HIGH)); - gpio_direction_output(IMX_GPIO_NR(1, 2), 0); - - /* USB Host Over Current */ - imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC); - } - - return 0; -} -#endif - -static void setup_iomux_fec(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - /* MDIO pads */ - NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), - NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), - - /* FEC 0 pads */ - NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), - - /* FEC 1 pads */ - NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS, - PAD_CTL_HYS | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH), - }; - - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} - -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg = { - MMC_SDHC1_BASE_ADDR, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1); - gpio_direction_input(IMX_GPIO_NR(1, 1)); - - return !gpio_get_value(IMX_GPIO_NR(1, 1)); -} - -#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH) - -int board_mmc_init(bd_t *bis) -{ - static const iomux_v3_cfg_t sd1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), - MX53_PAD_EIM_DA13__GPIO3_13, - - MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */ - }; - - esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); - - /* GPIO 2_31 is SD power */ - gpio_direction_output(IMX_GPIO_NR(2, 31), 0); - - return fsl_esdhc_initialize(bis, &esdhc_cfg); -} -#endif - -#ifdef CONFIG_VIDEO -static struct fb_videomode const ampire_wvga = { - .name = "Ampire", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 29851, /* picosecond (33.5 MHz) */ - .left_margin = 89, - .right_margin = 164, - .upper_margin = 23, - .lower_margin = 10, - .hsync_len = 10, - .vsync_len = 10, - .sync = FB_SYNC_CLK_LAT_FALL, -}; - -int board_video_skip(void) -{ - int ret; - ret = ipuv3_fb_init(&ire_wvga, 1, IPU_PIX_FMT_RGB666); - if (ret) - printf("Ampire LCD cannot be configured: %d\n", ret); - return ret; -} -#endif - -#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) - -static void setup_iomux_i2c(void) -{ - static const iomux_v3_cfg_t i2c_pads[] = { - NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); -} - -static void setup_iomux_video(void) -{ - static const iomux_v3_cfg_t lcd_pads[] = { - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0, - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1, - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2, - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3, - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4, - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5, - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6, - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7, - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8, - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9, - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10, - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11, - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12, - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13, - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14, - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15, - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16, - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17, - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18, - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19, - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20, - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21, - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22, - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23, - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK, - MX53_PAD_EIM_DA13__IPU_DI1_D0_CS, - MX53_PAD_EIM_DA14__IPU_DI1_D1_CS, - MX53_PAD_EIM_DA15__IPU_DI1_PIN1, - MX53_PAD_EIM_DA11__IPU_DI1_PIN2, - MX53_PAD_EIM_DA12__IPU_DI1_PIN3, - MX53_PAD_EIM_A25__IPU_DI1_PIN12, - MX53_PAD_EIM_DA10__IPU_DI1_PIN15, - }; - - imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); -} - -static void setup_iomux_nand(void) -{ - static const iomux_v3_cfg_t nand_pads[] = { - NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B, - PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B, - PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE, - PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE, - PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B, - PAD_CTL_PUS_100K_UP), - NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0, - PAD_CTL_PUS_100K_UP), - NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0, - PAD_CTL_DSE_HIGH), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE), - }; - - imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); -} - -static void m53_set_clock(void) -{ - int ret; - const uint32_t ref_clk = MXC_HCLK; - const uint32_t dramclk = 400; - uint32_t cpuclk; - - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, - PAD_CTL_DSE_HIGH | PAD_CTL_PKE)); - gpio_direction_input(IMX_GPIO_NR(4, 0)); - - /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */ - cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800; - - ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); - if (ret) - printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk); - - ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); - if (ret) { - printf("CPU: Switch peripheral clock to %dMHz failed\n", - dramclk); - } - - ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); - if (ret) - printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk); -} - -static void m53_set_nand(void) -{ - u32 i; - - /* NAND flash is muxed on ATA pins */ - setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK); - - /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */ - for (i = 0x4; i < 0x94; i += 0x18) { - clrbits_le32(WEIM_BASE_ADDR + i, - WEIM_GCR2_MUX16_BYP_GRANT_MASK); - } - - mxc_set_clock(0, 33, MXC_NFC_CLK); - enable_nfc_clk(1); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - setup_iomux_fec(); - setup_iomux_i2c(); - setup_iomux_nand(); - setup_iomux_video(); - - m53_set_clock(); - - mxc_set_sata_internal_clock(); - - /* NAND clock @ 33MHz */ - m53_set_nand(); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -int checkboard(void) -{ - puts("Board: Aries M53EVK\n"); - - return 0; -} - -/* - * NAND SPL - */ -#ifdef CONFIG_SPL_BUILD -void spl_board_init(void) -{ - setup_iomux_nand(); - m53_set_clock(); - m53_set_nand(); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_NAND; -} -#endif diff --git a/board/aries/ma5d4evk/Kconfig b/board/aries/ma5d4evk/Kconfig deleted file mode 100644 index 56b4f4a1a8..0000000000 --- a/board/aries/ma5d4evk/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MA5D4EVK - -config SYS_BOARD - default "ma5d4evk" - -config SYS_VENDOR - default "aries" - -config SYS_CONFIG_NAME - default "ma5d4evk" - -endif diff --git a/board/aries/ma5d4evk/MAINTAINERS b/board/aries/ma5d4evk/MAINTAINERS deleted file mode 100644 index a2fab52dfc..0000000000 --- a/board/aries/ma5d4evk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -Aries MA5D4EVK BOARD -#M: Marek Vasut <marek.vasut@gmail.com> -S: Orphan (since 2017-07) -F: board/aries/ma5d4evk/ -F: include/configs/ma5d4evk.h -F: configs/ma5d4evk_defconfig diff --git a/board/aries/ma5d4evk/Makefile b/board/aries/ma5d4evk/Makefile deleted file mode 100644 index 15fc2946d8..0000000000 --- a/board/aries/ma5d4evk/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2015 Marek Vasut <marex@denx.de> - -obj-y += ma5d4evk.o diff --git a/board/aries/ma5d4evk/ma5d4evk.c b/board/aries/ma5d4evk/ma5d4evk.c deleted file mode 100644 index c2b6845edc..0000000000 --- a/board/aries/ma5d4evk/ma5d4evk.c +++ /dev/null @@ -1,456 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Marek Vasut <marex@denx.de> - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> -#include <asm/arch/atmel_mpddrc.h> -#include <asm/arch/atmel_usba_udc.h> -#include <asm/arch/gpio.h> -#include <asm/arch/clk.h> -#include <asm/arch/sama5d3_smc.h> -#include <asm/arch/sama5d4.h> -#include <atmel_hlcdc.h> -#include <atmel_mci.h> -#include <lcd.h> -#include <mmc.h> -#include <net.h> -#include <netdev.h> -#include <spi.h> -#include <spi_flash.h> -#include <spl.h> -#include <version.h> - -DECLARE_GLOBAL_DATA_PTR; - -static u8 boot_mode_sf; - -/* FIXME gpio code here need to handle through DM_GPIO */ -#ifndef CONFIG_DM_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - at91_set_pio_output(AT91_PIO_PORTC, 3, 0); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - at91_set_pio_output(AT91_PIO_PORTC, 3, 1); -} - -static void ma5d4evk_spi0_hw_init(void) -{ - at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ - at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ - at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ - - at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_SPI0); -} -#endif /* CONFIG_DM_SPI */ - -#ifdef CONFIG_CMD_USB -static void ma5d4evk_usb_hw_init(void) -{ - at91_set_pio_output(AT91_PIO_PORTE, 11, 0); - at91_set_pio_output(AT91_PIO_PORTE, 14, 0); -} -#endif - -#ifdef CONFIG_LCD -vidinfo_t panel_info = { - .vl_col = 800, - .vl_row = 480, - .vl_clk = 33500000, - .vl_bpix = LCD_BPP, - .vl_tft = 1, - .vl_hsync_len = 10, - .vl_left_margin = 89, - .vl_right_margin = 164, - .vl_vsync_len = 10, - .vl_upper_margin = 23, - .vl_lower_margin = 10, - .mmio = ATMEL_BASE_LCDC, -}; - -/* No power up/down pin for the LCD pannel */ -void lcd_enable(void) { /* Empty! */ } -void lcd_disable(void) { /* Empty! */ } - -unsigned int has_lcdc(void) -{ - return 1; -} - -static void ma5d4evk_lcd_hw_init(void) -{ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 1); /* LCDPWM */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 1); /* LCDDEN */ - - at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ - - at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ - - at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ - at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_LCDC); -} - -#endif /* CONFIG_LCD */ - -#ifdef CONFIG_GENERIC_ATMEL_MCI -/* On-SoM eMMC */ -void ma5d4evk_mci0_hw_init(void) -{ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI1 CDA */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI1 DA0 */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI1 DA1 */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI1 DA2 */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI1 DA3 */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI1 DA4 */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI1 DA5 */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI1 DA6 */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI1 DA7 */ - at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI1 CLK */ - - /* - * As the mci io internal pull down is too strong, so if the io needs - * external pull up, the pull up resistor will be very small, if so - * the power consumption will increase, so disable the internal pull - * down to save the power. - */ - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0); - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_MCI0); -} - -/* On-board MicroSD slot */ -void ma5d4evk_mci1_hw_init(void) -{ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ - - /* - * As the mci io internal pull down is too strong, so if the io needs - * external pull up, the pull up resistor will be very small, if so - * the power consumption will increase, so disable the internal pull - * down to save the power. - */ - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); - - /* Deal with WP pin on the microSD slot. */ - at91_set_pio_output(AT91_PIO_PORTE, 16, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 16, 1); - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_MCI1); -} - -int board_mmc_init(bd_t *bis) -{ - int ret; - void *mci0 = (void *)ATMEL_BASE_MCI0; - void *mci1 = (void *)ATMEL_BASE_MCI1; - - /* De-assert reset on On-SoM eMMC */ - at91_set_pio_output(AT91_PIO_PORTE, 15, 1); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 15, 0); - - ret = atmel_mci_init(boot_mode_sf ? mci0 : mci1); - if (ret) /* eMMC init failed, skip it. */ - at91_set_pio_output(AT91_PIO_PORTE, 15, 0); - - /* Enable the power supply to On-board MicroSD */ - at91_set_pio_output(AT91_PIO_PORTE, 17, 0); - ret = atmel_mci_init(boot_mode_sf ? mci1 : mci0); - if (ret) /* uSD init failed, power it down. */ - at91_set_pio_output(AT91_PIO_PORTE, 17, 1); - - return 0; -} -#endif /* CONFIG_GENERIC_ATMEL_MCI */ - -#ifdef CONFIG_MACB -void ma5d4evk_macb0_hw_init(void) -{ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_GMAC0); -} -#endif - -static void ma5d4evk_serial_hw_init(void) -{ - /* USART0 */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */ - at91_periph_clk_enable(ATMEL_ID_USART0); - - /* USART1 */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */ - at91_periph_clk_enable(ATMEL_ID_USART1); -} - -int board_early_init_f(void) -{ - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - at91_periph_clk_enable(ATMEL_ID_PIOD); - at91_periph_clk_enable(ATMEL_ID_PIOE); - - /* Configure LEDs as OFF */ - at91_set_pio_output(AT91_PIO_PORTD, 28, 0); - at91_set_pio_output(AT91_PIO_PORTD, 29, 0); - at91_set_pio_output(AT91_PIO_PORTD, 30, 0); - - ma5d4evk_serial_hw_init(); - - return 0; -} - -static void board_identify(void) -{ - struct spi_flash *sf; - sf = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS, - CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE); - boot_mode_sf = (sf != NULL); -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - -#ifndef CONFIG_DM_SPI - ma5d4evk_spi0_hw_init(); -#endif -#ifdef CONFIG_GENERIC_ATMEL_MCI - ma5d4evk_mci0_hw_init(); - ma5d4evk_mci1_hw_init(); -#endif -#ifdef CONFIG_MACB - ma5d4evk_macb0_hw_init(); -#endif -#ifdef CONFIG_LCD - ma5d4evk_lcd_hw_init(); -#endif -#ifdef CONFIG_CMD_USB - ma5d4evk_usb_hw_init(); -#endif -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - at91_udp_hw_init(); -#endif - - board_identify(); - - /* Reset CAN controllers */ - at91_set_pio_output(AT91_PIO_PORTB, 21, 0); - udelay(100); - at91_set_pio_output(AT91_PIO_PORTB, 21, 1); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTB, 21, 0); - - return 0; -} - -int board_late_init(void) -{ - env_set("bootmode", boot_mode_sf ? "sf" : "emmc"); - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; - -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); -#endif - -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - usba_udc_probe(&pdata); -#ifdef CONFIG_USB_ETH_RNDIS - usb_eth_initialize(bis); -#endif -#endif - - return rc; -} - -/* SPL */ -#ifdef CONFIG_SPL_BUILD -void spl_board_init(void) -{ -#ifndef CONFIG_DM_SPI - ma5d4evk_spi0_hw_init(); -#endif -#ifdef CONFIG_GENERIC_ATMEL_MCI - ma5d4evk_mci0_hw_init(); - ma5d4evk_mci1_hw_init(); -#endif - board_identify(); -} - -void board_boot_order(u32 *spl_boot_list) -{ - spl_boot_list[0] = spl_boot_device(); - - switch (spl_boot_list[0]) { - case BOOT_DEVICE_MMC1: - case BOOT_DEVICE_MMC2: - spl_boot_list[0] = BOOT_DEVICE_MMC1; - break; - case BOOT_DEVICE_SPI: - break; - case BOOT_DEVICE_USB: - spl_boot_list[0] = BOOT_DEVICE_MMC2; - break; - } -} - -static void ddr2_conf(struct atmel_mpddrc_config *ddr2) -{ - ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); - - ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | - ATMEL_MPDDRC_CR_NR_ROW_13 | - ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | - ATMEL_MPDDRC_CR_NB_8BANKS | - ATMEL_MPDDRC_CR_NDQS_DISABLED | - ATMEL_MPDDRC_CR_UNAL_SUPPORTED); - - ddr2->rtr = 0x2b0; - - ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | - 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | - 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | - 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | - 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | - 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); - - ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | - 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | - 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | - 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); - - ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | - 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | - 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | - 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | - 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); -} - -void mem_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - struct atmel_mpddrc_config ddr2; - - ddr2_conf(&ddr2); - - /* enable MPDDR clock */ - at91_periph_clk_enable(ATMEL_ID_MPDDRC); - writel(AT91_PMC_DDR, &pmc->scer); - - /* DDRAM2 Controller initialize */ - ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); -} - -void at91_pmc_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - u32 tmp; - - tmp = AT91_PMC_PLLAR_29 | - AT91_PMC_PLLXR_PLLCOUNT(0x3f) | - AT91_PMC_PLLXR_MUL(87) | - AT91_PMC_PLLXR_DIV(1); - at91_plla_init(tmp); - - writel(0x0 << 8, &pmc->pllicpr); - - tmp = AT91_PMC_MCKR_H32MXDIV | - AT91_PMC_MCKR_PLLADIV_2 | - AT91_PMC_MCKR_MDIV_3 | - AT91_PMC_MCKR_CSS_PLLA; - at91_mck_init(tmp); -} -#endif diff --git a/board/aries/mcvevk/MAINTAINERS b/board/aries/mcvevk/MAINTAINERS deleted file mode 100644 index 0b719a154c..0000000000 --- a/board/aries/mcvevk/MAINTAINERS +++ /dev/null @@ -1,5 +0,0 @@ -Aries MCVEVK BOARD -#M: Marek Vasut <marek.vasut@gmail.com> -S: Orphan (since 2017-07) -F: include/configs/socfpga_mcvevk.h -F: configs/socfpga_mcvevk_defconfig diff --git a/board/aries/mcvevk/Makefile b/board/aries/mcvevk/Makefile deleted file mode 100644 index e1c8a6b3c7..0000000000 --- a/board/aries/mcvevk/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> - -obj-y := socfpga.o diff --git a/board/aries/mcvevk/qts/iocsr_config.h b/board/aries/mcvevk/qts/iocsr_config.h deleted file mode 100644 index e233d02b97..0000000000 --- a/board/aries/mcvevk/qts/iocsr_config.h +++ /dev/null @@ -1,659 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Altera SoCFPGA IOCSR configuration - */ - -#ifndef __SOCFPGA_IOCSR_CONFIG_H__ -#define __SOCFPGA_IOCSR_CONFIG_H__ - -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 - -const unsigned long iocsr_scan_chain0_table[] = { - 0x00000000, - 0x00000000, - 0x0FF00000, - 0xC0000000, - 0x0000003F, - 0x00008000, - 0x00000000, - 0x18060000, - 0x00000060, - 0x00000000, - 0x00000000, - 0x00004000, - 0x0C0300C0, - 0x00000000, - 0x0C000000, - 0x0000C030, - 0x0000C030, - 0x00002000, - 0x06018060, - 0x06018000, - 0x06000018, - 0x00006018, - 0x01806018, - 0x00001000, -}; - -const unsigned long iocsr_scan_chain1_table[] = { - 0x000C0300, - 0x300C0000, - 0x300000C0, - 0x000000C0, - 0x000300C0, - 0x00008000, - 0x00060180, - 0x18060000, - 0x18000000, - 0x00000060, - 0x00018060, - 0x00004000, - 0x000300C0, - 0x0C030000, - 0x0C000000, - 0x00000030, - 0x0000C030, - 0x00002000, - 0x00018060, - 0x06018000, - 0x01FE0000, - 0xF8000000, - 0x00000007, - 0x00001000, - 0x0300C030, - 0x00000000, - 0x03000000, - 0x0000000C, - 0x00000000, - 0x00000800, - 0x00006018, - 0x01806000, - 0x00000000, - 0x00000000, - 0x00001806, - 0x00000400, - 0x0000300C, - 0x00C03000, - 0x00C00000, - 0x00000003, - 0x00000C03, - 0x00000200, - 0x00001806, - 0x00601800, - 0x80600000, - 0x80000001, - 0x00000601, - 0x00000100, - 0x00001000, - 0x00300C00, - 0xC0300000, - 0xC0000000, - 0x00000300, - 0x00000080, -}; - -const unsigned long iocsr_scan_chain2_table[] = { - 0x300C0300, - 0x00000000, - 0x0FF00000, - 0x00000000, - 0x0C0300C0, - 0x00008000, - 0x00060180, - 0x00000000, - 0x18000000, - 0x00018060, - 0x06018060, - 0x00004000, - 0x200300C0, - 0x0C030000, - 0x0C000000, - 0x00000030, - 0x0000C030, - 0x00002000, - 0x00018060, - 0x00000000, - 0x06000000, - 0x00010018, - 0x01806018, - 0x00001000, - 0x0000C030, - 0x00000000, - 0x03000000, - 0x0000000C, - 0x00C0300C, - 0x00000800, -}; - -const unsigned long iocsr_scan_chain3_table[] = { - 0x0C420D80, - 0x0C3000FF, - 0x0A804001, - 0x07900000, - 0x08020000, - 0x00100000, - 0x0A800000, - 0x07900000, - 0x08020000, - 0x00100000, - 0x20430000, - 0x0C003001, - 0x00C00481, - 0x00000000, - 0x00000021, - 0x82000004, - 0x05400000, - 0x03C80000, - 0x04010000, - 0x00080000, - 0x05400000, - 0x03C80000, - 0x05400000, - 0x03C80000, - 0x90218000, - 0x86001800, - 0x00600240, - 0x80090218, - 0x00000001, - 0x40000002, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x4810C000, - 0x43000C00, - 0x00300120, - 0xC004810C, - 0x12043000, - 0x20000300, - 0x00040000, - 0x50670000, - 0x00000010, - 0x24590000, - 0x00001000, - 0xA0000034, - 0x0D000001, - 0xC0680A28, - 0x45034030, - 0x12481A01, - 0x80A280D0, - 0x34030C06, - 0x01A01450, - 0x280D0000, - 0x30C0680A, - 0x02490340, - 0xD000001A, - 0x0680A280, - 0x10040000, - 0x00200000, - 0x10040000, - 0x00200000, - 0x15000000, - 0x0F200000, - 0x15000000, - 0x0F200000, - 0x01FE0000, - 0x18000000, - 0x01800902, - 0x00240860, - 0x007F8006, - 0x00000000, - 0x0A800001, - 0x07900000, - 0x0A800000, - 0x07900000, - 0x0A800000, - 0x07900000, - 0x08020000, - 0x00100000, - 0x20430000, - 0x0C003001, - 0x00C00481, - 0x00000FF0, - 0x4810C000, - 0x80000C00, - 0x05400000, - 0x02480000, - 0x04000000, - 0x00080000, - 0x05400000, - 0x03C80000, - 0x05400000, - 0x03C80000, - 0x90218000, - 0x86001800, - 0x00600240, - 0x80090218, - 0x24086001, - 0x40000600, - 0x02A00040, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x4810C000, - 0x43000C00, - 0x00300120, - 0xC004810C, - 0x12043000, - 0x20000300, - 0x00040000, - 0x50670000, - 0x00000010, - 0x24590000, - 0x00001000, - 0xA0000034, - 0x0D000001, - 0xC0680A28, - 0x49034030, - 0x12481A02, - 0x80A280D0, - 0x34030C06, - 0x01A00040, - 0x280D0002, - 0x30C0680A, - 0x02490340, - 0xD00A281A, - 0x0680A280, - 0x10040000, - 0x00200000, - 0x10040000, - 0x00200000, - 0x15000000, - 0x0F200000, - 0x15000000, - 0x0F200000, - 0x01FE0000, - 0x18000000, - 0x01800902, - 0x00240860, - 0x007F8006, - 0x00000000, - 0x99300001, - 0x34343400, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A890, - 0xAA0D4000, - 0x01C3A800, - 0x00040100, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x01000000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x0002A000, - 0x0001E400, - 0x5506A000, - 0x00E1D400, - 0x00000000, - 0x2043090C, - 0x00003001, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA24, - 0x2A835000, - 0x0070EA00, - 0x00010040, - 0x00000200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00002000, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC0D5F80, - 0xFFFFFFFF, - 0x14F3690D, - 0x1A041414, - 0x00D00000, - 0x18864000, - 0x49247A06, - 0x9A28A3D7, - 0xF511451E, - 0x0356E388, - 0x821A0000, - 0x0000D000, - 0x05140680, - 0xD749247A, - 0x1E9A28A3, - 0x88F51145, - 0x00034EE3, - 0x00080000, - 0x00001000, - 0x00080200, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875001, - 0x00000000, - 0x00000010, - 0x0080C000, - 0x41000000, - 0x00003FC2, - 0x00820000, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A890, - 0xAA0D4000, - 0x01C3A800, - 0x00040000, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x00800000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x00020080, - 0x00000400, - 0x5506A000, - 0x00E1D400, - 0x00000000, - 0x0000090C, - 0x00000010, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA24, - 0x2A835000, - 0x0070EA00, - 0x00015000, - 0x0000F200, - 0x00000000, - 0x00000482, - 0x86120800, - 0x00600240, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC0D5F80, - 0xFFFFFFFF, - 0x14F3690D, - 0x1A041414, - 0x00D00000, - 0x18864000, - 0x49247A06, - 0xEBCF23D7, - 0xF611451E, - 0x034E9248, - 0x821A038E, - 0x0000D000, - 0x00000680, - 0xD749247A, - 0x1E9BCF23, - 0x88F61145, - 0x00034EE3, - 0x00080000, - 0x00001000, - 0x00080000, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875001, - 0x00000000, - 0x00000010, - 0x0080C000, - 0x41000000, - 0x00000002, - 0x00820004, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A890, - 0xAA0D4000, - 0x01C3A800, - 0x00040000, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x00800000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x0002A000, - 0x0001E400, - 0x5506A000, - 0x00E1D400, - 0x00000000, - 0x2043090C, - 0x00003001, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA00, - 0x00010000, - 0x00000200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00200000, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC0D5F80, - 0xFFFFFFFF, - 0x14F3690D, - 0x1A041414, - 0x00D00000, - 0x18864000, - 0x49247A06, - 0x9A28A3D7, - 0xF431451E, - 0x034E9248, - 0x821A0000, - 0x0000D000, - 0x00000680, - 0xD749247A, - 0x1E9A28A3, - 0x88F61145, - 0x000356E3, - 0x00080000, - 0x00001000, - 0x00080000, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875001, - 0x00000000, - 0x00000010, - 0x0080C000, - 0x41000000, - 0x00000002, - 0x00820004, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A800, - 0xAA0D4000, - 0x01C3A800, - 0x00040000, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x00800000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x00020000, - 0x00000400, - 0x5506A000, - 0x00E1D400, - 0x00000000, - 0x0000090C, - 0x00001000, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA00, - 0x2A835000, - 0x0070EA00, - 0x00010040, - 0x00000200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00400000, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC0D5F80, - 0xFFFFFFFF, - 0x14F1690D, - 0x1A041414, - 0x00D00000, - 0x08864000, - 0x49247A02, - 0xEBCF23DB, - 0xF431451E, - 0x0356E388, - 0x821A0000, - 0x0000D000, - 0x00000680, - 0xD749247A, - 0x1EEBCF23, - 0x88F43E79, - 0x000356A2, - 0x00080000, - 0x00001000, - 0x00080000, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875001, - 0x00000000, - 0x00000010, - 0x0080C000, - 0x41000000, - 0x00000002, - 0x00820004, - 0x00489800, - 0x801A1A1A, - 0x00000200, - 0x80000004, - 0x00000200, - 0x80000004, - 0x00000200, - 0x00000004, - 0x00000200, - 0x00000004, - 0x00040000, - 0x10000000, - 0x00000000, - 0x00004000, - 0x00010000, - 0x40002080, - 0x00000100, - 0x40000002, - 0x00000100, - 0x00000002, - 0x00000100, - 0x40000002, - 0x00000100, - 0x00000002, - 0x00020000, - 0x00000000, - 0x00000008, - 0x00000020, - 0x00008000, - 0x20001040, - 0x00000080, - 0x20000001, - 0x00000080, - 0x20000001, - 0x00000080, - 0x20000001, - 0x00000080, - 0x00000001, - 0x00010000, - 0x04000000, - 0x00FF0000, - 0x00000000, - 0x00004000, - 0x00000800, - 0xC0000001, - 0x00041419, - 0x40000000, - 0x04000816, - 0x000D0000, - 0x00006800, - 0x00000340, - 0xD000001A, - 0x06800000, - 0x00340000, - 0x0001A000, - 0x00000D00, - 0x40000068, - 0x1A000003, - 0x00D00000, - 0x00068000, - 0x00003400, - 0x000001A0, - 0x00000401, - 0x00000008, - 0x00000401, - 0x00000008, - 0x00000401, - 0x00000008, - 0x00000401, - 0x80000008, - 0x0000007F, - 0x20000000, - 0x00000000, - 0xE0000080, - 0x0000001F, - 0x00004000, -}; - - -#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/aries/mcvevk/qts/pinmux_config.h b/board/aries/mcvevk/qts/pinmux_config.h deleted file mode 100644 index 85f892ae47..0000000000 --- a/board/aries/mcvevk/qts/pinmux_config.h +++ /dev/null @@ -1,218 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Altera SoCFPGA PinMux configuration - */ - -#ifndef __SOCFPGA_PINMUX_CONFIG_H__ -#define __SOCFPGA_PINMUX_CONFIG_H__ - -const u8 sys_mgr_init_table[] = { - 3, /* EMACIO0 */ - 3, /* EMACIO1 */ - 3, /* EMACIO2 */ - 3, /* EMACIO3 */ - 3, /* EMACIO4 */ - 3, /* EMACIO5 */ - 3, /* EMACIO6 */ - 3, /* EMACIO7 */ - 3, /* EMACIO8 */ - 3, /* EMACIO9 */ - 3, /* EMACIO10 */ - 3, /* EMACIO11 */ - 3, /* EMACIO12 */ - 3, /* EMACIO13 */ - 0, /* EMACIO14 */ - 0, /* EMACIO15 */ - 0, /* EMACIO16 */ - 0, /* EMACIO17 */ - 0, /* EMACIO18 */ - 0, /* EMACIO19 */ - 3, /* FLASHIO0 */ - 0, /* FLASHIO1 */ - 3, /* FLASHIO2 */ - 3, /* FLASHIO3 */ - 3, /* FLASHIO4 */ - 3, /* FLASHIO5 */ - 3, /* FLASHIO6 */ - 3, /* FLASHIO7 */ - 0, /* FLASHIO8 */ - 3, /* FLASHIO9 */ - 3, /* FLASHIO10 */ - 3, /* FLASHIO11 */ - 0, /* GENERALIO0 */ - 1, /* GENERALIO1 */ - 1, /* GENERALIO2 */ - 0, /* GENERALIO3 */ - 0, /* GENERALIO4 */ - 1, /* GENERALIO5 */ - 1, /* GENERALIO6 */ - 1, /* GENERALIO7 */ - 1, /* GENERALIO8 */ - 0, /* GENERALIO9 */ - 0, /* GENERALIO10 */ - 0, /* GENERALIO11 */ - 0, /* GENERALIO12 */ - 2, /* GENERALIO13 */ - 2, /* GENERALIO14 */ - 1, /* GENERALIO15 */ - 1, /* GENERALIO16 */ - 1, /* GENERALIO17 */ - 1, /* GENERALIO18 */ - 0, /* GENERALIO19 */ - 0, /* GENERALIO20 */ - 0, /* GENERALIO21 */ - 0, /* GENERALIO22 */ - 0, /* GENERALIO23 */ - 0, /* GENERALIO24 */ - 0, /* GENERALIO25 */ - 0, /* GENERALIO26 */ - 0, /* GENERALIO27 */ - 0, /* GENERALIO28 */ - 0, /* GENERALIO29 */ - 0, /* GENERALIO30 */ - 0, /* GENERALIO31 */ - 0, /* MIXED1IO0 */ - 1, /* MIXED1IO1 */ - 1, /* MIXED1IO2 */ - 1, /* MIXED1IO3 */ - 1, /* MIXED1IO4 */ - 0, /* MIXED1IO5 */ - 0, /* MIXED1IO6 */ - 0, /* MIXED1IO7 */ - 1, /* MIXED1IO8 */ - 1, /* MIXED1IO9 */ - 1, /* MIXED1IO10 */ - 1, /* MIXED1IO11 */ - 0, /* MIXED1IO12 */ - 0, /* MIXED1IO13 */ - 0, /* MIXED1IO14 */ - 1, /* MIXED1IO15 */ - 1, /* MIXED1IO16 */ - 1, /* MIXED1IO17 */ - 1, /* MIXED1IO18 */ - 0, /* MIXED1IO19 */ - 0, /* MIXED1IO20 */ - 0, /* MIXED1IO21 */ - 0, /* MIXED2IO0 */ - 0, /* MIXED2IO1 */ - 0, /* MIXED2IO2 */ - 0, /* MIXED2IO3 */ - 0, /* MIXED2IO4 */ - 0, /* MIXED2IO5 */ - 0, /* MIXED2IO6 */ - 0, /* MIXED2IO7 */ - 0, /* GPLINMUX48 */ - 0, /* GPLINMUX49 */ - 0, /* GPLINMUX50 */ - 0, /* GPLINMUX51 */ - 0, /* GPLINMUX52 */ - 0, /* GPLINMUX53 */ - 0, /* GPLINMUX54 */ - 0, /* GPLINMUX55 */ - 0, /* GPLINMUX56 */ - 0, /* GPLINMUX57 */ - 0, /* GPLINMUX58 */ - 0, /* GPLINMUX59 */ - 0, /* GPLINMUX60 */ - 0, /* GPLINMUX61 */ - 0, /* GPLINMUX62 */ - 0, /* GPLINMUX63 */ - 0, /* GPLINMUX64 */ - 0, /* GPLINMUX65 */ - 0, /* GPLINMUX66 */ - 0, /* GPLINMUX67 */ - 0, /* GPLINMUX68 */ - 0, /* GPLINMUX69 */ - 0, /* GPLINMUX70 */ - 1, /* GPLMUX0 */ - 1, /* GPLMUX1 */ - 1, /* GPLMUX2 */ - 1, /* GPLMUX3 */ - 1, /* GPLMUX4 */ - 1, /* GPLMUX5 */ - 1, /* GPLMUX6 */ - 1, /* GPLMUX7 */ - 1, /* GPLMUX8 */ - 1, /* GPLMUX9 */ - 1, /* GPLMUX10 */ - 1, /* GPLMUX11 */ - 1, /* GPLMUX12 */ - 1, /* GPLMUX13 */ - 1, /* GPLMUX14 */ - 1, /* GPLMUX15 */ - 1, /* GPLMUX16 */ - 1, /* GPLMUX17 */ - 1, /* GPLMUX18 */ - 1, /* GPLMUX19 */ - 1, /* GPLMUX20 */ - 1, /* GPLMUX21 */ - 1, /* GPLMUX22 */ - 1, /* GPLMUX23 */ - 1, /* GPLMUX24 */ - 1, /* GPLMUX25 */ - 1, /* GPLMUX26 */ - 1, /* GPLMUX27 */ - 1, /* GPLMUX28 */ - 1, /* GPLMUX29 */ - 1, /* GPLMUX30 */ - 1, /* GPLMUX31 */ - 1, /* GPLMUX32 */ - 1, /* GPLMUX33 */ - 1, /* GPLMUX34 */ - 1, /* GPLMUX35 */ - 1, /* GPLMUX36 */ - 1, /* GPLMUX37 */ - 1, /* GPLMUX38 */ - 1, /* GPLMUX39 */ - 1, /* GPLMUX40 */ - 1, /* GPLMUX41 */ - 1, /* GPLMUX42 */ - 1, /* GPLMUX43 */ - 1, /* GPLMUX44 */ - 1, /* GPLMUX45 */ - 1, /* GPLMUX46 */ - 1, /* GPLMUX47 */ - 1, /* GPLMUX48 */ - 1, /* GPLMUX49 */ - 1, /* GPLMUX50 */ - 1, /* GPLMUX51 */ - 1, /* GPLMUX52 */ - 1, /* GPLMUX53 */ - 1, /* GPLMUX54 */ - 1, /* GPLMUX55 */ - 1, /* GPLMUX56 */ - 1, /* GPLMUX57 */ - 1, /* GPLMUX58 */ - 1, /* GPLMUX59 */ - 1, /* GPLMUX60 */ - 1, /* GPLMUX61 */ - 1, /* GPLMUX62 */ - 1, /* GPLMUX63 */ - 1, /* GPLMUX64 */ - 1, /* GPLMUX65 */ - 1, /* GPLMUX66 */ - 1, /* GPLMUX67 */ - 1, /* GPLMUX68 */ - 1, /* GPLMUX69 */ - 1, /* GPLMUX70 */ - 0, /* NANDUSEFPGA */ - 0, /* UART0USEFPGA */ - 0, /* RGMII1USEFPGA */ - 0, /* SPIS0USEFPGA */ - 0, /* CAN0USEFPGA */ - 0, /* I2C0USEFPGA */ - 0, /* SDMMCUSEFPGA */ - 0, /* QSPIUSEFPGA */ - 0, /* SPIS1USEFPGA */ - 0, /* RGMII0USEFPGA */ - 1, /* UART1USEFPGA */ - 0, /* CAN1USEFPGA */ - 0, /* USB1USEFPGA */ - 0, /* I2C3USEFPGA */ - 0, /* I2C2USEFPGA */ - 0, /* I2C1USEFPGA */ - 0, /* SPIM1USEFPGA */ - 0, /* USB0USEFPGA */ - 0 /* SPIM0USEFPGA */ -}; -#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/aries/mcvevk/qts/pll_config.h b/board/aries/mcvevk/qts/pll_config.h deleted file mode 100644 index 4fa868e458..0000000000 --- a/board/aries/mcvevk/qts/pll_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Altera SoCFPGA Clock and PLL configuration - */ - -#ifndef __SOCFPGA_PLL_CONFIG_H__ -#define __SOCFPGA_PLL_CONFIG_H__ - -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 - -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 - -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 - -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 - -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 1953125 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 3125000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 100000000 -#define CONFIG_HPS_CLK_CAN1_HZ 100000000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 - -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 - - -#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/aries/mcvevk/qts/sdram_config.h b/board/aries/mcvevk/qts/sdram_config.h deleted file mode 100644 index fd72926a89..0000000000 --- a/board/aries/mcvevk/qts/sdram_config.h +++ /dev/null @@ -1,343 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Altera SoCFPGA SDRAM configuration - */ - -#ifndef __SOCFPGA_SDRAM_CONFIG_H__ -#define __SOCFPGA_SDRAM_CONFIG_H__ - -/* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 - -/* Sequencer auto configuration */ -#define RW_MGR_ACTIVATE_0_AND_1 0x0D -#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E -#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 -#define RW_MGR_ACTIVATE_1 0x0F -#define RW_MGR_CLEAR_DQS_ENABLE 0x49 -#define RW_MGR_GUARANTEED_READ 0x4C -#define RW_MGR_GUARANTEED_READ_CONT 0x54 -#define RW_MGR_GUARANTEED_WRITE 0x18 -#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B -#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F -#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 -#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D -#define RW_MGR_IDLE 0x00 -#define RW_MGR_IDLE_LOOP1 0x7B -#define RW_MGR_IDLE_LOOP2 0x7A -#define RW_MGR_INIT_RESET_0_CKE_0 0x6F -#define RW_MGR_INIT_RESET_1_CKE_0 0x74 -#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 -#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 -#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 -#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 -#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 -#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 -#define RW_MGR_MRS0_DLL_RESET 0x02 -#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 -#define RW_MGR_MRS0_USER 0x07 -#define RW_MGR_MRS0_USER_MIRR 0x0C -#define RW_MGR_MRS1 0x03 -#define RW_MGR_MRS1_MIRR 0x09 -#define RW_MGR_MRS2 0x04 -#define RW_MGR_MRS2_MIRR 0x0A -#define RW_MGR_MRS3 0x05 -#define RW_MGR_MRS3_MIRR 0x0B -#define RW_MGR_PRECHARGE_ALL 0x12 -#define RW_MGR_READ_B2B 0x59 -#define RW_MGR_READ_B2B_WAIT1 0x61 -#define RW_MGR_READ_B2B_WAIT2 0x6B -#define RW_MGR_REFRESH_ALL 0x14 -#define RW_MGR_RETURN 0x01 -#define RW_MGR_SGLE_READ 0x7D -#define RW_MGR_ZQCL 0x06 - -/* Sequencer defines configuration */ -#define AFI_RATE_RATIO 1 -#define CALIB_LFIFO_OFFSET 7 -#define CALIB_VFIFO_OFFSET 5 -#define ENABLE_SUPER_QUICK_CALIBRATION 0 -#define IO_DELAY_PER_DCHAIN_TAP 25 -#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 -#define IO_DELAY_PER_OPA_TAP 312 -#define IO_DLL_CHAIN_LENGTH 8 -#define IO_DQDQS_OUT_PHASE_MAX 0 -#define IO_DQS_EN_DELAY_MAX 31 -#define IO_DQS_EN_DELAY_OFFSET 0 -#define IO_DQS_EN_PHASE_MAX 7 -#define IO_DQS_IN_DELAY_MAX 31 -#define IO_DQS_IN_RESERVE 4 -#define IO_DQS_OUT_RESERVE 4 -#define IO_IO_IN_DELAY_MAX 31 -#define IO_IO_OUT1_DELAY_MAX 31 -#define IO_IO_OUT2_DELAY_MAX 0 -#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 -#define MAX_LATENCY_COUNT_WIDTH 5 -#define READ_VALID_FIFO_SIZE 16 -#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550496 -#define RW_MGR_MEM_ADDRESS_MIRRORING 0 -#define RW_MGR_MEM_DATA_MASK_WIDTH 4 -#define RW_MGR_MEM_DATA_WIDTH 32 -#define RW_MGR_MEM_DQ_PER_READ_DQS 8 -#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 -#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 -#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 -#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 -#define RW_MGR_MEM_NUMBER_OF_RANKS 1 -#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 -#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 -#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 -#define TINIT_CNTR0_VAL 99 -#define TINIT_CNTR1_VAL 32 -#define TINIT_CNTR2_VAL 32 -#define TRESET_CNTR0_VAL 99 -#define TRESET_CNTR1_VAL 99 -#define TRESET_CNTR2_VAL 10 - -/* Sequencer ac_rom_init configuration */ -const u32 ac_rom_init[] = { - 0x20700000, - 0x20780000, - 0x10080421, - 0x10080520, - 0x10090044, - 0x100a0008, - 0x100b0000, - 0x10380400, - 0x10080441, - 0x100804c0, - 0x100a0024, - 0x10090010, - 0x100b0000, - 0x30780000, - 0x38780000, - 0x30780000, - 0x10680000, - 0x106b0000, - 0x10280400, - 0x10480000, - 0x1c980000, - 0x1c9b0000, - 0x1c980008, - 0x1c9b0008, - 0x38f80000, - 0x3cf80000, - 0x38780000, - 0x18180000, - 0x18980000, - 0x13580000, - 0x135b0000, - 0x13580008, - 0x135b0008, - 0x33780000, - 0x10580008, - 0x10780000 -}; - -/* Sequencer inst_rom_init configuration */ -const u32 inst_rom_init[] = { - 0x80000, - 0x80680, - 0x8180, - 0x8200, - 0x8280, - 0x8300, - 0x8380, - 0x8100, - 0x8480, - 0x8500, - 0x8580, - 0x8600, - 0x8400, - 0x800, - 0x8680, - 0x880, - 0xa680, - 0x80680, - 0x900, - 0x80680, - 0x980, - 0xa680, - 0x8680, - 0x80680, - 0xb68, - 0xcce8, - 0xae8, - 0x8ce8, - 0xb88, - 0xec88, - 0xa08, - 0xac88, - 0x80680, - 0xce00, - 0xcd80, - 0xe700, - 0xc00, - 0x20ce0, - 0x20ce0, - 0x20ce0, - 0x20ce0, - 0xd00, - 0x680, - 0x680, - 0x680, - 0x680, - 0x60e80, - 0x61080, - 0x61080, - 0x61080, - 0xa680, - 0x8680, - 0x80680, - 0xce00, - 0xcd80, - 0xe700, - 0xc00, - 0x30ce0, - 0x30ce0, - 0x30ce0, - 0x30ce0, - 0xd00, - 0x680, - 0x680, - 0x680, - 0x680, - 0x70e80, - 0x71080, - 0x71080, - 0x71080, - 0xa680, - 0x8680, - 0x80680, - 0x1158, - 0x6d8, - 0x80680, - 0x1168, - 0x7e8, - 0x7e8, - 0x87e8, - 0x40fe8, - 0x410e8, - 0x410e8, - 0x410e8, - 0x1168, - 0x7e8, - 0x7e8, - 0xa7e8, - 0x80680, - 0x40e88, - 0x41088, - 0x41088, - 0x41088, - 0x40f68, - 0x410e8, - 0x410e8, - 0x410e8, - 0xa680, - 0x40fe8, - 0x410e8, - 0x410e8, - 0x410e8, - 0x41008, - 0x41088, - 0x41088, - 0x41088, - 0x1100, - 0xc680, - 0x8680, - 0xe680, - 0x80680, - 0x0, - 0x8000, - 0xa000, - 0xc000, - 0x80000, - 0x80, - 0x8080, - 0xa080, - 0xc080, - 0x80080, - 0x9180, - 0x8680, - 0xa680, - 0x80680, - 0x40f08, - 0x80680 -}; - -#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/aries/mcvevk/socfpga.c b/board/aries/mcvevk/socfpga.c deleted file mode 100644 index f173bf84ac..0000000000 --- a/board/aries/mcvevk/socfpga.c +++ /dev/null @@ -1,5 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Marek Vasut <marex@denx.de> - */ -#include <common.h> diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig deleted file mode 100644 index e26d49aef6..0000000000 --- a/configs/m28evk_defconfig +++ /dev/null @@ -1,58 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_M28EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_FIT=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyAMA0,115200n8 " -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(u-boot),512k(env1),512k(env2),14m(boot),238m(data),-@4096k(UBI)" -CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_MMC_MXS=y -CONFIG_NAND=y -CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_MXS_SPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/m53evk_defconfig b/configs/m53evk_defconfig deleted file mode 100644 index 71f1d9fa6c..0000000000 --- a/configs/m53evk_defconfig +++ /dev/null @@ -1,58 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX5=y -CONFIG_SYS_TEXT_BASE=0x71000000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_M53EVK=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -# CONFIG_CMD_BMODE is not set -CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aries/m53evk/imximage.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttymxc1,115200" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SATA=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1024k(u-boot),512k(env1),512k(env2),14m(boot),240m(data),-@2048k(UBI)" -CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_DWC_AHSATA=y -CONFIG_FSL_ESDHC=y -CONFIG_NAND=y -CONFIG_NAND_MXC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_MCS7830=y -CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig deleted file mode 100644 index 312191b6e3..0000000000 --- a/configs/ma5d4evk_defconfig +++ /dev/null @@ -1,61 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_AT91=y -CONFIG_SYS_TEXT_BASE=0x26f00000 -CONFIG_TARGET_MA5D4EVK=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_ma5d4evk" -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_FIT=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS3,115200" -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMI is not set -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_DFU=y -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_DFU_MMC=y -CONFIG_DFU_SF=y -CONFIG_SPI_FLASH=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="AriesEmbedded" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_USB_GADGET_ATMEL_USBA=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_ETHER=y -CONFIG_FAT_WRITE=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig deleted file mode 100644 index fcae88d09f..0000000000 --- a/configs/socfpga_mcvevk_defconfig +++ /dev/null @@ -1,68 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x01000040 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_SOCFPGA_ARIES_MCVEVK=y -CONFIG_SPL=y -CONFIG_SPL_STACK_R_ADDR=0x00800000 -CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk" -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_DFU=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0" -CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SPL_DM=y -CONFIG_DFU_MMC=y -CONFIG_FPGA_SOCFPGA=y -CONFIG_DM_GPIO=y -CONFIG_DWAPB_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_DW=y -CONFIG_DM_MMC=y -CONFIG_MMC_DW=y -CONFIG_DM_ETH=y -CONFIG_PHY_GIGE=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_DM_RESET=y -CONFIG_SPI=y -CONFIG_CADENCE_QSPI=y -CONFIG_DESIGNWARE_SPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="denx" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USE_TINY_PRINTF=y diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h deleted file mode 100644 index bb1d6b4f5d..0000000000 --- a/include/configs/m28evk.h +++ /dev/null @@ -1,225 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ -#ifndef __CONFIGS_M28EVK_H__ -#define __CONFIGS_M28EVK_H__ - -/* System configurations */ -#define CONFIG_MACH_TYPE MACH_TYPE_M28EVK - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* Memory configuration */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ -#define CONFIG_ENV_SIZE (16 * 1024) - -/* Environment is in NAND */ -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_OFFSET (24 * CONFIG_ENV_SECT_SIZE) /* 3 MiB */ -#define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) - -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS -#endif - -/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#endif - -/* RTC */ -#ifdef CONFIG_CMD_DATE -/* Use the internal RTC in the MXS chip */ -#define CONFIG_RTC_INTERNAL -#ifdef CONFIG_RTC_INTERNAL -#define CONFIG_RTC_MXS -#else -#define CONFIG_RTC_M41T62 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 2000 -#endif -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_EHCI_MXS_PORT1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif - -/* SPI */ -#ifdef CONFIG_CMD_SPI -#define CONFIG_DEFAULT_SPI_BUS 2 -#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 - -/* SPI FLASH */ -#ifdef CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_BUS 2 -#define CONFIG_SF_DEFAULT_CS 0 -#define CONFIG_SF_DEFAULT_SPEED 40000000 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 - -#define CONFIG_ENV_SPI_BUS 2 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 40000000 -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 -#endif - -#endif - -/* LCD */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) -#endif - -/* Booting Linux */ -#define CONFIG_BOOTFILE "fitImage" -#define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environment */ -#define CONFIG_PREBOOT "run try_bootscript" -#define CONFIG_HOSTNAME "m28evk" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "consdev=ttyAMA0\0" \ - "baudrate=115200\0" \ - "bootscript=boot.scr\0" \ - "bootdev=/dev/mmcblk0p2\0" \ - "rootdev=/dev/mmcblk0p3\0" \ - "netdev=eth0\0" \ - "hostname=m28evk\0" \ - "rootpath=/opt/eldk-5.5/armv5te/rootfs-qte-sdk\0" \ - "kernel_addr_r=0x42000000\0" \ - "videomode=video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066," \ - "le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296," \ - "vmode:0\0" \ - "update_nand_full_filename=u-boot.nand\0" \ - "update_nand_firmware_filename=u-boot.sb\0" \ - "update_sd_firmware_filename=u-boot.sd\0" \ - "update_nand_firmware_maxsz=0x100000\0" \ - "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \ - "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \ - "update_nand_get_fcb_size=" /* Get size of FCB blocks */ \ - "nand device 0 ; " \ - "nand info ; " \ - "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \ - "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \ - "update_nand_full=" /* Update FCB, DBBT and FW */ \ - "if tftp ${update_nand_full_filename} ; then " \ - "run update_nand_get_fcb_size ; " \ - "nand scrub -y 0x0 ${filesize} ; " \ - "nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \ - "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \ - "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \ - "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \ - "fi\0" \ - "update_nand_firmware=" /* Update only firmware */ \ - "if tftp ${update_nand_firmware_filename} ; then " \ - "run update_nand_get_fcb_size ; " \ - "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \ - "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \ - "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \ - "nand erase ${fcb_sz} ${fw_sz} ; " \ - "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ - "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ - "fi\0" \ - "update_sd_firmware=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_sd_firmware_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ - "fi ; " \ - "fi\0" \ - "addcons=" \ - "setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "addip=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=" \ - "setenv bootargs ${bootargs} ${miscargs}\0" \ - "adddfltmtd=" \ - "if test \"x${mtdparts}\" == \"x\" ; then " \ - "mtdparts default ; " \ - "fi\0" \ - "addmtd=" \ - "run adddfltmtd ; " \ - "setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addargs=run addcons addmtd addmisc\0" \ - "mmcload=" \ - "mmc rescan ; " \ - "load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \ - "ubiload=" \ - "ubi part UBI ; ubifsmount ubi0:rootfs ; " \ - "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \ - "netload=" \ - "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ - "miscargs=nohlt panic=1\0" \ - "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ - "ubiargs=" \ - "setenv bootargs ubi.mtd=5 " \ - "root=ubi0:rootfs rootfstype=ubifs\0" \ - "nfsargs=" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ - "mmc_mmc=" \ - "run mmcload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "mmc_ubi=" \ - "run mmcload ubiargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "mmc_nfs=" \ - "run mmcload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "ubi_mmc=" \ - "run ubiload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "ubi_ubi=" \ - "run ubiload ubiargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "ubi_nfs=" \ - "run ubiload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_mmc=" \ - "run netload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_ubi=" \ - "run netload ubiargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_nfs=" \ - "run netload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "try_bootscript=" \ - "mmc rescan;" \ - "if test -e mmc 0:2 ${bootscript} ; then " \ - "if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \ - "then ; " \ - "echo Running bootscript... ; " \ - "source ${kernel_addr_r} ; " \ - "fi ; " \ - "fi\0" - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_M28EVK_H__ */ diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h deleted file mode 100644 index 9eaafc538c..0000000000 --- a/include/configs/m53evk.h +++ /dev/null @@ -1,267 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Aries M53 configuration - * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> - */ - -#ifndef __M53EVK_CONFIG_H__ -#define __M53EVK_CONFIG_H__ - -#include <asm/arch/imx-regs.h> - -#define CONFIG_REVISION_TAG -#define CONFIG_SYS_FSL_CLK - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * Memory configurations - */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) -#define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) -#define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x8ff00000 - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ - -/* - * Serial Driver - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART2_BASE - -/* - * MMC Driver - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 -#endif - -/* - * NAND - */ -#define CONFIG_ENV_SIZE (16 * 1024) -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI -#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI -#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_USE_FLASH_BBT - -/* Environment is in NAND */ -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_OFFSET (8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */ -#define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) - -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS -#endif - -/* - * Ethernet on SOC (FEC) - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_MII -#define CONFIG_DISCOVER_PHY -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC0" -#endif - -/* - * I2C - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ -#endif - -/* - * RTC - */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_M41T62 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 2000 -#endif - -/* - * USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_MX5 -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#endif - -/* - * SATA - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR -#define CONFIG_LBA48 -#endif - -/* - * LCD - */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASHIMAGE_GUARD -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) -#endif - -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTFILE "fitImage" -#define CONFIG_LOADADDR 0x70800000 -#define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * NAND SPL - */ -#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx" -#define CONFIG_SPL_TEXT_BASE 0x70008000 -#define CONFIG_SPL_PAD_TO 0x8000 -#define CONFIG_SPL_STACK 0x70004000 - -#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 - -/* - * Extra Environments - */ -#define CONFIG_PREBOOT "run try_bootscript" -#define CONFIG_HOSTNAME "m53evk" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "consdev=ttymxc1\0" \ - "baudrate=115200\0" \ - "bootscript=boot.scr\0" \ - "bootdev=/dev/mmcblk0p1\0" \ - "rootdev=/dev/mmcblk0p2\0" \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-qte-sdk\0" \ - "kernel_addr_r=0x72000000\0" \ - "addcons=" \ - "setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "addip=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=" \ - "setenv bootargs ${bootargs} ${miscargs}\0" \ - "adddfltmtd=" \ - "if test \"x${mtdparts}\" == \"x\" ; then " \ - "mtdparts default ; " \ - "fi\0" \ - "addmtd=" \ - "run adddfltmtd ; " \ - "setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addargs=run addcons addmtd addmisc\0" \ - "mmcload=" \ - "mmc rescan ; " \ - "load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \ - "ubiload=" \ - "ubi part UBI ; ubifsmount ubi0:rootfs ; " \ - "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \ - "netload=" \ - "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ - "miscargs=nohlt panic=1\0" \ - "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ - "ubiargs=" \ - "setenv bootargs ubi.mtd=5 " \ - "root=ubi0:rootfs rootfstype=ubifs\0" \ - "nfsargs=" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ - "mmc_mmc=" \ - "run mmcload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "mmc_ubi=" \ - "run mmcload ubiargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "mmc_nfs=" \ - "run mmcload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "ubi_mmc=" \ - "run ubiload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "ubi_ubi=" \ - "run ubiload ubiargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "ubi_nfs=" \ - "run ubiload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_mmc=" \ - "run netload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_ubi=" \ - "run netload ubiargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_nfs=" \ - "run netload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "try_bootscript=" \ - "mmc rescan;" \ - "if test -e mmc 0:1 ${bootscript} ; then " \ - "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \ - "then ; " \ - "echo Running bootscript... ; " \ - "source ${kernel_addr_r} ; " \ - "fi ; " \ - "fi\0" - -#endif /* __M53EVK_CONFIG_H__ */ diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h deleted file mode 100644 index 5e3d6e80a8..0000000000 --- a/include/configs/ma5d4evk.h +++ /dev/null @@ -1,217 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Aries MA5D4 configuration - * Copyright (C) 2015 Marek Vasut <marex@denx.de> - */ - -#ifndef __MA5D4EVK_CONFIG_H__ -#define __MA5D4EVK_CONFIG_H__ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#include "at91-sama5_common.h" -#define CONFIG_SYS_USE_SERIALFLASH 1 -#define CONFIG_BOARD_LATE_INIT - -/* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c - -/* - * Memory configurations - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x210000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -/* - * Environment - */ -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_SYS_MMC_ENV_DEV 0 /* eMMC */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ - -/* - * U-Boot general configurations - */ - -/* - * Serial Driver - */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE 0xf802c000 -#define CONFIG_USART_ID 6 - -/* - * Ethernet - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY -#define CONFIG_ARP_TIMEOUT 200UL -#define CONFIG_IP_DEFRAG -#endif - -/* - * LCD - */ -#ifdef CONFIG_LCD -#define CONFIG_BMP_16BPP -#define CONFIG_BMP_24BPP -#define CONFIG_BMP_32BPP -#define LCD_BPP LCD_COLOR16 -#define LCD_OUTPUT_BPP 24 -#define CONFIG_ATMEL_HLCD -#endif - -/* - * SD/MMC - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#endif - -/* - * SPI NOR (boot memory) - */ -#ifdef CONFIG_CMD_SF -#define CONFIG_ATMEL_SPI0 -#define CONFIG_SPI_FLASH_ATMEL -#define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS 0 -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#endif - -/* - * USB - */ -#ifdef CONFIG_CMD_USB - -/* USB device */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 * 1024 * 1024) -#define DFU_DEFAULT_POLL_TIMEOUT 300 -#endif - -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTFILE "fitImage" -#define CONFIG_LOADADDR 0x20800000 -#define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * Extra Environments - */ -#define CONFIG_PREBOOT "run try_bootscript" -#define CONFIG_HOSTNAME "ma5d4evk" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "consdev=ttyS3\0" \ - "baudrate=115200\0" \ - "bootscript=boot.scr\0" \ - "bootdev=/dev/mmcblk0p1\0" \ - "bootpart=0:1\0" \ - "rootdev=/dev/mmcblk0p2\0" \ - "netdev=eth0\0" \ - "dfu_alt_info=mmc raw 0 3867148288\0" \ - "kernel_addr_r=0x22000000\0" \ - "update_spi_firmware_spl_addr=0x21000000\0" \ - "update_spi_firmware_spl_filename=boot.bin\0" \ - "update_spi_firmware_addr=0x22000000\0" \ - "update_spi_firmware_filename=u-boot.img\0" \ - "update_spi_firmware=" /* Update the SPI flash firmware */ \ - "if sf probe ; then " \ - "if tftp ${update_spi_firmware_spl_addr} " \ - "${update_spi_firmware_spl_filename} ; then " \ - "setenv update_spi_firmware_spl_filesize ${filesize} ; "\ - "if tftp ${update_spi_firmware_addr} " \ - "${update_spi_firmware_filename} ; then " \ - "setenv update_spi_firmware_filesize ${filesize} ; " \ - "sf update ${update_spi_firmware_spl_addr} 0x0 " \ - "${update_spi_firmware_spl_filesize} ; " \ - "sf update ${update_spi_firmware_addr} 0x10000 " \ - "${update_spi_firmware_filesize} ; " \ - "fi ; " \ - "fi ; " \ - "fi\0" \ - "addcons=" \ - "setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "addip=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=" \ - "setenv bootargs ${bootargs} ${miscargs}\0" \ - "addargs=run addcons addmisc\0" \ - "mmcload=" \ - "mmc rescan ; " \ - "load mmc ${bootpart} ${kernel_addr_r} ${bootfile}\0" \ - "netload=" \ - "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ - "miscargs=nohlt panic=1\0" \ - "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ - "nfsargs=" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ - "fdtimg=if test ${bootmode} = \"sf\" ; then " \ - "setenv kernel_fdt 1 ; " \ - "else ; " \ - "setenv kernel_fdt 2 ; " \ - "fi\0" \ - "mmc_mmc=" \ - "run fdtimg mmcload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}:kernel@1 - ${kernel_addr_r}:fdt@${kernel_fdt}\0" \ - "mmc_nfs=" \ - "run fdtimg mmcload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}:kernel@1 - ${kernel_addr_r}:fdt@${kernel_fdt}\0" \ - "net_mmc=" \ - "run fdtimg netload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}:kernel@1 - ${kernel_addr_r}:fdt@${kernel_fdt}\0" \ - "net_nfs=" \ - "run fdtimg netload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}:kernel@1 - ${kernel_addr_r}:fdt@${kernel_fdt}\0" \ - "try_bootscript=" \ - "mmc rescan;" \ - "if test -e mmc 1:1 ${bootscript} ; then " \ - "if load mmc 1:1 ${kernel_addr_r} ${bootscript};" \ - "then ; " \ - "echo Running bootscript... ; " \ - "source ${kernel_addr_r} ; " \ - "fi ; " \ - "fi\0" -/* SPL */ -#define CONFIG_SPL_TEXT_BASE 0x200000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 - -#define CONFIG_SYS_USE_MMC -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT - -#endif /* __MA5D4EVK_CONFIG_H__ */ diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h deleted file mode 100644 index 4d1c4f2c2b..0000000000 --- a/include/configs/socfpga_mcvevk.h +++ /dev/null @@ -1,102 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Marek Vasut <marex@denx.de> - */ -#ifndef __CONFIG_ARIES_MCVEVK_H__ -#define __CONFIG_ARIES_MCVEVK_H__ - -#include <asm/arch/base_addr_ac5.h> - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on MCV */ - -/* Booting Linux */ -#define CONFIG_BOOTFILE "fitImage" -#define CONFIG_PREBOOT "run try_bootscript" -#define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Environment is in MMC */ -#define CONFIG_ENV_OVERWRITE - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "consdev=ttyS0\0" \ - "baudrate=115200\0" \ - "bootscript=boot.scr\0" \ - "bootdev=/dev/mmcblk0p2\0" \ - "rootdev=/dev/mmcblk0p3\0" \ - "netdev=eth0\0" \ - "hostname=mcvevk\0" \ - "kernel_addr_r=0x10000000\0" \ - "dfu_alt_info=mmc raw 0 3867148288\0" \ - "update_filename=u-boot-with-spl.sfp\0" \ - "update_sd_offset=0x800\0" \ - "update_sd=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} ${update_sd_offset} ${fw_sz} ; " \ - "fi ; " \ - "fi\0" \ - "update_qspi_offset=0x0\0" \ - "update_qspi=" /* Update the QSPI firmware */ \ - "if sf probe ; then " \ - "if tftp ${update_filename} ; then " \ - "sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \ - "fi ; " \ - "fi\0" \ - "fpga_filename=output_file.rbf\0" \ - "load_fpga=" /* Load FPGA bitstream */ \ - "if tftp ${fpga_filename} ; then " \ - "fpga load 0 $loadaddr $filesize ; " \ - "bridge enable ; " \ - "fi\0" \ - "addcons=" \ - "setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "addip=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=" \ - "setenv bootargs ${bootargs} ${miscargs}\0" \ - "addargs=run addcons addmisc\0" \ - "mmcload=" \ - "mmc rescan ; " \ - "load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \ - "netload=" \ - "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ - "miscargs=nohlt panic=1\0" \ - "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ - "nfsargs=" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ - "mmc_mmc=" \ - "run mmcload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "mmc_nfs=" \ - "run mmcload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_mmc=" \ - "run netload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_nfs=" \ - "run netload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "try_bootscript=" \ - "mmc rescan;" \ - "if test -e mmc 0:2 ${bootscript} ; then " \ - "if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \ - "then ; " \ - "echo Running bootscript... ; " \ - "source ${kernel_addr_r} ; " \ - "fi ; " \ - "fi\0" - -/* The rest of the configuration is shared */ -#include <configs/socfpga_common.h> - -#endif /* __CONFIG_ARIES_MCVEVK_H__ */ |