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author | Marek Vasut <marex@denx.de> | 2019-04-16 14:19:34 +0200 |
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committer | Marek Vasut <marex@denx.de> | 2019-04-29 10:08:55 +0200 |
commit | c1d4b464c8b8826b1d8a6d84ee5202f71ce933d1 (patch) | |
tree | 5b522270674ff21cca254a209348725c36a2c6fc /scripts | |
parent | 8df653c32545171ecede4b740e38e8a4af4ed9eb (diff) | |
download | u-boot-c1d4b464c8b8826b1d8a6d84ee5202f71ce933d1.tar.gz u-boot-c1d4b464c8b8826b1d8a6d84ee5202f71ce933d1.tar.xz u-boot-c1d4b464c8b8826b1d8a6d84ee5202f71ce933d1.zip |
ARM: socfpga: Disable bridges in SPL unless booting from FPGA
Disable bridges between L3 Main switch and FPGA unless booting
from FPGA and keep them disabled to prevent glitches and possible
hangs of the L3 Main switch.
The current version of the code could have enabled the bridges
between the L3 Main switch and FPGA for a short period of time
in board_init_f() in case the FPGA was programmed and then again
disable them at the end of board_init_f(). Replace this with a
code which only sets up the handoff registers and let the user
enable the bridges later on.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions