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| author | York Sun <yorksun@freescale.com> | 2015-01-06 13:18:47 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-02-24 13:09:06 -0800 |
| commit | 9955b4ab0187e0e9faac57acc01ebe7714d0ec23 (patch) | |
| tree | 0cf5592aeb45af97ff734a8653589dde5a16e1b7 /scripts | |
| parent | 1f3402e7291afa3ba0a5f4da72640edaf2f65405 (diff) | |
| download | u-boot-9955b4ab0187e0e9faac57acc01ebe7714d0ec23.tar.gz u-boot-9955b4ab0187e0e9faac57acc01ebe7714d0ec23.tar.xz u-boot-9955b4ab0187e0e9faac57acc01ebe7714d0ec23.zip | |
driver/ddr/fsl: Add workaround for A008336
Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space
for 64-bit DDR controllers.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions