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| author | Rick Chen <rick@andestech.com> | 2019-11-14 13:52:25 +0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-12-10 08:23:10 +0800 |
| commit | 8ba595b6bda56eac15d721554ea0ab8fc6a48f73 (patch) | |
| tree | af8b3931b445a7fac6e79195923aa302ab7829a5 /scripts/objdiff | |
| parent | 43a0832ba09068d1ab0628afbe62e498450ece63 (diff) | |
| download | u-boot-8ba595b6bda56eac15d721554ea0ab8fc6a48f73.tar.gz u-boot-8ba595b6bda56eac15d721554ea0ab8fc6a48f73.tar.xz u-boot-8ba595b6bda56eac15d721554ea0ab8fc6a48f73.zip | |
riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL
The mcache_ctl csr only can be manipulated in M mode.
Add SPL_RISCV_MMODE for U-Boot SPL to control cache
operation.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Diffstat (limited to 'scripts/objdiff')
0 files changed, 0 insertions, 0 deletions