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| author | vijay rai <vijay.rai@freescale.com> | 2014-06-20 10:45:29 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-07-22 16:25:54 -0700 |
| commit | 6666017f44e39ec0385e3c7736b8c9af46cf4f08 (patch) | |
| tree | fab7529d9b9ac0b7f28fcbcd358c2ca52633311e /scripts/checkstack.pl | |
| parent | 591dd192307d81cf8f8705b06854e973c53d4c4d (diff) | |
| download | u-boot-6666017f44e39ec0385e3c7736b8c9af46cf4f08.tar.gz u-boot-6666017f44e39ec0385e3c7736b8c9af46cf4f08.tar.xz u-boot-6666017f44e39ec0385e3c7736b8c9af46cf4f08.zip | |
powerpc/t1040qds: Initialize EPHY2 clock to RGMII only
Setting FPGA register brdcfg9 EPHY2 bits to '0' to initialize EPHY2 clock to RGMII mode.
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'scripts/checkstack.pl')
0 files changed, 0 insertions, 0 deletions