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| author | Jagan Teki <jagan@amarulasolutions.com> | 2019-07-16 17:27:12 +0530 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-07-20 23:59:44 +0800 |
| commit | 5cbc8669819a69c22a50d2fb22c9d4962c8bbad5 (patch) | |
| tree | c0ecd11723228a17348918bc330e0ec1b8063d11 /scripts/checkstack.pl | |
| parent | 6cbd2426b34e7430b0733ab9a912d378c027b647 (diff) | |
ram: rk3399: Don't wait for PLL lock in lpddr4
lpddr4 has PLL bypass mode during phy initialization phase,
which does all pll configurations.
So no need to wait explicitly during pctl config.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Diffstat (limited to 'scripts/checkstack.pl')
0 files changed, 0 insertions, 0 deletions