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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2013-12-12 12:09:01 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-01-02 14:10:13 -0800 |
| commit | 562de1d6da5bdc1789bd258d464d6ca57571861d (patch) | |
| tree | 84ada120ab90055522b69a080817f2c5bbb13bc4 /scripts/checkstack.pl | |
| parent | fbe76ae4e3bacd5183294488947ec148df28d55b (diff) | |
| download | u-boot-562de1d6da5bdc1789bd258d464d6ca57571861d.tar.gz u-boot-562de1d6da5bdc1789bd258d464d6ca57571861d.tar.xz u-boot-562de1d6da5bdc1789bd258d464d6ca57571861d.zip | |
board/t1040qds: Relax IFC FPGA timings
Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion)
is 0 i.e. 0 ns hold time on writes. This may not work on higher clock
freqencies.
So, Increase TCH as 0x8 i.e. 8 ip_clk.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Diffstat (limited to 'scripts/checkstack.pl')
0 files changed, 0 insertions, 0 deletions