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author | Matthew McClintock <msm@freescale.com> | 2012-08-13 13:21:19 +0000 |
---|---|---|
committer | Andy Fleming <afleming@freescale.com> | 2012-08-23 10:24:17 -0500 |
commit | 8c454047fe9c08a51410dca01b945cdcecb18b7e (patch) | |
tree | abe2c281cbaf813d2ae2c46d69e9c2dd05600b1e /nand_spl/board/freescale/p1010rdb | |
parent | abbe536ebc3ee974593b115de716705f0091344a (diff) | |
download | u-boot-8c454047fe9c08a51410dca01b945cdcecb18b7e.tar.gz u-boot-8c454047fe9c08a51410dca01b945cdcecb18b7e.tar.xz u-boot-8c454047fe9c08a51410dca01b945cdcecb18b7e.zip |
nand_spl: update udelay for Freescale boards
Let's use the more appropriate udelay for the nand_spl. While we
can't make use of u-boot's full udelay we can atl east use a for
loop that won't get optimized away .Since we have the bus clock
we can use the timebase to calculate wall time.
Looked at reusing the u-boot udelay functions but it pulls in a lot
of code and would require quite a bit of work to keep us within the
very small space constrains we currently have
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'nand_spl/board/freescale/p1010rdb')
-rw-r--r-- | nand_spl/board/freescale/p1010rdb/Makefile | 6 | ||||
-rw-r--r-- | nand_spl/board/freescale/p1010rdb/nand_boot.c | 11 |
2 files changed, 10 insertions, 7 deletions
diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile index 8d240eadd9..cdbd49292c 100644 --- a/nand_spl/board/freescale/p1010rdb/Makefile +++ b/nand_spl/board/freescale/p1010rdb/Makefile @@ -39,7 +39,8 @@ CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o ticks.o COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o + nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o \ + ../common.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -123,6 +124,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c: + @rm -f $(obj)../common.c + ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c endif ######################################################################### diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c index f5294d0da4..a0755098fe 100644 --- a/nand_spl/board/freescale/p1010rdb/nand_boot.c +++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c @@ -27,8 +27,9 @@ #include <asm/immap_85xx.h> #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_law.h> +#include <asm/global_data.h> -#define udelay(x) { int j; for (j = 0; j < x * 10000; j++) isync(); } +DECLARE_GLOBAL_DATA_PTR; unsigned long ddr_freq_mhz; @@ -82,8 +83,7 @@ void sdram_init(void) __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds); } - /* mimic 500us delay, with busy isync() loop */ - udelay(100); + udelay(500); /* Let the controller go */ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); @@ -94,20 +94,19 @@ void sdram_init(void) void board_init_f(ulong bootflag) { u32 plat_ratio, ddr_ratio; - unsigned long bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; - bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); + gd->bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); |