Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts:

	board/davinci/da830evm/da830evm.c
	board/edb93xx/sdram_cfg.c
	board/esd/otc570/otc570.c
	board/netstar/eeprom.c
	board/netstar/eeprom_start.S
	cpu/arm920t/ep93xx/timer.c
	include/configs/netstar.h
	include/configs/otc570.h

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

101 files changed, 6265 insertions, 522 deletions

diff --git a/include/amba_clcd.h b/include/amba_clcd.h
new file mode 100644
index 0000000000..db80517e53
--- /dev/null
+++ b/include/amba_clcd.h
@@ -0,0 +1,77 @@
+/*
+ * Register definitions for the AMBA CLCD logic cell.
+ *
+ * derived from David A Rusling, although rearranged as a C structure
+ *     linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
+ *
+ * Copyright (C) 2001 ARM Limited
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+/*
+ * CLCD Controller Internal Register addresses
+ */
+struct clcd_registers {
+	u32 tim0;	/* 0x00 */
+	u32 tim1;
+	u32 tim2;
+	u32 tim3;
+	u32 ubas;	/* 0x10 */
+	u32 lbas;
+#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW)
+	u32 ienb;
+	u32 cntl;
+#else /* Someone rearranged these two registers on the Versatile */
+	u32 cntl;
+	u32 ienb;
+#endif
+	u32 stat;	/* 0x20 */
+	u32 intr;
+	u32 ucur;
+	u32 lcur;
+	u32 unused[0x74];	/* 0x030..0x1ff */
+	u32 palette[0x80];	/* 0x200..0x3ff */
+};
+
+/* Bit definition for TIM2 */
+#define TIM2_CLKSEL		(1 << 5)
+#define TIM2_IVS		(1 << 11)
+#define TIM2_IHS		(1 << 12)
+#define TIM2_IPC		(1 << 13)
+#define TIM2_IOE		(1 << 14)
+#define TIM2_BCD		(1 << 26)
+
+/* Bit definitions for control register */
+#define CNTL_LCDEN		(1 << 0)
+#define CNTL_LCDBPP1		(0 << 1)
+#define CNTL_LCDBPP2		(1 << 1)
+#define CNTL_LCDBPP4		(2 << 1)
+#define CNTL_LCDBPP8		(3 << 1)
+#define CNTL_LCDBPP16		(4 << 1)
+#define CNTL_LCDBPP16_565	(6 << 1)
+#define CNTL_LCDBPP24		(5 << 1)
+#define CNTL_LCDBW		(1 << 4)
+#define CNTL_LCDTFT		(1 << 5)
+#define CNTL_LCDMONO8		(1 << 6)
+#define CNTL_LCDDUAL		(1 << 7)
+#define CNTL_BGR		(1 << 8)
+#define CNTL_BEBO		(1 << 9)
+#define CNTL_BEPO		(1 << 10)
+#define CNTL_LCDPWR		(1 << 11)
+#define CNTL_LCDVCOMP(x)	((x) << 12)
+#define CNTL_LDMAFIFOTIME	(1 << 15)
+#define CNTL_WATERMARK		(1 << 16)
+
+/* u-boot specific: information passed by the board file */
+struct clcd_config {
+	struct clcd_registers *address;
+	u32			tim0;
+	u32			tim1;
+	u32			tim2;
+	u32			tim3;
+	u32			cntl;
+	unsigned long		pixclock;
+};
diff --git a/include/asm-arm/arch-at91/at91_emac.h b/include/asm-arm/arch-at91/at91_emac.h
new file mode 100644
index 0000000000..45ae33311e
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91_emac.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC))
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef AT91_H
+#define AT91_H
+
+typedef struct at91_emac {
+	u32	 ctl;
+	u32	 cfg;
+	u32	 sr;
+	u32	 tar;
+	u32	 tcr;
+	u32	 tsr;
+	u32	 rbqp;
+	u32	 reserved0;
+	u32	 rsr;
+	u32	 isr;
+	u32	 ier;
+	u32	 idr;
+	u32	 imr;
+	u32	 man;
+	u32	 reserved1[2];
+	u32	 fra;
+	u32	 scol;
+	u32	 mocl;
+	u32	 ok;
+	u32	 seqe;
+	u32	 ale;
+	u32	 dte;
+	u32	 lcol;
+	u32	 ecol;
+	u32	 cse;
+	u32	 tue;
+	u32	 cde;
+	u32	 elr;
+	u32	 rjb;
+	u32	 usf;
+	u32	 sqee;
+	u32	 drfc;
+	u32	 reserved2[3];
+	u32	 hsh;
+	u32	 hsl;
+	u32	 sh1l;
+	u32	 sa1h;
+	u32	 sa2l;
+	u32	 sa2h;
+	u32	 sa3l;
+	u32	 sa3h;
+	u32	 sa4l;
+	u32	 sa4h;
+} at91_emac_t;
+
+#define AT91_EMAC_CTL_LB	0x0001
+#define AT91_EMAC_CTL_LBL	0x0002
+#define AT91_EMAC_CTL_RE	0x0004
+#define AT91_EMAC_CTL_TE	0x0008
+#define AT91_EMAC_CTL_MPE	0x0010
+#define AT91_EMAC_CTL_CSR	0x0020
+#define AT91_EMAC_CTL_ISR	0x0040
+#define AT91_EMAC_CTL_WES	0x0080
+#define AT91_EMAC_CTL_BP	0x1000
+
+#define AT91_EMAC_CFG_SPD	0x0001
+#define AT91_EMAC_CFG_FD	0x0002
+#define AT91_EMAC_CFG_BR	0x0004
+#define AT91_EMAC_CFG_CAF	0x0010
+#define AT91_EMAC_CFG_NBC	0x0020
+#define AT91_EMAC_CFG_MTI	0x0040
+#define AT91_EMAC_CFG_UNI	0x0080
+#define AT91_EMAC_CFG_BIG	0x0100
+#define AT91_EMAC_CFG_EAE	0x0200
+#define AT91_EMAC_CFG_CLK_MASK	0xFFFFF3FF
+#define AT91_EMAC_CFG_MCLK_8	0x0000
+#define AT91_EMAC_CFG_MCLK_16	0x0400
+#define AT91_EMAC_CFG_MCLK_32	0x0800
+#define AT91_EMAC_CFG_MCLK_64	0x0C00
+#define AT91_EMAC_CFG_RTY	0x1000
+#define AT91_EMAC_CFG_RMII	0x2000
+
+#define AT91_EMAC_SR_LINK	0x0001
+#define AT91_EMAC_SR_MDIO	0x0002
+#define AT91_EMAC_SR_IDLE	0x0004
+
+#define AT91_EMAC_TCR_LEN(x)	(x & 0x7FF)
+#define AT91_EMAC_TCR_NCRC	0x8000
+
+#define AT91_EMAC_TSR_OVR	0x0001
+#define AT91_EMAC_TSR_COL	0x0002
+#define AT91_EMAC_TSR_RLE	0x0004
+#define AT91_EMAC_TSR_TXIDLE	0x0008
+#define AT91_EMAC_TSR_BNQ	0x0010
+#define AT91_EMAC_TSR_COMP	0x0020
+#define AT91_EMAC_TSR_UND	0x0040
+
+#define AT91_EMAC_RSR_BNA	0x0001
+#define AT91_EMAC_RSR_REC	0x0002
+#define AT91_EMAC_RSR_OVR	0x0004
+
+/*  ISR, IER, IDR, IMR use the same bits */
+#define AT91_EMAC_IxR_DONE	0x0001
+#define AT91_EMAC_IxR_RCOM	0x0002
+#define AT91_EMAC_IxR_RBNA	0x0004
+#define AT91_EMAC_IxR_TOVR	0x0008
+#define AT91_EMAC_IxR_TUND	0x0010
+#define AT91_EMAC_IxR_RTRY	0x0020
+#define AT91_EMAC_IxR_TBRE	0x0040
+#define AT91_EMAC_IxR_TCOM	0x0080
+#define AT91_EMAC_IxR_TIDLE	0x0100
+#define AT91_EMAC_IxR_LINK	0x0200
+#define AT91_EMAC_IxR_ROVR	0x0400
+#define AT91_EMAC_IxR_HRESP	0x0800
+
+#define AT91_EMAC_MAN_DATA_MASK		0xFFFF
+#define AT91_EMAC_MAN_CODE_802_3	0x00020000
+#define AT91_EMAC_MAN_REGA(reg)		((reg & 0x1F) << 18)
+#define AT91_EMAC_MAN_PHYA(phy)		((phy & 0x1F) << 23)
+#define AT91_EMAC_MAN_RW_R		0x20000000
+#define AT91_EMAC_MAN_RW_W		0x10000000
+#define AT91_EMAC_MAN_HIGH		0x40000000
+#define AT91_EMAC_MAN_LOW		0x80000000
+
+#endif
diff --git a/include/asm-arm/arch-at91/at91_matrix.h b/include/asm-arm/arch-at91/at91_matrix.h
new file mode 100644
index 0000000000..9b3c110f52
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91_matrix.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef AT91_MATRIX_H
+#define AT91_MATRIX_H
+
+#ifdef __ASSEMBLY__
+
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x11C)
+#elif defined(CONFIG_AT91SAM9261)
+#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x30)
+#elif defined(CONFIG_AT91SAM9263)
+#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x120)
+#elif defined(CONFIG_AT91SAM9G45)
+#define AT91_ASM_MATRIX_CSA0	(AT91_MATRIX_BASE + 0x128)
+#else
+#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
+#endif
+
+#define AT91_ASM_MATRIX_MCFG	AT91_MATRIX_BASE
+
+#else
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+#define AT91_MATRIX_MASTERS	6
+#define AT91_MATRIX_SLAVES	5
+#elif defined(CONFIG_AT91SAM9261)
+#define AT91_MATRIX_MASTERS	1
+#define AT91_MATRIX_SLAVES	5
+#elif defined(CONFIG_AT91SAM9263)
+#define AT91_MATRIX_MASTERS	9
+#define AT91_MATRIX_SLAVES	7
+#elif defined(CONFIG_AT91SAM9G45)
+#define AT91_MATRIX_MASTERS	11
+#define AT91_MATRIX_SLAVES	8
+#else
+#error CPU not supported. Please update at91_matrix.h
+#endif
+
+typedef struct at91_priority {
+	u32	a;
+	u32	b;
+} at91_priority_t;
+
+typedef struct at91_matrix {
+	u32		mcfg[AT91_MATRIX_MASTERS];
+#if defined(CONFIG_AT91SAM9261)
+	u32		scfg[AT91_MATRIX_SLAVES];
+	u32		res61_1[3];
+	u32		tcr;
+	u32		res61_2[2];
+	u32		csa;
+	u32		pucr;
+	u32		res61_3[114];
+#else
+	u32		reserve1[16 - AT91_MATRIX_MASTERS];
+	u32		scfg[AT91_MATRIX_SLAVES];
+	u32		reserve2[16 - AT91_MATRIX_SLAVES];
+	at91_priority_t	pr[AT91_MATRIX_SLAVES];
+	u32		reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
+	u32		mrcr;		/* 0x100 Master Remap Control */
+	u32		reserve4[3];
+#if	defined(CONFIG_AT91SAM9G45)
+	u32		ccr[52]		/* 0x110 - 0x1E0 Chip Configuration */
+	u32		womr;		/* 0x1E4 Write Protect Mode  */
+	u32		wpsr;		/* 0x1E8 Write Protect Status */
+	u32		resg45_1[10];
+#elif defined(CONFIG_AT91SAM9260)  || defined(CONFIG_AT91SAM9G20)
+	u32		res60_1[3];
+	u32		csa;
+	u32		res60_2[56];
+#elif defined(CONFIG_AT91SAM9263)
+	u32		res63_1;
+	u32		tcmr;
+	u32		res63_2[2];
+	u32		csa[2];
+	u32		res63_3[54];
+#else
+	u32		reserve5[60];
+#endif
+#endif
+} at91_matrix_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_CSA_DBPUC		0x00000100
+#define AT91_MATRIX_CSA_VDDIOMSEL_1_8V	0x00000000
+#define AT91_MATRIX_CSA_VDDIOMSEL_3_3V	0x00010000
+
+#define AT91_MATRIX_CSA_EBI_CS1A	0x00000002
+#define AT91_MATRIX_CSA_EBI_CS3A	0x00000008
+#define AT91_MATRIX_CSA_EBI_CS4A	0x00000010
+#define AT91_MATRIX_CSA_EBI_CS5A	0x00000020
+
+#define AT91_MATRIX_CSA_EBI1_CS2A	0x00000008
+
+#endif
diff --git a/include/asm-arm/arch-at91/at91_mc.h b/include/asm-arm/arch-at91/at91_mc.h
new file mode 100644
index 0000000000..acfbd10c5c
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91_mc.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef AT91_MC_H
+#define AT91_MC_H
+
+#define AT91_ASM_MC_EBI_CSA	(AT91_MC_BASE + 0x60)
+#define AT91_ASM_MC_EBI_CFG	(AT91_MC_BASE + 0x64)
+#define AT91_ASM_MC_SMC_CSR0	(AT91_MC_BASE + 0x70)
+#define AT91_ASM_MC_SDRAMC_MR	(AT91_MC_BASE + 0x90)
+#define AT91_ASM_MC_SDRAMC_TR	(AT91_MC_BASE + 0x94)
+#define AT91_ASM_MC_SDRAMC_CR	(AT91_MC_BASE + 0x98)
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_ebi {
+	u32 	csa;		/* 0x00 Chip Select Assignment Register */
+	u32	cfgr;		/* 0x04 Configuration Register */
+	u32	reserved[2];
+} __attribute__ ((packed)) at91_ebi_t;
+
+#define AT91_EBI_CSA_CS0A	0x0001
+#define AT91_EBI_CSA_CS1A	0x0002
+
+#define AT91_EBI_CSA_CS3A	0x0008
+#define AT91_EBI_CSA_CS4A	0x0010
+
+typedef struct at91_sdramc {
+	u32	mr; 	/* 0x00 SDRAMC Mode Register */
+	u32	tr; 	/* 0x04 SDRAMC Refresh Timer Register */
+	u32	cr; 	/* 0x08 SDRAMC Configuration Register */
+	u32	ssr; 	/* 0x0C SDRAMC Self Refresh Register */
+	u32	lpr; 	/* 0x10 SDRAMC Low Power Register */
+	u32	ier; 	/* 0x14 SDRAMC Interrupt Enable Register */
+	u32	idr; 	/* 0x18 SDRAMC Interrupt Disable Register */
+	u32	imr; 	/* 0x1C SDRAMC Interrupt Mask Register */
+	u32	icr; 	/* 0x20 SDRAMC Interrupt Status Register */
+	u32	reserved[3];
+} __attribute__ ((packed)) at91_sdramc_t;
+
+typedef struct at91_smc {
+	u32	csr[8]; 	/* 0x00 SDRAMC Mode Register */
+} __attribute__ ((packed)) at91_smc_t;
+
+#define AT91_SMC_CSR_RWHOLD(x)		((x & 0x7) << 28)
+#define AT91_SMC_CSR_RWSETUP(x)		((x & 0x7) << 24)
+#define AT91_SMC_CSR_ACSS_STANDARD	0x00000000
+#define AT91_SMC_CSR_ACSS_1CYCLE	0x00010000
+#define AT91_SMC_CSR_ACSS_2CYCLE	0x00020000
+#define AT91_SMC_CSR_ACSS_3CYCLE	0x00030000
+#define AT91_SMC_CSR_DRP		0x00008000
+#define AT91_SMC_CSR_DBW_8		0x00004000
+#define AT91_SMC_CSR_DBW_16		0x00002000
+#define AT91_SMC_CSR_BAT_8		0x00000000
+#define AT91_SMC_CSR_BAT_16		0x00001000
+#define AT91_SMC_CSR_TDF(x)		((x & 0xF) << 8)
+#define AT91_SMC_CSR_WSEN		0x00000080
+#define AT91_SMC_CSR_NWS(x)		(x & 0x7F)
+
+typedef struct at91_bfc {
+	u32	mr; 	/* 0x00 SDRAMC Mode Register */
+} __attribute__ ((packed)) at91_bfc_t;
+
+typedef struct at91_mc {
+	u32		rcr;		/* 0x00 MC Remap Control Register */
+	u32		asr;		/* 0x04 MC Abort Status Register */
+	u32		aasr;		/* 0x08 MC Abort Address Status Reg */
+	u32		mpr;		/* 0x0C MC Master Priority Register */
+	u32		reserved1[20];	/* 0x10-0x5C */
+	at91_ebi_t	ebi;		/* 0x60	- 0x6C EBI */
+	at91_smc_t	smc;		/* 0x70 - 0x8C SMC User Interface */
+	at91_sdramc_t	sdramc;		/* 0x90 - 0xBC SDRAMC User Interface */
+	at91_bfc_t	bfc;		/* 0xC0 BFC User Interface */
+	u32		reserved2[15];
+} __attribute__ ((packed)) at91_mc_t;
+
+#endif
+#endif
diff --git a/include/asm-arm/arch-at91/at91_pdc.h b/include/asm-arm/arch-at91/at91_pdc.h
new file mode 100644
index 0000000000..42f87caec1
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91_pdc.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef AT91_PDC_H
+#define AT91_PDC_H
+
+typedef struct at91_pdc {
+	u32	rpr;		/* 0x100 Receive Pointer Register */
+	u32	rcr;		/* 0x104 Receive Counter Register */
+	u32	tpr;		/* 0x108 Transmit Pointer Register */
+	u32	tcr;		/* 0x10C Transmit Counter Register */
+	u32	pnpr;		/* 0x110 Receive Next Pointer Register */
+	u32	pncr;		/* 0x114 Receive Next Counter Register */
+	u32	tnpr;		/* 0x118 Transmit Next Pointer Register */
+	u32	tncr;		/* 0x11C Transmit Next Counter Register */
+	u32	ptcr;		/* 0x120 Transfer Control Register */
+	u32	ptsr;		/* 0x124 Transfer Status Register */
+} at91_pdc_t;
+
+#endif
diff --git a/include/asm-arm/arch-at91/at91_pio.h b/include/asm-arm/arch-at91/at91_pio.h
index f6ce1f924e..f7915a3322 100644
--- a/include/asm-arm/arch-at91/at91_pio.h
+++ b/include/asm-arm/arch-at91/at91_pio.h
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
  *
  * Parallel I/O Controller (PIO) - System peripherals registers.
  * Based on AT91RM9200 datasheet revision E.
@@ -16,6 +17,115 @@
 #ifndef AT91_PIO_H
 #define AT91_PIO_H
 
+
+#define AT91_ASM_PIO_RANGE	0x200
+#define AT91_ASM_PIOC_ASR	\
+	(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
+#define AT91_ASM_PIOC_BSR	\
+	(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74)
+#define AT91_ASM_PIOC_PDR	\
+	(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04)
+#define AT91_ASM_PIOC_PUDR	\
+	(AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60)
+
+#define AT91_ASM_PIOD_PDR	\
+	(AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04)
+#define AT91_ASM_PIOD_PUDR	\
+	(AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60)
+#define AT91_ASM_PIOD_ASR	\
+	(AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_port {
+	u32	per;		/* 0x00 PIO Enable Register */
+	u32	pdr;		/* 0x04 PIO Disable Register */
+	u32	psr;		/* 0x08 PIO Status Register */
+	u32	reserved0;
+	u32	oer;		/* 0x10 Output Enable Register */
+	u32	odr;		/* 0x14 Output Disable Registerr */
+	u32	osr;		/* 0x18 Output Status Register */
+	u32	reserved1;
+	u32	ifer;		/* 0x20 Input Filter Enable Register */
+	u32	ifdr;		/* 0x24 Input Filter Disable Register */
+	u32	ifsr;		/* 0x28 Input Filter Status Register */
+	u32	reserved2;
+	u32	sodr;		/* 0x30 Set Output Data Register */
+	u32	codr;		/* 0x34 Clear Output Data Register */
+	u32	odsr;		/* 0x38 Output Data Status Register */
+	u32	pdsr;		/* 0x3C Pin Data Status Register */
+	u32	ier;		/* 0x40 Interrupt Enable Register */
+	u32	idr;		/* 0x44 Interrupt Disable Register */
+	u32	imr;		/* 0x48 Interrupt Mask Register */
+	u32	isr;		/* 0x4C Interrupt Status Register */
+	u32	mder;		/* 0x50 Multi-driver Enable Register */
+	u32	mddr;		/* 0x54 Multi-driver Disable Register */
+	u32	mdsr;		/* 0x58 Multi-driver Status Register */
+	u32	reserved3;
+	u32	pudr;		/* 0x60 Pull-up Disable Register */
+	u32	puer;		/* 0x64 Pull-up Enable Register */
+	u32	pusr;		/* 0x68 Pad Pull-up Status Register */
+	u32	reserved4;
+	u32	asr;		/* 0x70 Select A Register */
+	u32	bsr;		/* 0x74 Select B Register */
+	u32	absr;		/* 0x78 AB Select Status Register */
+	u32	reserved5[9];	/*  */
+	u32	ower;		/* 0xA0 Output Write Enable Register */
+	u32	owdr;		/* 0xA4 Output Write Disable Register */
+	u32	owsr;		/* OxA8 utput Write Status Register */
+	u32	reserved6[85];
+} at91_port_t;
+
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
+	defined(CONFIG_AT91SAM9G10) || defined(CONFIG_AT91SAM9G20)
+#define AT91_PIO_PORTS	3
+#elif defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) || \
+	defined(CONFIG_AT91SAM9M10G45)
+#define AT91_PIO_PORTS	5
+#elif defined(CONFIG_AT91RM9200) || defined(CONFIG_AT91CAP9) || \
+	defined(CONFIG_AT91SAM9RL)
+#define AT91_PIO_PORTS	4
+#else
+#error "Unsupported cpu. Please update at91_pio.h"
+#endif
+
+typedef union at91_pio {
+	struct {
+		at91_port_t	pioa;
+		at91_port_t	piob;
+		at91_port_t	pioc;
+	#if (AT91_PIO_PORTS > 3)
+		at91_port_t	piod;
+	#endif
+	#if (AT91_PIO_PORTS > 4)
+		at91_port_t	pioe;
+	#endif
+	} ;
+	at91_port_t port[AT91_PIO_PORTS];
+} at91_pio_t;
+
+#ifdef CONFIG_AT91_GPIO
+int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
+int at91_set_pio_output(unsigned port, unsigned pin, int value);
+int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
+int at91_set_pio_value(unsigned port, unsigned pin, int value);
+int at91_get_pio_value(unsigned port, unsigned pin);
+#endif
+#endif
+
+#define	AT91_PIO_PORTA		0x0
+#define	AT91_PIO_PORTB		0x1
+#define	AT91_PIO_PORTC		0x2
+#define	AT91_PIO_PORTD		0x3
+#define	AT91_PIO_PORTE		0x4
+
+#ifdef CONFIG_AT91_LEGACY
+
 #define PIO_PER		0x00	/* Enable Register */
 #define PIO_PDR		0x04	/* Disable Register */
 #define PIO_PSR		0x08	/* Status Register */
@@ -45,5 +155,6 @@
 #define PIO_OWER	0xa0	/* Output Write Enable Register */
 #define PIO_OWDR	0xa4	/* Output Write Disable Register */
 #define PIO_OWSR	0xa8	/* Output Write Status Register */
+#endif
 
 #endif
diff --git a/include/asm-arm/arch-at91/at91_pit.h b/include/asm-arm/arch-at91/at91_pit.h
index 94dd242a5f..5615a0206c 100644
--- a/include/asm-arm/arch-at91/at91_pit.h
+++ b/include/asm-arm/arch-at91/at91_pit.h
@@ -16,6 +16,20 @@
 #ifndef AT91_PIT_H
 #define AT91_PIT_H
 
+typedef struct at91_pit {
+	u32	mr;	/* 0x00 Mode Register */
+	u32	sr;	/* 0x04 Status Register */
+	u32	pivr;	/* 0x08 Periodic Interval Value Register */
+	u32	piir;	/* 0x0C Periodic Interval Image Register */
+} at91_pit_t;
+
+#define		AT91_PIT_MR_IEN		0x02000000
+#define		AT91_PIT_MR_EN		0x01000000
+#define		AT91_PIT_MR_PIV_MASK	(x & 0x000fffff)
+#define		AT91_PIT_MR_PIV(x)	(x & AT91_PIT_MR_PIV_MASK)
+
+#ifdef CONFIG_AT91_LEGACY
+
 #define AT91_PIT_MR		(AT91_PIT + 0x00)	/* Mode Register */
 #define		AT91_PIT_PITIEN		(1 << 25)		/* Timer Interrupt Enable */
 #define		AT91_PIT_PITEN		(1 << 24)		/* Timer Enabled */
@@ -29,4 +43,5 @@
 #define		AT91_PIT_PICNT		(0xfff << 20)		/* Interval Counter */
 #define		AT91_PIT_CPIV		(0xfffff)		/* Inverval Value */
 
+#endif /* CONFIG_AT91_LEGACY */
 #endif
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index 9fe94c7e4c..680fe33270 100644
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
  *
  * Power Management Controller (PMC) - System peripherals registers.
  * Based on AT91RM9200 datasheet revision E.
@@ -16,6 +17,98 @@
 #ifndef AT91_PMC_H
 #define AT91_PMC_H
 
+#define	AT91_ASM_PMC_MOR	(AT91_PMC_BASE + 0x20)
+#define	AT91_ASM_PMC_PLLAR	(AT91_PMC_BASE + 0x28)
+#define	AT91_ASM_PMC_PLLBR	(AT91_PMC_BASE + 0x2c)
+#define AT91_ASM_PMC_MCKR	(AT91_PMC_BASE + 0x30)
+#define AT91_ASM_PMC_SR		(AT91_PMC_BASE + 0x68)
+
+#ifndef __ASSEMBLY__
+
+#include <asm/types.h>
+
+typedef struct at91_pmc {
+	u32	scer;		/* 0x00 System Clock Enable Register */
+	u32	scdr;		/* 0x04 System Clock Disable Register */
+	u32	scsr;		/* 0x08 System Clock Status Register */
+	u32	reserved0;
+	u32	pcer;		/* 0x10 Peripheral Clock Enable Register */
+	u32	pcdr;		/* 0x14 Peripheral Clock Disable Register */
+	u32	pcsr;		/* 0x18 Peripheral Clock Status Register */
+	u32	reserved1;
+	u32	mor;		/* 0x20 Main Oscilator Register */
+	u32	mcfr;		/* 0x24 Main Clock Frequency Register */
+	u32	pllar;		/* 0x28 PLL A Register */
+	u32	pllbr;		/* 0x2C PLL B Register */
+	u32	mckr;		/* 0x30 Master Clock Register */
+	u32	reserved2[3];
+	u32	pck[4];		/* 0x40 Programmable Clock Register 0 - 3 */
+	u32	reserved3[4];
+	u32	ier;		/* 0x60 Interrupt Enable Register */
+	u32	idr;		/* 0x64 Interrupt Disable Register */
+	u32	sr;		/* 0x68 Status Register */
+	u32	imr;		/* 0x6C Interrupt Mask Register */
+	u32	reserved4[4];
+	u32	pllicpr;	/* 0x80 Change Pump Current Register (SAM9) */
+	u32	reserved5[21];
+	u32	wpmr;		/* 0xE4 Write Protect Mode Register (CAP0) */
+	u32	wpsr;		/* 0xE8 Write Protect Status Register (CAP0) */
+	u32	reserved8[5];
+} at91_pmc_t;
+
+#endif	/* end not assembly */
+
+#define AT91_PMC_MOR_MOSCEN		0x01
+#define AT91_PMC_MOR_OSCBYPASS		0x02
+#define AT91_PMC_MOR_OSCOUNT(x)		((x & 0xff) << 8)
+
+#define AT91_PMC_PLLXR_DIV(x)		(x & 0xFF)
+#define AT91_PMC_PLLXR_PLLCOUNT(x)	((x & 0x3F) << 8)
+#define AT91_PMC_PLLXR_OUT(x)		((x & 0x03) << 14)
+#define AT91_PMC_PLLXR_MUL(x)		((x & 0x7FF) << 16)
+#define AT91_PMC_PLLAR_29		0x20000000
+#define AT91_PMC_PLLBR_USBDIV_1		0x00000000
+#define AT91_PMC_PLLBR_USBDIV_2		0x10000000
+#define AT91_PMC_PLLBR_USBDIV_4		0x20000000
+
+#define AT91_PMC_MCFR_MAINRDY		0x00010000
+#define AT91_PMC_MCFR_MAINF_MASK	0x0000FFFF
+
+#define AT91_PMC_MCKR_CSS_SLOW		0x00000000
+#define AT91_PMC_MCKR_CSS_MAIN		0x00000001
+#define AT91_PMC_MCKR_CSS_PLLA		0x00000002
+#define AT91_PMC_MCKR_CSS_PLLB		0x00000003
+#define AT91_PMC_MCKR_CSS_MASK		0x00000003
+
+#define AT91_PMC_MCKR_PRES_1		0x00000000
+#define AT91_PMC_MCKR_PRES_2		0x00000004
+#define AT91_PMC_MCKR_PRES_4		0x00000008
+#define AT91_PMC_MCKR_PRES_8		0x0000000C
+#define AT91_PMC_MCKR_PRES_16		0x00000010
+#define AT91_PMC_MCKR_PRES_32		0x00000014
+#define AT91_PMC_MCKR_PRES_64		0x00000018
+#define AT91_PMC_MCKR_PRES_MASK		0x0000001C
+
+#define AT91_PMC_MCKR_MDIV_1		0x00000000
+#define AT91_PMC_MCKR_MDIV_2		0x00000100
+#define AT91_PMC_MCKR_MDIV_4		0x00000200
+#define AT91_PMC_MCKR_MDIV_MASK		0x00000300
+
+#define AT91_PMC_MCKR_PLLADIV_1		0x00001000
+#define AT91_PMC_MCKR_PLLADIV_2		0x00002000
+
+#define AT91_PMC_IXR_MOSCS		0x00000001
+#define AT91_PMC_IXR_LOCKA		0x00000002
+#define AT91_PMC_IXR_LOCKB		0x00000004
+#define AT91_PMC_IXR_MCKRDY		0x00000008
+#define AT91_PMC_IXR_LOCKU		0x00000040
+#define AT91_PMC_IXR_PCKRDY0		0x00000100
+#define AT91_PMC_IXR_PCKRDY1		0x00000200
+#define AT91_PMC_IXR_PCKRDY2		0x00000400
+#define AT91_PMC_IXR_PCKRDY3		0x00000800
+
+#ifdef CONFIG_AT91_LEGACY
+
 #define	AT91_PMC_SCER		(AT91_PMC + 0x00)	/* System Clock Enable Register */
 #define	AT91_PMC_SCDR		(AT91_PMC + 0x04)	/* System Clock Disable Register */
 
@@ -117,4 +210,5 @@
 
 #define AT91_PMC_VER		(AT91_PMC + 0xfc)	/* PMC Module Version [AT91CAP9 only] */
 
+#endif /* CONFIG_AT91_LEGACY */
 #endif
diff --git a/include/asm-arm/arch-at91/at91_rstc.h b/include/asm-arm/arch-at91/at91_rstc.h
index e49caef921..9ff2c5b7ac 100644
--- a/include/asm-arm/arch-at91/at91_rstc.h
+++ b/include/asm-arm/arch-at91/at91_rstc.h
@@ -16,11 +16,37 @@
 #ifndef AT91_RSTC_H
 #define AT91_RSTC_H
 
+#define AT91_ASM_RSTC_MR	(AT91_RSTC_BASE + 0x08)
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_rstc {
+	u32	cr;	/* Reset Controller Control Register */
+	u32	sr;	/* Reset Controller Status Register */
+	u32	mr;	/* Reset Controller Mode Register */
+} at91_rstc_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_RSTC_KEY		0xA5000000
+
+#define AT91_RSTC_CR_PROCRST	0x00000001
+#define AT91_RSTC_CR_PERRST	0x00000004
+#define AT91_RSTC_CR_EXTRST	0x00000008
+
+#define AT91_RSTC_MR_URSTEN	0x00000001
+#define AT91_RSTC_MR_URSTIEN	0x00000010
+#define AT91_RSTC_MR_ERSTL(x)	((x & 0xf) << 8)
+#define AT91_RSTC_MR_ERSTL_MASK	0x0000FF00
+
+#define AT91_RSTC_SR_NRSTL	0x00010000
+
+#ifdef CONFIG_AT91_LEGACY
+
 #define AT91_RSTC_CR		(AT91_RSTC + 0x00)	/* Reset Controller Control Register */
 #define		AT91_RSTC_PROCRST	(1 << 0)		/* Processor Reset */
 #define		AT91_RSTC_PERRST	(1 << 2)		/* Peripheral Reset */
 #define		AT91_RSTC_EXTRST	(1 << 3)		/* External Reset */
-#define		AT91_RSTC_KEY		(0xa5 << 24)		/* KEY Password */
 
 #define AT91_RSTC_SR		(AT91_RSTC + 0x04)	/* Reset Controller Status Register */
 #define		AT91_RSTC_URSTS		(1 << 0)		/* User Reset Status */
@@ -38,4 +64,6 @@
 #define		AT91_RSTC_URSTIEN	(1 << 4)		/* User Reset Interrupt Enable */
 #define		AT91_RSTC_ERSTL		(0xf << 8)		/* External Reset Length */
 
+#endif /* CONFIG_AT91_LEGACY */
+
 #endif
diff --git a/include/asm-arm/arch-at91/at91_spi.h b/include/asm-arm/arch-at91/at91_spi.h
index 30643c6092..c520e89d2b 100644
--- a/include/asm-arm/arch-at91/at91_spi.h
+++ b/include/asm-arm/arch-at91/at91_spi.h
@@ -16,6 +16,25 @@
 #ifndef AT91_SPI_H
 #define AT91_SPI_H
 
+#include <asm/arch/at91_pdc.h>
+
+typedef struct at91_spi {
+	u32		cr;		/* 0x00 Control Register */
+	u32		mr;		/* 0x04 Mode Register */
+	u32		rdr;		/* 0x08 Receive Data Register */
+	u32		tdr;		/* 0x0C Transmit Data Register */
+	u32		sr;		/* 0x10 Status Register */
+	u32		ier;		/* 0x14 Interrupt Enable Register */
+	u32		idr;		/* 0x18 Interrupt Disable Register */
+	u32		imr;		/* 0x1C Interrupt Mask Register */
+	u32		reserve1[4];
+	u32		csr[4];		/* 0x30 Chip Select Register 0-3 */
+	u32		reserve2[48];
+	at91_pdc_t	pdc;
+} at91_spi_t;
+
+#ifdef CONFIG_AT91_LEGACY
+
 #define AT91_SPI_CR			0x00		/* Control Register */
 #define		AT91_SPI_SPIEN		(1 <<  0)		/* SPI Enable */
 #define		AT91_SPI_SPIDIS		(1 <<  1)		/* SPI Disable */
@@ -102,4 +121,6 @@
 
 #define AT91_SPI_PTSR		0x0124			/* PDC Transfer Status Register */
 
+#endif /* CONFIG_AT91_LEGACY */
+
 #endif
diff --git a/include/asm-arm/arch-at91/at91_st.h b/include/asm-arm/arch-at91/at91_st.h
new file mode 100644
index 0000000000..53f932085b
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91_st.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef AT91_ST_H
+#define AT91_ST_H
+
+typedef struct at91_st {
+
+	u32	cr;
+	u32	pimr;
+	u32	wdmr;
+	u32	rtmr;
+	u32	sr;
+	u32	ier;
+	u32	idr;
+	u32	imr;
+	u32	rtar;
+	u32	crtr;
+} __attribute__ ((packed)) at91_st_t ;
+
+#define AT91_ST_CR_WDRST	1
+
+#define AT91_ST_WDMR_WDV(x)	(x & 0xFFFF)
+#define AT91_ST_WDMR_RSTEN	0x00010000
+#define AT91_ST_WDMR_EXTEN 	0x00020000
+
+#endif
diff --git a/include/asm-arm/arch-at91/at91_tc.h b/include/asm-arm/arch-at91/at91_tc.h
new file mode 100644
index 0000000000..1e180adb3c
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91_tc.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef AT91_TC_H
+#define AT91_TC_H
+
+typedef struct at91_tcc {
+	u32		ccr;	/* 0x00 Channel Control Register */
+	u32		cmr;	/* 0x04 Channel Mode Register */
+	u32		reserved1[2];
+	u32		cv;	/* 0x10 Counter Value */
+	u32		ra;	/* 0x14 Register A */
+	u32		rb;	/* 0x18 Register B */
+	u32		rc;	/* 0x1C Register C */
+	u32		sr;	/* 0x20 Status Register */
+	u32		ier;	/* 0x24 Interrupt Enable Register */
+	u32		idr;	/* 0x28 Interrupt Disable Register */
+	u32		imr;	/* 0x2C Interrupt Mask Register */
+	u32		reserved3[4];
+} __attribute__ ((packed)) at91_tcc_t;
+
+#define AT91_TC_CCR_CLKEN		0x00000001
+#define AT91_TC_CCR_CLKDIS		0x00000002
+#define AT91_TC_CCR_SWTRG		0x00000004
+
+#define AT91_TC_CMR_CPCTRG		0x00004000
+
+#define AT91_TC_CMR_TCCLKS_CLOCK1	0x00000000
+#define AT91_TC_CMR_TCCLKS_CLOCK2	0x00000001
+#define AT91_TC_CMR_TCCLKS_CLOCK3	0x00000002
+#define AT91_TC_CMR_TCCLKS_CLOCK4	0x00000003
+#define AT91_TC_CMR_TCCLKS_CLOCK5	0x00000004
+#define AT91_TC_CMR_TCCLKS_XC0		0x00000005
+#define AT91_TC_CMR_TCCLKS_XC1		0x00000006
+#define AT91_TC_CMR_TCCLKS_XC2		0x00000007
+
+typedef struct at91_tc {
+	at91_tcc_t	tc[3];	/* 0x00 TC Channel 0-2 */
+	u32		bcr;	/* 0xC0 TC Block Control Register */
+	u32		bmr;	/* 0xC4 TC Block Mode Register */
+} __attribute__ ((packed)) at91_tc_t;
+
+#define AT91_TC_BMR_TC0XC0S_TCLK0	0x00000000
+#define AT91_TC_BMR_TC0XC0S_NONE	0x00000001
+#define AT91_TC_BMR_TC0XC0S_TIOA1	0x00000002
+#define AT91_TC_BMR_TC0XC0S_TIOA2	0x00000003
+
+#define AT91_TC_BMR_TC1XC1S_TCLK1	0x00000000
+#define AT91_TC_BMR_TC1XC1S_NONE	0x00000004
+#define AT91_TC_BMR_TC1XC1S_TIOA0	0x00000008
+#define AT91_TC_BMR_TC1XC1S_TIOA2	0x0000000C
+
+#define AT91_TC_BMR_TC2XC2S_TCLK2	0x00000000
+#define AT91_TC_BMR_TC2XC2S_NONE	0x00000010
+#define AT91_TC_BMR_TC2XC2S_TIOA0	0x00000020
+#define AT91_TC_BMR_TC2XC2S_TIOA1	0x00000030
+
+#endif
diff --git a/include/asm-arm/arch-at91/at91_wdt.h b/include/asm-arm/arch-at91/at91_wdt.h
index 7e18537cfb..cf08dafdd8 100644
--- a/include/asm-arm/arch-at91/at91_wdt.h
+++ b/include/asm-arm/arch-at91/at91_wdt.h
@@ -17,6 +17,34 @@
 #ifndef AT91_WDT_H
 #define AT91_WDT_H
 
+#ifdef __ASSEMBLY__
+
+#define AT91_ASM_WDT_MR	(AT91_WDT_BASE +  0x04)
+
+#else
+
+typedef struct at91_wdt {
+	u32	cr;
+	u32	mr;
+	u32	sr;
+} at91_wdt_t;
+
+#endif
+
+#define AT91_WDT_CR_WDRSTT		1
+#define AT91_WDT_CR_KEY			0xa5000000	/* KEY Password */
+
+#define AT91_WDT_MR_WDV(x)		(x & 0xfff)
+#define AT91_WDT_MR_WDFIEN		0x00001000
+#define AT91_WDT_MR_WDRSTEN		0x00002000
+#define AT91_WDT_MR_WDRPROC		0x00004000
+#define AT91_WDT_MR_WDDIS		0x00008000
+#define AT91_WDT_MR_WDD(x)		((x & 0xfff) << 16)
+#define AT91_WDT_MR_WDDBGHLT		0x10000000
+#define AT91_WDT_MR_WDIDLEHLT		0x20000000
+
+#ifdef CONFIG_AT91_LEGACY
+
 #define AT91_WDT_CR		(AT91_WDT + 0x00)	/* Watchdog Control Register */
 #define		AT91_WDT_WDRSTT		(1    << 0)		/* Restart */
 #define		AT91_WDT_KEY		(0xa5 << 24)		/* KEY Password */
@@ -35,4 +63,5 @@
 #define		AT91_WDT_WDUNF		(1 << 0)		/* Watchdog Underflow */
 #define		AT91_WDT_WDERR		(1 << 1)		/* Watchdog Error */
 
+#endif /* CONFIG_AT91_LEGACY */
 #endif
diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h
index b128ac5a39..5af6fdc251 100644
--- a/include/asm-arm/arch-at91/at91cap9.h
+++ b/include/asm-arm/arch-at91/at91cap9.h
@@ -53,6 +53,13 @@
 #define AT91CAP9_ID_IRQ0	30	/* Advanced Interrupt Controller (IRQ0) */
 #define AT91CAP9_ID_IRQ1	31	/* Advanced Interrupt Controller (IRQ1) */
 
+#define AT91_PIO_BASE	0xfffff200
+#define AT91_PMC_BASE	0xfffffc00
+#define AT91_RSTC_BASE	0xfffffd00
+#define AT91_PIT_BASE	0xfffffd30
+
+#ifdef CONFIG_AT91_LEGACY
+
 /*
  * User Peripheral physical base addresses.
  */
@@ -119,6 +126,7 @@
 #define		AT91CAP9_SCKCR_OSCSEL_RC	(0 << 3)
 #define		AT91CAP9_SCKCR_OSCSEL_32	(1 << 3)
 
+#endif /* CONFIG_AT91_LEGACY */
 /*
  * Internal Memory.
  */
@@ -137,6 +145,6 @@
 /*
  * Cpu Name
  */
-#define AT91_CPU_NAME	"AT91CAP9"
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91CAP9"
 
 #endif
diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h
new file mode 100644
index 0000000000..1bee6f2b58
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91rm9200.h
@@ -0,0 +1,135 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __AT91RM9200_H__
+#define __AT91RM9200_H__
+
+/* Periperial Identifiers */
+
+#define AT91_ID_SYS	1	/* System Peripheral */
+#define AT91_ID_PIOA	2	/* PIO port A */
+#define AT91_ID_PIOB	3	/* PIO port B */
+#define AT91_ID_PIOC	4	/* PIO port C */
+#define AT91_ID_PIOD	5	/* PIO port D BGA only */
+#define AT91_ID_USART0	6	/* USART 0 */
+#define AT91_ID_USART1	7	/* USART 1 */
+#define AT91_ID_USART2	8	/* USART 2 */
+#define AT91_ID_USART3	9	/* USART 3 */
+#define AT91_ID_MCI	10	/* Multimedia Card Interface */
+#define AT91_ID_UDP	11	/* USB Device Port */
+#define AT91_ID_TWI	12	/* Two Wire Interface */
+#define AT91_ID_SPI	13	/* Serial Peripheral Interface */
+#define AT91_ID_SSC0	14	/* Synch. Serial Controller 0 */
+#define AT91_ID_SSC1	15	/* Synch. Serial Controller 1 */
+#define AT91_ID_SSC2	16	/* Synch. Serial Controller 2 */
+#define AT91_ID_TC0	17	/* Timer Counter 0 */
+#define AT91_ID_TC1	18	/* Timer Counter 1 */
+#define AT91_ID_TC2	19	/* Timer Counter 2 */
+#define AT91_ID_TC3	20	/* Timer Counter 3 */
+#define AT91_ID_TC4	21	/* Timer Counter 4 */
+#define AT91_ID_TC5	22	/* Timer Counter 5 */
+#define AT91_ID_UHP	23	/* OHCI USB Host Port */
+#define AT91_ID_EMAC	24	/* Ethernet MAC */
+#define AT91_ID_IRQ0	25	/* Advanced Interrupt Controller */
+#define AT91_ID_IRQ1	26	/* Advanced Interrupt Controller */
+#define AT91_ID_IRQ2	27	/* Advanced Interrupt Controller */
+#define AT91_ID_IRQ3	28	/* Advanced Interrupt Controller */
+#define AT91_ID_IRQ4	29	/* Advanced Interrupt Controller */
+#define AT91_ID_IRQ5	30	/* Advanced Interrupt Controller */
+#define AT91_ID_IRQ6	31	/* Advanced Interrupt Controller */
+
+#define AT91_USB_HOST_BASE	0x00300000
+
+#define AT91_TC_BASE		0xFFFA0000
+#define AT91_UDP_BASE		0xFFFB0000
+#define AT91_MCI_BASE		0xFFFB4000
+#define AT91_TWI_BASE		0xFFFB8000
+#define AT91_EMAC_BASE		0xFFFBC000
+#define AT91_USART_BASE		0xFFFC0000	/* 4x 0x4000 Offset */
+#define AT91_SCC_BASE		0xFFFD0000	/* 4x 0x4000 Offset */
+#define AT91_SPI_BASE		0xFFFE0000
+
+#define AT91_AIC_BASE		0xFFFFF000
+#define AT91_DBGU_BASE		0xFFFFF200
+#define AT91_PIO_BASE		0xFFFFF400	/* 4x 0x200 Offset */
+#define AT91_PMC_BASE		0xFFFFFC00
+#define AT91_ST_BASE		0xFFFFFD00
+#define AT91_ST_BASE		0xFFFFFD00
+#define AT91_RTC_BASE		0xFFFFFE00
+#define AT91_MC_BASE		0xFFFFFF00
+
+
+/* AT91RM9200 Periperial Multiplexing A */
+/* Port A */
+#define AT91_PMX_AA_EREFCK	0x00000080
+#define AT91_PMX_AA_ETXCK	0x00000080
+#define AT91_PMX_AA_ETXEN	0x00000100
+#define AT91_PMX_AA_ETX0	0x00000200
+#define AT91_PMX_AA_ETX1	0x00000400
+#define AT91_PMX_AA_ECRS	0x00000800
+#define AT91_PMX_AA_ECRSDV	0x00000800
+#define AT91_PMX_AA_ERX0	0x00001000
+#define AT91_PMX_AA_ERX1	0x00002000
+#define AT91_PMX_AA_ERXER	0x00004000
+#define AT91_PMX_AA_EMDC	0x00008000
+#define AT91_PMX_AA_EMDIO	0x00010000
+
+#define AT91_PMX_AA_TXD2	0x00810000
+
+#define AT91_PMX_AA_TWD		0x02000000
+#define AT91_PMX_AA_TWCK	0x04000000
+
+/* Port B */
+#define AT91_PMX_BA_ERXCK	0x00080000
+#define AT91_PMX_BA_ECOL	0x00040000
+#define AT91_PMX_BA_ERXDV	0x00020000
+#define AT91_PMX_BA_ERX3	0x00010000
+#define AT91_PMX_BA_ERX2 	0x00008000
+#define AT91_PMX_BA_ETXER	0x00004000
+#define AT91_PMX_BA_ETX3	0x00002000
+#define AT91_PMX_BA_ETX2	0x00001000
+
+/* Port B */
+
+#define AT91_PMX_CA_BFCK	0x00000001
+#define AT91_PMX_CA_BFRDY	0x00000002
+#define AT91_PMX_CA_SMOE	0x00000002
+#define AT91_PMX_CA_BFAVD	0x00000004
+#define AT91_PMX_CA_BFBAA	0x00000008
+#define AT91_PMX_CA_SMWE	0x00000008
+#define AT91_PMX_CA_BFOE	0x00000010
+#define AT91_PMX_CA_BFWE	0x00000020
+#define AT91_PMX_CA_NWAIT	0x00000040
+#define AT91_PMX_CA_A23		0x00000080
+#define AT91_PMX_CA_A24		0x00000100
+#define AT91_PMX_CA_A25		0x00000200
+#define AT91_PMX_CA_CFRNW	0x00000200
+#define AT91_PMX_CA_NCS4	0x00000400
+#define AT91_PMX_CA_CFCS	0x00000400
+#define AT91_PMX_CA_NCS5	0x00000800
+#define AT91_PMX_CA_CFCE1	0x00001000
+#define AT91_PMX_CA_NCS6	0x00001000
+#define AT91_PMX_CA_CFCE2	0x00002000
+#define AT91_PMX_CA_NCS7	0x00002000
+#define AT91_PMX_CA_D16_31	0xFFFF0000
+
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91RM9200"
+
+#endif
diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h
index 73975f484e..a60a0811c0 100644
--- a/include/asm-arm/arch-at91/at91sam9260.h
+++ b/include/asm-arm/arch-at91/at91sam9260.h
@@ -49,6 +49,18 @@
 #define AT91SAM9260_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
 #define AT91SAM9260_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
 
+#define AT91_EMAC_BASE		0xfffc4000
+#define AT91_SDRAMC_BASE	0xffffea00
+#define AT91_SMC_BASE		0xffffec00
+#define AT91_MATRIX_BASE	0xffffee00
+#define AT91_PIO_BASE		0xfffff400
+#define AT91_PMC_BASE		0xfffffc00
+#define AT91_RSTC_BASE		0xfffffd00
+#define AT91_PIT_BASE		0xfffffd30
+#define AT91_WDT_BASE		0xfffffd40
+
+#ifdef CONFIG_AT91_LEGACY
+
 /*
  * User Peripheral physical base addresses.
  */
@@ -105,6 +117,8 @@
 #define AT91_USART4	AT91SAM9260_BASE_US4
 #define AT91_USART5	AT91SAM9260_BASE_US5
 
+#endif /* CONFIG_AT91_LEGACY */
+
 /*
  * Internal Memory.
  */
@@ -125,9 +139,9 @@
  * Cpu Name
  */
 #if defined(CONFIG_AT91SAM9260)
-#define AT91_CPU_NAME	"AT91SAM9260"
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9260"
 #elif defined(CONFIG_AT91SAM9G20)
-#define AT91_CPU_NAME	"AT91SAM9G20"
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9G20"
 #endif
 
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h
index b303e07bbc..2952292c5d 100644
--- a/include/asm-arm/arch-at91/at91sam9261.h
+++ b/include/asm-arm/arch-at91/at91sam9261.h
@@ -43,6 +43,16 @@
 #define AT91SAM9261_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
 #define AT91SAM9261_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
 
+#define AT91_SDRAMC_BASE	0xffffea00
+#define AT91_SMC_BASE		0xffffec00
+#define AT91_MATRIX_BASE	0xffffee00
+#define AT91_PIO_BASE		0xfffff400
+#define AT91_PMC_BASE		0xfffffc00
+#define AT91_RSTC_BASE		0xfffffd00
+#define AT91_PIT_BASE		0xfffffd30
+#define AT91_WDT_BASE		0xfffffd40
+
+#ifdef CONFIG_AT91_LEGACY
 
 /*
  * User Peripheral physical base addresses.
@@ -64,7 +74,6 @@
 #define AT91SAM9261_BASE_SPI1		0xfffcc000
 #define AT91_BASE_SYS			0xffffea00
 
-
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
@@ -88,6 +97,7 @@
 #define AT91_USART1	AT91SAM9261_BASE_US1
 #define AT91_USART2	AT91SAM9261_BASE_US2
 
+#endif /* CONFIG_AT91_LEGACY */
 
 /*
  * Internal Memory.
@@ -104,6 +114,6 @@
 /*
  * Cpu Name
  */
-#define AT91_CPU_NAME	"AT91SAM9261"
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9261"
 
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h
index 966a6836fe..c177bd059e 100644
--- a/include/asm-arm/arch-at91/at91sam9263.h
+++ b/include/asm-arm/arch-at91/at91sam9263.h
@@ -47,6 +47,24 @@
 #define AT91SAM9263_ID_IRQ0	30	/* Advanced Interrupt Controller (IRQ0) */
 #define AT91SAM9263_ID_IRQ1	31	/* Advanced Interrupt Controller (IRQ1) */
 
+#define AT91_EMAC_BASE		0xfffbc000
+#define AT91_ECC0_BASE		0xffffe000
+#define AT91_SDRAMC0_BASE	0xffffe200
+#define AT91_SMC0_BASE		0xffffe400
+#define AT91_ECC1_BASE		0xffffe600
+#define AT91_SDRAMC1_BASE	0xffffe800
+#define AT91_SMC1_BASE		0xffffea00
+#define AT91_MATRIX_BASE	0xffffec00
+#define AT91_CCFG_BASE		0xffffed10
+#define AT91_DBGU_BASE		0xffffee00
+#define AT91_AIC_BASE		0xfffff000
+#define AT91_PIO_BASE		0xfffff200
+#define AT91_PMC_BASE		0xfffffc00
+#define AT91_RSTC_BASE		0xfffffd00
+#define AT91_PIT_BASE		0xfffffd30
+#define AT91_WDT_BASE		0xfffffd40
+
+#ifdef CONFIG_AT91_LEGACY
 
 /*
  * User Peripheral physical base addresses.
@@ -108,6 +126,8 @@
 #define AT91_SMC	AT91_SMC0
 #define AT91_SDRAMC	AT91_SDRAMC0
 
+#endif /* CONFIG_AT91_LEGACY */
+
 /*
  * Internal Memory.
  */
@@ -127,6 +147,6 @@
 /*
  * Cpu Name
  */
-#define AT91_CPU_NAME	"AT91SAM9263"
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9263"
 
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9_sdramc.h b/include/asm-arm/arch-at91/at91sam9_sdramc.h
index 5af2b54b12..c3da3a6a35 100644
--- a/include/asm-arm/arch-at91/at91sam9_sdramc.h
+++ b/include/asm-arm/arch-at91/at91sam9_sdramc.h
@@ -17,6 +17,19 @@
 #ifndef AT91SAM9_SDRAMC_H
 #define AT91SAM9_SDRAMC_H
 
+#ifdef __ASSEMBLY__
+
+#ifndef AT91_SDRAMC_BASE
+#define AT91_SDRAMC_BASE	AT91_SDRAMC0_BASE
+#endif
+
+#define AT91_ASM_SDRAMC_MR	AT91_SDRAMC_BASE
+#define AT91_ASM_SDRAMC_TR	(AT91_SDRAMC_BASE + 0x04)
+#define AT91_ASM_SDRAMC_CR	(AT91_SDRAMC_BASE + 0x08)
+#define AT91_ASM_SDRAMC_MDR	(AT91_SDRAMC_BASE + 0x24)
+
+#endif
+
 /* SDRAM Controller (SDRAMC) registers */
 #define AT91_SDRAMC_MR		(AT91_SDRAMC + 0x00)	/* SDRAM Controller Mode Register */
 #define		AT91_SDRAMC_MODE	(0xf << 0)		/* Command Mode */
diff --git a/include/asm-arm/arch-at91/at91sam9_smc.h b/include/asm-arm/arch-at91/at91sam9_smc.h
index d64511b36d..d180c8af87 100644
--- a/include/asm-arm/arch-at91/at91sam9_smc.h
+++ b/include/asm-arm/arch-at91/at91sam9_smc.h
@@ -16,6 +16,68 @@
 #ifndef AT91SAM9_SMC_H
 #define AT91SAM9_SMC_H
 
+#ifdef __ASSEMBLY__
+
+#ifndef AT91_SMC_BASE
+#define AT91_SMC_BASE	AT91_SMC0_BASE
+#endif
+
+#define AT91_ASM_SMC_SETUP0	AT91_SMC_BASE
+#define AT91_ASM_SMC_PULSE0	(AT91_SMC_BASE + 0x04)
+#define AT91_ASM_SMC_CYCLE0	(AT91_SMC_BASE + 0x08)
+#define AT91_ASM_SMC_MODE0	(AT91_SMC_BASE + 0x0C)
+
+#else
+
+typedef struct	at91_cs {
+	u32	setup;		/* 0x00 SMC Setup Register */
+	u32	pulse;		/* 0x04 SMC Pulse Register */
+	u32	cycle;		/* 0x08 SMC Cycle Register */
+	u32	mode;		/* 0x0C SMC Mode Register */
+} at91_cs_t;
+
+typedef struct	at91_smc {
+	at91_cs_t	cs[8];
+} at91_smc_t;
+
+#endif /*  __ASSEMBLY__ */
+
+#define AT91_SMC_SETUP_NWE(x)		(x & 0x3f)
+#define AT91_SMC_SETUP_NCS_WR(x)	((x & 0x3f) << 8)
+#define AT91_SMC_SETUP_NRD(x)		((x & 0x3f) << 16)
+#define AT91_SMC_SETUP_NCS_RD(x)	((x & 0x3f) << 24)
+
+#define AT91_SMC_PULSE_NWE(x)		(x & 0x7f)
+#define AT91_SMC_PULSE_NCS_WR(x)	((x & 0x7f) << 8)
+#define AT91_SMC_PULSE_NRD(x)		((x & 0x7f) << 16)
+#define AT91_SMC_PULSE_NCS_RD(x)	((x & 0x7f) << 24)
+
+#define AT91_SMC_CYCLE_NWE(x)		(x & 0x1ff)
+#define AT91_SMC_CYCLE_NRD(x)		((x & 0x1ff) << 16)
+
+#define AT91_SMC_MODE_RM_NCS		0x00000000
+#define AT91_SMC_MODE_RM_NRD		0x00000001
+#define AT91_SMC_MODE_WM_NCS		0x00000000
+#define AT91_SMC_MODE_WM_NWE		0x00000002
+
+#define AT91_SMC_MODE_EXNW_DISABLE	0x00000000
+#define AT91_SMC_MODE_EXNW_FROZEN	0x00000020
+#define AT91_SMC_MODE_EXNW_READY	0x00000030
+
+#define AT91_SMC_MODE_BAT		0x00000100
+#define AT91_SMC_MODE_DBW_8		0x00000000
+#define AT91_SMC_MODE_DBW_16		0x00001000
+#define AT91_SMC_MODE_DBW_32		0x00002000
+#define AT91_SMC_MODE_TDF_CYCLE(x)	((x & 0xf) << 16)
+#define AT91_SMC_MODE_TDF		0x00100000
+#define AT91_SMC_MODE_PMEN		0x01000000
+#define AT91_SMC_MODE_PS_4		0x00000000
+#define AT91_SMC_MODE_PS_8		0x10000000
+#define AT91_SMC_MODE_PS_16		0x20000000
+#define AT91_SMC_MODE_PS_32		0x30000000
+
+#ifdef CONFIG_AT91_LEGACY
+
 #define AT91_SMC_SETUP(n)	(AT91_SMC + 0x00 + ((n)*0x10))	/* Setup Register for CS n */
 #define		AT91_SMC_NWESETUP	(0x3f << 0)			/* NWE Setup Length */
 #define			AT91_SMC_NWESETUP_(x)	((x) << 0)
@@ -74,3 +136,4 @@
 #endif
 
 #endif
+#endif
diff --git a/include/asm-arm/arch-at91/at91sam9g45.h b/include/asm-arm/arch-at91/at91sam9g45.h
index 0feed9c28b..445f4b2123 100644
--- a/include/asm-arm/arch-at91/at91sam9g45.h
+++ b/include/asm-arm/arch-at91/at91sam9g45.h
@@ -51,6 +51,17 @@
 #define AT91SAM9G45_ID_VDEC	30	/* Video Decoder */
 #define AT91SAM9G45_ID_IRQ0	31	/* Advanced Interrupt Controller */
 
+#define AT91_EMAC_BASE		0xfffbc000
+#define AT91_SMC_BASE		0xffffe800
+#define AT91_MATRIX_BASE	0xffffea00
+#define AT91_PIO_BASE		0xfffff200
+#define AT91_PMC_BASE		0xfffffc00
+#define AT91_RSTC_BASE		0xfffffd00
+#define AT91_PIT_BASE		0xfffffd30
+#define AT91_WDT_BASE		0xfffffd40
+
+#ifdef CONFIG_AT91_LEGACY
+
 /*
  * User Peripheral physical base addresses.
  */
@@ -114,6 +125,8 @@
 #define AT91_USART2	AT91SAM9G45_BASE_US2
 #define AT91_USART3	AT91SAM9G45_BASE_US3
 
+#endif
+
 /*
  * Internal Memory.
  */
@@ -134,6 +147,6 @@
 /*
  * Cpu Name
  */
-#define AT91_CPU_NAME	"AT91SAM9G45"
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9G45"
 
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h
index 4dd8037c6e..8eb0d4fa29 100644
--- a/include/asm-arm/arch-at91/at91sam9rl.h
+++ b/include/asm-arm/arch-at91/at91sam9rl.h
@@ -44,6 +44,16 @@
 #define AT91SAM9RL_ID_AC97C	24	/* AC97 Controller */
 #define AT91SAM9RL_ID_IRQ0	31	/* Advanced Interrupt Controller (IRQ0) */
 
+#define AT91_SDRAMC_BASE	0xffffea00
+#define AT91_SMC_BASE		0xffffec00
+#define AT91_MATRIX_BASE	0xffffee00
+#define AT91_PIO_BASE		0xfffff400
+#define AT91_PMC_BASE		0xfffffc00
+#define AT91_RSTC_BASE		0xfffffd00
+#define AT91_PIT_BASE		0xfffffd30
+#define AT91_WDT_BASE		0xfffffd40
+
+#ifdef CONFIG_AT91_LEGACY
 
 /*
  * User Peripheral physical base addresses.
@@ -68,7 +78,6 @@
 #define AT91SAM9RL_BASE_AC97C	0xfffd8000
 #define AT91_BASE_SYS		0xffffc000
 
-
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
@@ -99,6 +108,7 @@
 #define AT91_USART2	AT91SAM9RL_BASE_US2
 #define AT91_USART3	AT91SAM9RL_BASE_US3
 
+#endif /* CONFIG_AT91_LEGACY */
 
 /*
  * Internal Memory.
@@ -115,6 +125,6 @@
 /*
  * Cpu Name
  */
-#define AT91_CPU_NAME	"AT91SAM9RL"
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9RL"
 
 #endif
diff --git a/include/asm-arm/arch-at91/gpio.h b/include/asm-arm/arch-at91/gpio.h
index e2d375b34c..716f81fa3c 100644
--- a/include/asm-arm/arch-at91/gpio.h
+++ b/include/asm-arm/arch-at91/gpio.h
@@ -18,6 +18,8 @@
 #include <asm/arch/at91_pio.h>
 #include <asm/arch/hardware.h>
 
+#ifdef CONFIG_AT91_LEGACY
+
 #define PIN_BASE		32
 
 #define MAX_GPIO_BANKS		5
@@ -214,154 +216,23 @@ static inline unsigned pin_to_mask(unsigned pin)
 	return 1 << (pin % 32);
 }
 
-/*
- * mux the pin to the "GPIO" peripheral role.
- */
-static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup)
-{
-	void		*pio = pin_to_controller(pin);
-	unsigned	mask = pin_to_mask(pin);
-
-	__raw_writel(mask, pio + PIO_IDR);
-	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-	__raw_writel(mask, pio + PIO_PER);
-	return 0;
-}
-
-/*
- * mux the pin to the "A" internal peripheral role.
- */
-static inline int at91_set_A_periph(unsigned pin, int use_pullup)
-{
-	void		*pio = pin_to_controller(pin);
-	unsigned	mask = pin_to_mask(pin);
-
-	__raw_writel(mask, pio + PIO_IDR);
-	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-	__raw_writel(mask, pio + PIO_ASR);
-	__raw_writel(mask, pio + PIO_PDR);
-	return 0;
-}
-
-/*
- * mux the pin to the "B" internal peripheral role.
- */
-static inline int at91_set_B_periph(unsigned pin, int use_pullup)
-{
-	void		*pio = pin_to_controller(pin);
-	unsigned	mask = pin_to_mask(pin);
-
-	__raw_writel(mask, pio + PIO_IDR);
-	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-	__raw_writel(mask, pio + PIO_BSR);
-	__raw_writel(mask, pio + PIO_PDR);
-	return 0;
-}
-
-/*
- * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
- * configure it for an input.
- */
-static inline int at91_set_gpio_input(unsigned pin, int use_pullup)
-{
-	void		*pio = pin_to_controller(pin);
-	unsigned	mask = pin_to_mask(pin);
-
-	__raw_writel(mask, pio + PIO_IDR);
-	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-	__raw_writel(mask, pio + PIO_ODR);
-	__raw_writel(mask, pio + PIO_PER);
-	return 0;
-}
-
-/*
- * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
- * and configure it for an output.
- */
-static inline int at91_set_gpio_output(unsigned pin, int value)
-{
-	void		*pio = pin_to_controller(pin);
-	unsigned	mask = pin_to_mask(pin);
-
-	__raw_writel(mask, pio + PIO_IDR);
-	__raw_writel(mask, pio + PIO_PUDR);
-	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
-	__raw_writel(mask, pio + PIO_OER);
-	__raw_writel(mask, pio + PIO_PER);
-	return 0;
-}
-
-/*
- * enable/disable the glitch filter; mostly used with IRQ handling.
- */
-static inline int at91_set_deglitch(unsigned pin, int is_on)
-{
-	void		*pio = pin_to_controller(pin);
-	unsigned	mask = pin_to_mask(pin);
-
-	__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
-	return 0;
-}
-
-/*
- * enable/disable the multi-driver; This is only valid for output and
- * allows the output pin to run as an open collector output.
- */
-static inline int at91_set_multi_drive(unsigned pin, int is_on)
-{
-	void		*pio = pin_to_controller(pin);
-	unsigned	mask = pin_to_mask(pin);
-
-	__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
-	return 0;
-}
-
-static inline int gpio_direction_input(unsigned pin)
-{
-	void		*pio = pin_to_controller(pin);
-	unsigned	mask = pin_to_mask(pin);
-
-	if (!(__raw_readl(pio + PIO_PSR) & mask))
-		return -EINVAL;
-	__raw_writel(mask, pio + PIO_ODR);
-	return 0;
-}
-
-static inline int gpio_direction_output(unsigned pin, int value)
-{
-	void		*pio = pin_to_controller(pin);
-	unsigned	mask = pin_to_mask(pin);
-
-	if (!(__raw_readl(pio + PIO_PSR) & mask))
-		return -EINVAL;
-	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
-	__raw_writel(mask, pio + PIO_OER);
-	return 0;
-}
-
-/*
- * assuming the pin is muxed as a gpio output, set its value.
- */
-static inline int at91_set_gpio_value(unsigned pin, int value)
-{
-	void		*pio = pin_to_controller(pin);
-	unsigned	mask = pin_to_mask(pin);
-
-	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
-	return 0;
-}
-
-/*
- * read the pin's value (works even if it's not muxed as a gpio).
- */
-static inline int at91_get_gpio_value(unsigned pin)
-{
-	void		*pio = pin_to_controller(pin);
-	unsigned	mask = pin_to_mask(pin);
-	u32		pdsr;
-
-	pdsr = __raw_readl(pio + PIO_PDSR);
-	return (pdsr & mask) != 0;
-}
-
+/* The following macros are need for backward compatibility */
+#define at91_set_GPIO_periph(x, y) \
+	at91_set_gpio_periph((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_A_periph(x, y) \
+	at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_B_periph(x, y) \
+	at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_gpio_output(x, y) \
+	at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_gpio_input(x, y) \
+	at91_set_pio_input((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_gpio_value(x, y) \
+	at91_set_pio_value((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_get_gpio_value(x) \
+	at91_get_pio_value((x - PIN_BASE) / 32,(x % 32))
+#else
+#define at91_set_gpio_value(x, y)	at91_set_pio_value(x, y)
+#define at91_get_gpio_value(x)		at91_get_pio_value(x)
+#endif
 #endif
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index de06a1004b..4ddb3155d7 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -17,7 +17,7 @@
 #include <asm/sizes.h>
 
 #if defined(CONFIG_AT91RM9200)
-#include <asm/arch/at91rm9200.h>
+#include <asm/arch-at91/at91rm9200.h>
 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
 #include <asm/arch/at91sam9260.h>
 #define AT91_BASE_SPI	AT91SAM9260_BASE_SPI0
diff --git a/include/asm-arm/arch-at91/io.h b/include/asm-arm/arch-at91/io.h
index f09b2df0e3..38d185eb7c 100644
--- a/include/asm-arm/arch-at91/io.h
+++ b/include/asm-arm/arch-at91/io.h
@@ -23,6 +23,8 @@
 
 #include <asm/io.h>
 
+#ifdef CONFIG_AT91_LEGACY
+
 static inline unsigned int at91_sys_read(unsigned int reg_offset)
 {
 	void *addr = (void *)AT91_BASE_SYS;
@@ -36,5 +38,6 @@ static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
 
 	__raw_writel(value, addr + reg_offset);
 }
+#endif
 
 #endif
diff --git a/include/asm-arm/arch-davinci/emac_defs.h b/include/asm-arm/arch-davinci/emac_defs.h
index 96bc80e476..b0ec8f5090 100644
--- a/include/asm-arm/arch-davinci/emac_defs.h
+++ b/include/asm-arm/arch-davinci/emac_defs.h
@@ -43,6 +43,13 @@
 #define EMAC_WRAPPER_BASE_ADDR		(0x01d0a000)
 #define EMAC_WRAPPER_RAM_ADDR		(0x01d08000)
 #define EMAC_MDIO_BASE_ADDR		(0x01d0b000)
+#define DAVINCI_EMAC_VERSION2
+#elif defined(CONFIG_SOC_DA8XX)
+#define EMAC_BASE_ADDR			DAVINCI_EMAC_CNTRL_REGS_BASE
+#define EMAC_WRAPPER_BASE_ADDR		DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
+#define EMAC_WRAPPER_RAM_ADDR		DAVINCI_EMAC_WRAPPER_RAM_BASE
+#define EMAC_MDIO_BASE_ADDR		DAVINCI_MDIO_CNTRL_REGS_BASE
+#define DAVINCI_EMAC_VERSION2
 #else
 #define EMAC_BASE_ADDR			(0x01c80000)
 #define EMAC_WRAPPER_BASE_ADDR		(0x01c81000)
@@ -51,6 +58,11 @@
 #endif
 
 #ifdef CONFIG_SOC_DM646X
+#define DAVINCI_EMAC_VERSION2
+#define DAVINCI_EMAC_GIG_ENABLE
+#endif
+
+#ifdef CONFIG_SOC_DM646X
 /* MDIO module input frequency */
 #define EMAC_MDIO_BUS_FREQ		76500000
 /* MDIO clock output frequency */
@@ -60,6 +72,11 @@
 #define EMAC_MDIO_BUS_FREQ		121500000
 /* MDIO clock output frequency */
 #define EMAC_MDIO_CLOCK_FREQ		2200000		/* 2.2 MHz */
+#elif defined(CONFIG_SOC_DA8XX)
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ		clk_get(DAVINCI_MDIO_CLKID)
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ		2000000		/* 2.0 MHz */
 #else
 /* MDIO module input frequency */
 #define EMAC_MDIO_BUS_FREQ		99000000	/* PLL/6 - 99 MHz */
@@ -128,6 +145,10 @@ typedef volatile struct _emac_desc
 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE	(0x1)
 #define EMAC_MACCONTROL_GIGABIT_ENABLE		(1 << 7)
 #define EMAC_MACCONTROL_GIGFORCE		(1 << 17)
+#define EMAC_MACCONTROL_RMIISPEED_100		(1 << 15)
+
+#define EMAC_MAC_ADDR_MATCH		(1 << 19)
+#define EMAC_MAC_ADDR_IS_VALID		(1 << 20)
 
 #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE	(0x200000)
 #define EMAC_RXMBPENABLE_RXBROADEN	(0x2000)
@@ -283,10 +304,40 @@ typedef struct  {
 
 /* EMAC Wrapper Registers Structure */
 typedef struct  {
-#if defined(CONFIG_SOC_DM646X) || defined(CONFIG_SOC_DM365)
-	dv_reg		IDVER;
-	dv_reg		SOFTRST;
-	dv_reg		EMCTRL;
+#ifdef DAVINCI_EMAC_VERSION2
+	dv_reg		idver;
+	dv_reg		softrst;
+	dv_reg		emctrl;
+	dv_reg		c0rxthreshen;
+	dv_reg		c0rxen;
+	dv_reg		c0txen;
+	dv_reg		c0miscen;
+	dv_reg		c1rxthreshen;
+	dv_reg		c1rxen;
+	dv_reg		c1txen;
+	dv_reg		c1miscen;
+	dv_reg		c2rxthreshen;
+	dv_reg		c2rxen;
+	dv_reg		c2txen;
+	dv_reg		c2miscen;
+	dv_reg		c0rxthreshstat;
+	dv_reg		c0rxstat;
+	dv_reg		c0txstat;
+	dv_reg		c0miscstat;
+	dv_reg		c1rxthreshstat;
+	dv_reg		c1rxstat;
+	dv_reg		c1txstat;
+	dv_reg		c1miscstat;
+	dv_reg		c2rxthreshstat;
+	dv_reg		c2rxstat;
+	dv_reg		c2txstat;
+	dv_reg		c2miscstat;
+	dv_reg		c0rximax;
+	dv_reg		c0tximax;
+	dv_reg		c1rximax;
+	dv_reg		c1tximax;
+	dv_reg		c2rximax;
+	dv_reg		c2tximax;
 #else
 	u_int8_t	RSVD0[4100];
 	dv_reg		EWCTL;
@@ -316,6 +367,7 @@ typedef struct  {
 
 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
+void davinci_eth_set_mac_addr(const u_int8_t *addr);
 
 typedef struct
 {
diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h
index 8fd4e01b8e..aa57703c68 100644
--- a/include/asm-arm/arch-davinci/emif_defs.h
+++ b/include/asm-arm/arch-davinci/emif_defs.h
@@ -24,7 +24,7 @@
 
 #include <asm/arch/hardware.h>
 
-typedef struct {
+typedef struct davinci_emif_regs {
 	dv_reg		ERCSR;
 	dv_reg		AWCCR;
 	dv_reg		SDBCR;
@@ -66,6 +66,9 @@ typedef struct {
 
 typedef emif_registers	*emifregs;
 
+#define davinci_emif_regs \
+	((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
+
 #define DAVINCI_NANDFCR_NAND_ENABLE(n)			(1 << (n-2))
 #define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK		(3 << 4)
 #define DAVINCI_NANDFCR_4BIT_ECC_SEL(n)			((n-2) << 4)
@@ -73,4 +76,17 @@ typedef emif_registers	*emifregs;
 #define DAVINCI_NANDFCR_4BIT_ECC_START			(1 << 12)
 #define DAVINCI_NANDFCR_4BIT_CALC_START			(1 << 13)
 
+/* Chip Select setup */
+#define DAVINCI_ABCR_STROBE_SELECT			(1 << 31)
+#define DAVINCI_ABCR_EXT_WAIT				(1 << 30)
+#define DAVINCI_ABCR_WSETUP(n)				(n << 26)
+#define DAVINCI_ABCR_WSTROBE(n)				(n << 20)
+#define DAVINCI_ABCR_WHOLD(n)				(n << 17)
+#define DAVINCI_ABCR_RSETUP(n)				(n << 13)
+#define DAVINCI_ABCR_RSTROBE(n)				(n << 7)
+#define DAVINCI_ABCR_RHOLD(n)				(n << 4)
+#define DAVINCI_ABCR_TA(n)				(n << 2)
+#define DAVINCI_ABCR_ASIZE_16BIT			1
+#define DAVINCI_ABCR_ASIZE_8BIT				0
+
 #endif
diff --git a/include/asm-arm/arch-mx25/clock.h b/include/asm-arm/arch-mx25/clock.h
new file mode 100644
index 0000000000..c59f588570
--- /dev/null
+++ b/include/asm-arm/arch-mx25/clock.h
@@ -0,0 +1,36 @@
+/*
+ *
+ * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
+ *
+ * Modified for mx25 by John Rigby <jrigby@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+ulong imx_get_perclk(int clk);
+ulong imx_get_ahbclk(void);
+
+#define imx_get_uartclk() imx_get_perclk(15)
+#define imx_get_fecclk() (imx_get_ahbclk()/2)
+
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/include/asm-arm/arch-mx25/imx-regs.h b/include/asm-arm/arch-mx25/imx-regs.h
new file mode 100644
index 0000000000..f709bd8e0e
--- /dev/null
+++ b/include/asm-arm/arch-mx25/imx-regs.h
@@ -0,0 +1,316 @@
+/*
+ * Copyright (C) 2009, DENX Software Engineering
+ * Author: John Rigby <jcrigby@gmail.com
+ *
+ *   Based on arch-mx31/mx31-regs.h
+ *	Copyright (C) 2009 Ilya Yanok,
+ *		Emcraft Systems <yanok@emcraft.com>
+ *   and arch-mx27/imx-regs.h
+ *	Copyright (C) 2007 Pengutronix,
+ *		Sascha Hauer <s.hauer@pengutronix.de>
+ *	Copyright (C) 2009 Ilya Yanok,
+ *		Emcraft Systems <yanok@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _IMX_REGS_H
+#define _IMX_REGS_H
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_FEC_MXC
+extern void mx25_fec_init_pins(void);
+#endif
+
+/* Clock Control Module (CCM) registers */
+struct ccm_regs {
+	u32 mpctl;	/* Core PLL Control */
+	u32 upctl;	/* USB PLL Control */
+	u32 cctl;	/* Clock Control */
+	u32 cgr0;	/* Clock Gating Control 0 */
+	u32 cgr1;	/* Clock Gating Control 1 */
+	u32 cgr2;	/* Clock Gating Control 2 */
+	u32 pcdr[4];	/* PER Clock Dividers */
+	u32 rcsr;	/* CCM Status */
+	u32 crdr;	/* CCM Reset and Debug */
+	u32 dcvr0;	/* DPTC Comparator Value 0 */
+	u32 dcvr1;	/* DPTC Comparator Value 1 */
+	u32 dcvr2;	/* DPTC Comparator Value 2 */
+	u32 dcvr3;	/* DPTC Comparator Value 3 */
+	u32 ltr0;	/* Load Tracking 0 */
+	u32 ltr1;	/* Load Tracking 1 */
+	u32 ltr2;	/* Load Tracking 2 */
+	u32 ltr3;	/* Load Tracking 3 */
+	u32 ltbr0;	/* Load Tracking Buffer 0 */
+	u32 ltbr1;	/* Load Tracking Buffer 1 */
+	u32 pcmr0;	/* Power Management Control 0 */
+	u32 pcmr1;	/* Power Management Control 1 */
+	u32 pcmr2;	/* Power Management Control 2 */
+	u32 mcr;	/* Miscellaneous Control */
+	u32 lpimr0;	/* Low Power Interrupt Mask 0 */
+	u32 lpimr1;	/* Low Power Interrupt Mask 1 */
+};
+
+/* Enhanced SDRAM Controller (ESDRAMC) registers */
+struct esdramc_regs {
+	u32 ctl0; 	/* control 0 */
+	u32 cfg0; 	/* configuration 0 */
+	u32 ctl1; 	/* control 1 */
+	u32 cfg1; 	/* configuration 1 */
+	u32 misc; 	/* miscellaneous */
+	u32 pad[3];
+	u32 cdly1;	/* Delay Line 1 configuration debug */
+	u32 cdly2;	/* delay line 2 configuration debug */
+	u32 cdly3;	/* delay line 3 configuration debug */
+	u32 cdly4;	/* delay line 4 configuration debug */
+	u32 cdly5;	/* delay line 5 configuration debug */
+	u32 cdlyl;	/* delay line cycle length debug */
+};
+
+/* GPIO registers */
+struct gpio_regs {
+	u32 dr;		/* data */
+	u32 dir;	/* direction */
+	u32 psr;	/* pad satus */
+	u32 icr1;	/* interrupt config 1 */
+	u32 icr2;	/* interrupt config 2 */
+	u32 imr;	/* interrupt mask */
+	u32 isr;	/* interrupt status */
+	u32 edge_sel;	/* edge select */
+};
+
+/* General Purpose Timer (GPT) registers */
+struct gpt_regs {
+	u32 ctrl;   	/* control */
+	u32 pre;    	/* prescaler */
+	u32 stat;   	/* status */
+	u32 intr;   	/* interrupt */
+	u32 cmp[3]; 	/* output compare 1-3 */
+	u32 capt[2];	/* input capture 1-2 */
+	u32 counter;	/* counter */
+};
+
+/* Watchdog Timer (WDOG) registers */
+struct wdog_regs {
+	u32 wcr;	/* Control */
+	u32 wsr;	/* Service */
+	u32 wrsr;	/* Reset Status */
+	u32 wicr;	/* Interrupt Control */
+	u32 wmcr;	/* Misc Control */
+};
+
+/* IIM control registers */
+struct iim_regs {
+	u32 iim_stat;
+	u32 iim_statm;
+	u32 iim_err;
+	u32 iim_emask;
+	u32 iim_fctl;
+	u32 iim_ua;
+	u32 iim_la;
+	u32 iim_sdat;
+	u32 iim_prev;
+	u32 iim_srev;
+	u32 iim_prog_p;
+	u32 res1[0x1f5];
+	u32 iim_bank_area0[0x20];
+	u32 res2[0xe0];
+	u32 iim_bank_area1[0x20];
+	u32 res3[0xe0];
+	u32 iim_bank_area2[0x20];
+};
+#endif
+
+/* AIPS 1 */
+#define IMX_AIPS1_BASE		(0x43F00000)
+#define IMX_MAX_BASE		(0x43F04000)
+#define IMX_CLKCTL_BASE		(0x43F08000)
+#define IMX_ETB_SLOT4_BASE	(0x43F0C000)
+#define IMX_ETB_SLOT5_BASE	(0x43F10000)
+#define IMX_ECT_CTIO_BASE	(0x43F18000)
+#define IMX_I2C_BASE		(0x43F80000)
+#define IMX_I2C3_BASE		(0x43F84000)
+#define IMX_CAN1_BASE		(0x43F88000)
+#define IMX_CAN2_BASE		(0x43F8C000)
+#define IMX_UART1_BASE		(0x43F90000)
+#define IMX_UART2_BASE		(0x43F94000)
+#define IMX_I2C2_BASE		(0x43F98000)
+#define IMX_OWIRE_BASE		(0x43F9C000)
+#define IMX_CSPI1_BASE		(0x43FA4000)
+#define IMX_KPP_BASE		(0x43FA8000)
+#define IMX_IOPADMUX_BASE	(0x43FAC000)
+#define IMX_IOPADCTL_BASE	(0x43FAC22C)
+#define IMX_IOPADGRPCTL_BASE	(0x43FAC418)
+#define IMX_IOPADINPUTSEL_BASE	(0x43FAC460)
+#define IMX_AUDMUX_BASE		(0x43FB0000)
+#define IMX_ECT_IP1_BASE	(0x43FB8000)
+#define IMX_ECT_IP2_BASE	(0x43FBC000)
+
+/* SPBA */
+#define IMX_SPBA_BASE		(0x50000000)
+#define IMX_CSPI3_BASE		(0x50004000)
+#define IMX_UART4_BASE		(0x50008000)
+#define IMX_UART3_BASE		(0x5000C000)
+#define IMX_CSPI2_BASE		(0x50010000)
+#define IMX_SSI2_BASE		(0x50014000)
+#define IMX_ESAI_BASE		(0x50018000)
+#define IMX_ATA_DMA_BASE	(0x50020000)
+#define IMX_SIM1_BASE		(0x50024000)
+#define IMX_SIM2_BASE		(0x50028000)
+#define IMX_UART5_BASE		(0x5002C000)
+#define IMX_TSC_BASE		(0x50030000)
+#define IMX_SSI1_BASE		(0x50034000)
+#define IMX_FEC_BASE		(0x50038000)
+#define IMX_SPBA_CTRL_BASE	(0x5003C000)
+
+/* AIPS 2 */
+#define IMX_AIPS2_BASE		(0x53F00000)
+#define IMX_CCM_BASE		(0x53F80000)
+#define IMX_GPT4_BASE		(0x53F84000)
+#define IMX_GPT3_BASE		(0x53F88000)
+#define IMX_GPT2_BASE		(0x53F8C000)
+#define IMX_GPT1_BASE		(0x53F90000)
+#define IMX_EPIT1_BASE		(0x53F94000)
+#define IMX_EPIT2_BASE		(0x53F98000)
+#define IMX_GPIO4_BASE		(0x53F9C000)
+#define IMX_PWM2_BASE		(0x53FA0000)
+#define IMX_GPIO3_BASE		(0x53FA4000)
+#define IMX_PWM3_BASE		(0x53FA8000)
+#define IMX_SCC_BASE		(0x53FAC000)
+#define IMX_SCM_BASE		(0x53FAE000)
+#define IMX_SMN_BASE		(0x53FAF000)
+#define IMX_RNGD_BASE		(0x53FB0000)
+#define IMX_MMC_SDHC1_BASE	(0x53FB4000)
+#define IMX_MMC_SDHC2_BASE	(0x53FB8000)
+#define IMX_LCDC_BASE		(0x53FBC000)
+#define IMX_SLCDC_BASE		(0x53FC0000)
+#define IMX_PWM4_BASE		(0x53FC8000)
+#define IMX_GPIO1_BASE		(0x53FCC000)
+#define IMX_GPIO2_BASE		(0x53FD0000)
+#define IMX_SDMA_BASE		(0x53FD4000)
+#define IMX_WDT_BASE		(0x53FDC000)
+#define IMX_PWM1_BASE		(0x53FE0000)
+#define IMX_RTIC_BASE		(0x53FEC000)
+#define IMX_IIM_BASE		(0x53FF0000)
+#define IMX_USB_BASE		(0x53FF4000)
+#define IMX_CSI_BASE		(0x53FF8000)
+#define IMX_DRYICE_BASE		(0x53FFC000)
+
+#define IMX_ARM926_ROMPATCH	(0x60000000)
+#define IMX_ARM926_ASIC		(0x68000000)
+
+/* 128K Internal Static RAM */
+#define IMX_RAM_BASE		(0x78000000)
+
+/* SDRAM BANKS */
+#define IMX_SDRAM_BANK0_BASE	(0x80000000)
+#define IMX_SDRAM_BANK1_BASE	(0x90000000)
+
+#define IMX_WEIM_CS0		(0xA0000000)
+#define IMX_WEIM_CS1		(0xA8000000)
+#define IMX_WEIM_CS2		(0xB0000000)
+#define IMX_WEIM_CS3		(0xB2000000)
+#define IMX_WEIM_CS4		(0xB4000000)
+#define IMX_ESDRAMC_BASE	(0xB8001000)
+#define IMX_WEIM_CTRL_BASE	(0xB8002000)
+#define IMX_M3IF_CTRL_BASE	(0xB8003000)
+#define IMX_EMI_CTRL_BASE	(0xB8004000)
+
+/* NAND Flash Controller */
+#define IMX_NFC_BASE		(0xBB000000)
+#define NFC_BASE_ADDR		IMX_NFC_BASE
+
+/* CCM bitfields */
+#define CCM_PLL_MFI_SHIFT	10
+#define CCM_PLL_MFI_MASK	0xf
+#define CCM_PLL_MFN_SHIFT	0
+#define CCM_PLL_MFN_MASK	0x3ff
+#define CCM_PLL_MFD_SHIFT	16
+#define CCM_PLL_MFD_MASK	0x3ff
+#define CCM_PLL_PD_SHIFT	26
+#define CCM_PLL_PD_MASK		0xf
+#define CCM_CCTL_ARM_DIV_SHIFT	30
+#define CCM_CCTL_ARM_DIV_MASK	3
+#define CCM_CCTL_AHB_DIV_SHIFT	28
+#define CCM_CCTL_AHB_DIV_MASK	3
+#define CCM_CCTL_ARM_SRC	(1 << 14)
+#define CCM_CGR1_GPT1		(1 << 19)
+#define CCM_PERCLK_REG(clk)	(clk / 4)
+#define CCM_PERCLK_SHIFT(clk)	(8 * (clk % 4))
+#define CCM_PERCLK_MASK		0x3f
+#define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
+#define CCM_RCSR_NF_PS(v)	((v >> 26) & 3)
+
+/* ESDRAM Controller register bitfields */
+#define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
+#define ESDCTL_BL		(1 << 7)
+#define ESDCTL_FP		(1 << 8)
+#define ESDCTL_PWDT(x)		(((x) & 3) << 10)
+#define ESDCTL_SREFR(x)		(((x) & 7) << 13)
+#define ESDCTL_DSIZ_16_UPPER	(0 << 16)
+#define ESDCTL_DSIZ_16_LOWER	(1 << 16)
+#define ESDCTL_DSIZ_32		(2 << 16)
+#define ESDCTL_COL8		(0 << 20)
+#define ESDCTL_COL9		(1 << 20)
+#define ESDCTL_COL10		(2 << 20)
+#define ESDCTL_ROW11		(0 << 24)
+#define ESDCTL_ROW12		(1 << 24)
+#define ESDCTL_ROW13		(2 << 24)
+#define ESDCTL_ROW14		(3 << 24)
+#define ESDCTL_ROW15		(4 << 24)
+#define ESDCTL_SP		(1 << 27)
+#define ESDCTL_SMODE_NORMAL	(0 << 28)
+#define ESDCTL_SMODE_PRECHARGE	(1 << 28)
+#define ESDCTL_SMODE_AUTO_REF	(2 << 28)
+#define ESDCTL_SMODE_LOAD_MODE	(3 << 28)
+#define ESDCTL_SMODE_MAN_REF	(4 << 28)
+#define ESDCTL_SDE		(1 << 31)
+
+#define ESDCFG_TRC(x)		(((x) & 0xf) << 0)
+#define ESDCFG_TRCD(x)		(((x) & 0x7) << 4)
+#define ESDCFG_TCAS(x)		(((x) & 0x3) << 8)
+#define ESDCFG_TRRD(x)		(((x) & 0x3) << 10)
+#define ESDCFG_TRAS(x)		(((x) & 0x7) << 12)
+#define ESDCFG_TWR		(1 << 15)
+#define ESDCFG_TMRD(x)		(((x) & 0x3) << 16)
+#define ESDCFG_TRP(x)		(((x) & 0x3) << 18)
+#define ESDCFG_TWTR		(1 << 20)
+#define ESDCFG_TXP(x)		(((x) & 0x3) << 21)
+
+#define ESDMISC_RST		(1 << 1)
+#define ESDMISC_MDDREN		(1 << 2)
+#define ESDMISC_MDDR_DL_RST	(1 << 3)
+#define ESDMISC_MDDR_MDIS	(1 << 4)
+#define ESDMISC_LHD		(1 << 5)
+#define ESDMISC_MA10_SHARE	(1 << 6)
+#define ESDMISC_SDRAM_RDY	(1 << 31)
+
+/* GPT bits */
+#define GPT_CTRL_SWR		(1 << 15)	/* Software reset */
+#define GPT_CTRL_FRR		(1 << 9)	/* Freerun / restart */
+#define GPT_CTRL_CLKSOURCE_32	(4 << 6)	/* Clock source	*/
+#define GPT_CTRL_TEN		1		/* Timer enable	*/
+
+/* WDOG enable */
+#define WCR_WDE 0x04
+
+/* FUSE bank offsets */
+#define IIM0_MAC		0x1a
+
+#endif				/* _IMX_REGS_H */
diff --git a/include/asm-arm/arch-mx25/imx25-pinmux.h b/include/asm-arm/arch-mx25/imx25-pinmux.h
new file mode 100644
index 0000000000..a4c658b41b
--- /dev/null
+++ b/include/asm-arm/arch-mx25/imx25-pinmux.h
@@ -0,0 +1,421 @@
+/*
+ * iopin settings are controlled by four different sets of registers
+ *	iopad mux control
+ *	individual iopad setup (voltage select, pull/keep, drive strength ...)
+ *	group iopad setup (same as above but for groups of signals)
+ *	input select when multiple inputs are possible
+ */
+
+/*
+ * software pad mux control
+ */
+/* SW Input On (Loopback) */
+#define MX25_PIN_MUX_SION		(1 << 4)
+/* MUX Mode (0-7) */
+#define MX25_PIN_MUX_MODE(mode)		((mode & 0x7) << 0)
+struct iomuxc_mux_ctl {
+	u32 gpr1;
+	u32 observe_int_mux;
+	u32 pad_a10;
+	u32 pad_a13;
+	u32 pad_a14;
+	u32 pad_a15;
+	u32 pad_a16;
+	u32 pad_a17;
+	u32 pad_a18;
+	u32 pad_a19;
+	u32 pad_a20;
+	u32 pad_a21;
+	u32 pad_a22;
+	u32 pad_a23;
+	u32 pad_a24;
+	u32 pad_a25;
+	u32 pad_eb0;
+	u32 pad_eb1;
+	u32 pad_oe;
+	u32 pad_cs0;
+	u32 pad_cs1;
+	u32 pad_cs4;
+	u32 pad_cs5;
+	u32 pad_nf_ce0;
+	u32 pad_ecb;
+	u32 pad_lba;
+	u32 pad_bclk;
+	u32 pad_rw;
+	u32 pad_nfwe_b;
+	u32 pad_nfre_b;
+	u32 pad_nfale;
+	u32 pad_nfcle;
+	u32 pad_nfwp_b;
+	u32 pad_nfrb;
+	u32 pad_d15;
+	u32 pad_d14;
+	u32 pad_d13;
+	u32 pad_d12;
+	u32 pad_d11;
+	u32 pad_d10;
+	u32 pad_d9;
+	u32 pad_d8;
+	u32 pad_d7;
+	u32 pad_d6;
+	u32 pad_d5;
+	u32 pad_d4;
+	u32 pad_d3;
+	u32 pad_d2;
+	u32 pad_d1;
+	u32 pad_d0;
+	u32 pad_ld0;
+	u32 pad_ld1;
+	u32 pad_ld2;
+	u32 pad_ld3;
+	u32 pad_ld4;
+	u32 pad_ld5;
+	u32 pad_ld6;
+	u32 pad_ld7;
+	u32 pad_ld8;
+	u32 pad_ld9;
+	u32 pad_ld10;
+	u32 pad_ld11;
+	u32 pad_ld12;
+	u32 pad_ld13;
+	u32 pad_ld14;
+	u32 pad_ld15;
+	u32 pad_hsync;
+	u32 pad_vsync;
+	u32 pad_lsclk;
+	u32 pad_oe_acd;
+	u32 pad_contrast;
+	u32 pad_pwm;
+	u32 pad_csi_d2;
+	u32 pad_csi_d3;
+	u32 pad_csi_d4;
+	u32 pad_csi_d5;
+	u32 pad_csi_d6;
+	u32 pad_csi_d7;
+	u32 pad_csi_d8;
+	u32 pad_csi_d9;
+	u32 pad_csi_mclk;
+	u32 pad_csi_vsync;
+	u32 pad_csi_hsync;
+	u32 pad_csi_pixclk;
+	u32 pad_i2c1_clk;
+	u32 pad_i2c1_dat;
+	u32 pad_cspi1_mosi;
+	u32 pad_cspi1_miso;
+	u32 pad_cspi1_ss0;
+	u32 pad_cspi1_ss1;
+	u32 pad_cspi1_sclk;
+	u32 pad_cspi1_rdy;
+	u32 pad_uart1_rxd;
+	u32 pad_uart1_txd;
+	u32 pad_uart1_rts;
+	u32 pad_uart1_cts;
+	u32 pad_uart2_rxd;
+	u32 pad_uart2_txd;
+	u32 pad_uart2_rts;
+	u32 pad_uart2_cts;
+	u32 pad_sd1_cmd;
+	u32 pad_sd1_clk;
+	u32 pad_sd1_data0;
+	u32 pad_sd1_data1;
+	u32 pad_sd1_data2;
+	u32 pad_sd1_data3;
+	u32 pad_kpp_row0;
+	u32 pad_kpp_row1;
+	u32 pad_kpp_row2;
+	u32 pad_kpp_row3;
+	u32 pad_kpp_col0;
+	u32 pad_kpp_col1;
+	u32 pad_kpp_col2;
+	u32 pad_kpp_col3;
+	u32 pad_fec_mdc;
+	u32 pad_fec_mdio;
+	u32 pad_fec_tdata0;
+	u32 pad_fec_tdata1;
+	u32 pad_fec_tx_en;
+	u32 pad_fec_rdata0;
+	u32 pad_fec_rdata1;
+	u32 pad_fec_rx_dv;
+	u32 pad_fec_tx_clk;
+	u32 pad_rtck;
+	u32 pad_de_b;
+	u32 pad_gpio_a;
+	u32 pad_gpio_b;
+	u32 pad_gpio_c;
+	u32 pad_gpio_d;
+	u32 pad_gpio_e;
+	u32 pad_gpio_f;
+	u32 pad_ext_armclk;
+	u32 pad_upll_bypclk;
+	u32 pad_vstby_req;
+	u32 pad_vstby_ack;
+	u32 pad_power_fail;
+	u32 pad_clko;
+	u32 pad_boot_mode0;
+	u32 pad_boot_mode1;
+};
+
+/*
+ * software pad control
+ */
+/* Select 3.3 or 1.8 volts */
+#define MX25_PIN_PAD_CTL_DVS_33			(0 << 13)
+#define MX25_PIN_PAD_CTL_DVS_18			(1 << 13)
+/* Enable hysteresis */
+#define MX25_PIN_PAD_CTL_HYS			(1 << 8)
+/* Enable pull/keeper */
+#define MX25_PIN_PAD_CTL_PKE			(1 << 7)
+/* 0 - keeper / 1 - pull */
+#define MX25_PIN_PAD_CTL_PUE			(1 << 6)
+/* pull up/down strength */
+#define MX25_PIN_PAD_CTL_100K_PD		(0 << 4)
+#define MX25_PIN_PAD_CTL_47K_PU			(1 << 4)
+#define MX25_PIN_PAD_CTL_100K_PU		(2 << 4)
+#define MX25_PIN_PAD_CTL_22K_PU			(3 << 4)
+/* open drain control */
+#define MX25_PIN_PAD_CTL_OD			(1 << 3)
+/* drive strength */
+#define MX25_PIN_PAD_CTL_DS_NOM			(0 << 1)
+#define MX25_PIN_PAD_CTL_DS_HIGH		(1 << 1)
+#define MX25_PIN_PAD_CTL_DS_MAX			(2 << 1)
+#define MX25_PIN_PAD_CTL_DS_MAX11		(3 << 1)
+/* slew rate */
+#define MX25_PIN_PAD_CTL_SRE_SLOW		(0 << 0)
+#define MX25_PIN_PAD_CTL_SRE_FAST		(1 << 0)
+struct  iomuxc_pad_ctl {
+	u32 pad_a13;
+	u32 pad_a14;
+	u32 pad_a15;
+	u32 pad_a17;
+	u32 pad_a18;
+	u32 pad_a19;
+	u32 pad_a20;
+	u32 pad_a21;
+	u32 pad_a23;
+	u32 pad_a24;
+	u32 pad_a25;
+	u32 pad_eb0;
+	u32 pad_eb1;
+	u32 pad_oe;
+	u32 pad_cs4;
+	u32 pad_cs5;
+	u32 pad_nf_ce0;
+	u32 pad_ecb;
+	u32 pad_lba;
+	u32 pad_rw;
+	u32 pad_nfrb;
+	u32 pad_d15;
+	u32 pad_d14;
+	u32 pad_d13;
+	u32 pad_d12;
+	u32 pad_d11;
+	u32 pad_d10;
+	u32 pad_d9;
+	u32 pad_d8;
+	u32 pad_d7;
+	u32 pad_d6;
+	u32 pad_d5;
+	u32 pad_d4;
+	u32 pad_d3;
+	u32 pad_d2;
+	u32 pad_d1;
+	u32 pad_d0;
+	u32 pad_ld0;
+	u32 pad_ld1;
+	u32 pad_ld2;
+	u32 pad_ld3;
+	u32 pad_ld4;
+	u32 pad_ld5;
+	u32 pad_ld6;
+	u32 pad_ld7;
+	u32 pad_ld8;
+	u32 pad_ld9;
+	u32 pad_ld10;
+	u32 pad_ld11;
+	u32 pad_ld12;
+	u32 pad_ld13;
+	u32 pad_ld14;
+	u32 pad_ld15;
+	u32 pad_hsync;
+	u32 pad_vsync;
+	u32 pad_lsclk;
+	u32 pad_oe_acd;
+	u32 pad_contrast;
+	u32 pad_pwm;
+	u32 pad_csi_d2;
+	u32 pad_csi_d3;
+	u32 pad_csi_d4;
+	u32 pad_csi_d5;
+	u32 pad_csi_d6;
+	u32 pad_csi_d7;
+	u32 pad_csi_d8;
+	u32 pad_csi_d9;
+	u32 pad_csi_mclk;
+	u32 pad_csi_vsync;
+	u32 pad_csi_hsync;
+	u32 pad_csi_pixclk;
+	u32 pad_i2c1_clk;
+	u32 pad_i2c1_dat;
+	u32 pad_cspi1_mosi;
+	u32 pad_cspi1_miso;
+	u32 pad_cspi1_ss0;
+	u32 pad_cspi1_ss1;
+	u32 pad_cspi1_sclk;
+	u32 pad_cspi1_rdy;
+	u32 pad_uart1_rxd;
+	u32 pad_uart1_txd;
+	u32 pad_uart1_rts;
+	u32 pad_uart1_cts;
+	u32 pad_uart2_rxd;
+	u32 pad_uart2_txd;
+	u32 pad_uart2_rts;
+	u32 pad_uart2_cts;
+	u32 pad_sd1_cmd;
+	u32 pad_sd1_clk;
+	u32 pad_sd1_data0;
+	u32 pad_sd1_data1;
+	u32 pad_sd1_data2;
+	u32 pad_sd1_data3;
+	u32 pad_kpp_row0;
+	u32 pad_kpp_row1;
+	u32 pad_kpp_row2;
+	u32 pad_kpp_row3;
+	u32 pad_kpp_col0;
+	u32 pad_kpp_col1;
+	u32 pad_kpp_col2;
+	u32 pad_kpp_col3;
+	u32 pad_fec_mdc;
+	u32 pad_fec_mdio;
+	u32 pad_fec_tdata0;
+	u32 pad_fec_tdata1;
+	u32 pad_fec_tx_en;
+	u32 pad_fec_rdata0;
+	u32 pad_fec_rdata1;
+	u32 pad_fec_rx_dv;
+	u32 pad_fec_tx_clk;
+	u32 pad_rtck;
+	u32 pad_tdo;
+	u32 pad_de_b;
+	u32 pad_gpio_a;
+	u32 pad_gpio_b;
+	u32 pad_gpio_c;
+	u32 pad_gpio_d;
+	u32 pad_gpio_e;
+	u32 pad_gpio_f;
+	u32 pad_vstby_req;
+	u32 pad_vstby_ack;
+	u32 pad_power_fail;
+	u32 pad_clko;
+};
+
+
+/*
+ * Pad group drive strength and voltage select
+ * Same fields as iomuxc_pad_ctl plus ddr type
+ */
+/* Select DDR type */
+#define MX25_PIN_PAD_CTL_DDR_18			(0 << 11)
+#define MX25_PIN_PAD_CTL_DDR_33			(1 << 11)
+#define MX25_PIN_PAD_CTL_DDR_MAX		(2 << 11)
+struct iomuxc_pad_grp_ctl {
+	u32 grp_dvs_misc;
+	u32 grp_dse_fec;
+	u32 grp_dvs_jtag;
+	u32 grp_dse_nfc;
+	u32 grp_dse_csi;
+	u32 grp_dse_weim;
+	u32 grp_dse_ddr;
+	u32 grp_dvs_crm;
+	u32 grp_dse_kpp;
+	u32 grp_dse_sdhc1;
+	u32 grp_dse_lcd;
+	u32 grp_dse_uart;
+	u32 grp_dvs_nfc;
+	u32 grp_dvs_csi;
+	u32 grp_dse_cspi1;
+	u32 grp_ddrtype;
+	u32 grp_dvs_sdhc1;
+	u32 grp_dvs_lcd;
+};
+
+/*
+ * Pad input select control
+ * Select which pad to connect to an input port
+ * where multiple pads can function as given input
+ */
+#define MX25_PAD_INPUT_SELECT_DAISY(in)		((in & 0x7) << 0)
+struct iomuxc_pad_input_select {
+	u32 audmux_p4_input_da_amx;
+	u32 audmux_p4_input_db_amx;
+	u32 audmux_p4_input_rxclk_amx;
+	u32 audmux_p4_input_rxfs_amx;
+	u32 audmux_p4_input_txclk_amx;
+	u32 audmux_p4_input_txfs_amx;
+	u32 audmux_p7_input_da_amx;
+	u32 audmux_p7_input_txfs_amx;
+	u32 can1_ipp_ind_canrx;
+	u32 can2_ipp_ind_canrx;
+	u32 csi_ipp_csi_d_0;
+	u32 csi_ipp_csi_d_1;
+	u32 cspi1_ipp_ind_ss3_b;
+	u32 cspi2_ipp_cspi_clk_in;
+	u32 cspi2_ipp_ind_dataready_b;
+	u32 cspi2_ipp_ind_miso;
+	u32 cspi2_ipp_ind_mosi;
+	u32 cspi2_ipp_ind_ss0_b;
+	u32 cspi2_ipp_ind_ss1_b;
+	u32 cspi3_ipp_cspi_clk_in;
+	u32 cspi3_ipp_ind_dataready_b;
+	u32 cspi3_ipp_ind_miso;
+	u32 cspi3_ipp_ind_mosi;
+	u32 cspi3_ipp_ind_ss0_b;
+	u32 cspi3_ipp_ind_ss1_b;
+	u32 cspi3_ipp_ind_ss2_b;
+	u32 cspi3_ipp_ind_ss3_b;
+	u32 esdhc1_ipp_dat4_in;
+	u32 esdhc1_ipp_dat5_in;
+	u32 esdhc1_ipp_dat6_in;
+	u32 esdhc1_ipp_dat7_in;
+	u32 esdhc2_ipp_card_clk_in;
+	u32 esdhc2_ipp_cmd_in;
+	u32 esdhc2_ipp_dat0_in;
+	u32 esdhc2_ipp_dat1_in;
+	u32 esdhc2_ipp_dat2_in;
+	u32 esdhc2_ipp_dat3_in;
+	u32 esdhc2_ipp_dat4_in;
+	u32 esdhc2_ipp_dat5_in;
+	u32 esdhc2_ipp_dat6_in;
+	u32 esdhc2_ipp_dat7_in;
+	u32 fec_fec_col;
+	u32 fec_fec_crs;
+	u32 fec_fec_rdata_2;
+	u32 fec_fec_rdata_3;
+	u32 fec_fec_rx_clk;
+	u32 fec_fec_rx_er;
+	u32 i2c2_ipp_scl_in;
+	u32 i2c2_ipp_sda_in;
+	u32 i2c3_ipp_scl_in;
+	u32 i2c3_ipp_sda_in;
+	u32 kpp_ipp_ind_col_4;
+	u32 kpp_ipp_ind_col_5;
+	u32 kpp_ipp_ind_col_6;
+	u32 kpp_ipp_ind_col_7;
+	u32 kpp_ipp_ind_row_4;
+	u32 kpp_ipp_ind_row_5;
+	u32 kpp_ipp_ind_row_6;
+	u32 kpp_ipp_ind_row_7;
+	u32 sim1_pin_sim_rcvd1_in;
+	u32 sim1_pin_sim_simpd1;
+	u32 sim1_sim_rcvd1_io;
+	u32 sim2_pin_sim_rcvd1_in;
+	u32 sim2_pin_sim_simpd1;
+	u32 sim2_sim_rcvd1_io;
+	u32 uart3_ipp_uart_rts_b;
+	u32 uart3_ipp_uart_rxd_mux;
+	u32 uart4_ipp_uart_rts_b;
+	u32 uart4_ipp_uart_rxd_mux;
+	u32 uart5_ipp_uart_rts_b;
+	u32 uart5_ipp_uart_rxd_mux;
+	u32 usb_top_ipp_ind_otg_usb_oc;
+	u32 usb_top_ipp_ind_uh2_usb_oc;
+};
diff --git a/include/asm-arm/arch-mx27/clock.h b/include/asm-arm/arch-mx27/clock.h
index 5fc75c5d5c..7e9c7aabb0 100644
--- a/include/asm-arm/arch-mx27/clock.h
+++ b/include/asm-arm/arch-mx27/clock.h
@@ -36,4 +36,7 @@ ulong imx_get_perclk2(void);
 ulong imx_get_perclk3(void);
 ulong imx_get_ahbclk(void);
 
+#define imx_get_uartclk imx_get_perclk1
+#define imx_get_fecclk imx_get_ahbclk
+
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/include/asm-arm/arch-mx31/mx31.h b/include/asm-arm/arch-mx31/mx31.h
index 53b9f27333..3cc4b350b6 100644
--- a/include/asm-arm/arch-mx31/mx31.h
+++ b/include/asm-arm/arch-mx31/mx31.h
@@ -25,6 +25,7 @@
 #define __ASM_ARCH_MX31_H
 
 extern u32 mx31_get_ipg_clk(void);
+#define imx_get_uartclk mx31_get_ipg_clk
 extern void mx31_gpio_mux(unsigned long mode);
 
 enum mx31_gpio_direction {
diff --git a/include/asm-arm/arch-mx51/asm-offsets.h b/include/asm-arm/arch-mx51/asm-offsets.h
new file mode 100644
index 0000000000..3a83fa07a1
--- /dev/null
+++ b/include/asm-arm/arch-mx51/asm-offsets.h
@@ -0,0 +1,50 @@
+/*
+ * needed for cpu/arm_cortexa8/mx51/lowlevel_init.S
+ *
+ * These should be auto-generated
+ */
+/* CCM */
+#define CLKCTL_CCR              0x00
+#define CLKCTL_CCDR             0x04
+#define CLKCTL_CSR              0x08
+#define CLKCTL_CCSR             0x0C
+#define CLKCTL_CACRR            0x10
+#define CLKCTL_CBCDR            0x14
+#define CLKCTL_CBCMR            0x18
+#define CLKCTL_CSCMR1           0x1C
+#define CLKCTL_CSCMR2           0x20
+#define CLKCTL_CSCDR1           0x24
+#define CLKCTL_CS1CDR           0x28
+#define CLKCTL_CS2CDR           0x2C
+#define CLKCTL_CDCDR            0x30
+#define CLKCTL_CHSCCDR          0x34
+#define CLKCTL_CSCDR2           0x38
+#define CLKCTL_CSCDR3           0x3C
+#define CLKCTL_CSCDR4           0x40
+#define CLKCTL_CWDR             0x44
+#define CLKCTL_CDHIPR           0x48
+#define CLKCTL_CDCR             0x4C
+#define CLKCTL_CTOR             0x50
+#define CLKCTL_CLPCR            0x54
+#define CLKCTL_CISR             0x58
+#define CLKCTL_CIMR             0x5C
+#define CLKCTL_CCOSR            0x60
+#define CLKCTL_CGPR             0x64
+#define CLKCTL_CCGR0            0x68
+#define CLKCTL_CCGR1            0x6C
+#define CLKCTL_CCGR2            0x70
+#define CLKCTL_CCGR3            0x74
+#define CLKCTL_CCGR4            0x78
+#define CLKCTL_CCGR5            0x7C
+#define CLKCTL_CCGR6            0x80
+#define CLKCTL_CMEOR            0x84
+
+/* DPLL */
+#define PLL_DP_CTL	0x00
+#define PLL_DP_CONFIG	0x04
+#define PLL_DP_OP	0x08
+#define PLL_DP_MFD	0x0C
+#define PLL_DP_MFN	0x10
+#define PLL_DP_HFS_OP	0x1C
+#define PLL_DP_HFS_MFD	0x20
+#define PLL_DP_HFS_MFN	0x24
diff --git a/include/asm-arm/arch-mx51/clock.h b/include/asm-arm/arch-mx51/clock.h
new file mode 100644
index 0000000000..1f8a537a56
--- /dev/null
+++ b/include/asm-arm/arch-mx51/clock.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_AHB_CLK,
+	MXC_IPG_CLK,
+	MXC_IPG_PERCLK,
+	MXC_UART_CLK,
+	MXC_CSPI_CLK,
+	MXC_FEC_CLK,
+};
+
+unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
+
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/include/asm-arm/arch-mx51/crm_regs.h b/include/asm-arm/arch-mx51/crm_regs.h
new file mode 100644
index 0000000000..14aa231a5b
--- /dev/null
+++ b/include/asm-arm/arch-mx51/crm_regs.h
@@ -0,0 +1,192 @@
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+
+#define MXC_CCM_BASE	CCM_BASE_ADDR
+
+/* DPLL register mapping structure */
+struct mxc_pll_reg {
+	u32 ctrl;
+	u32 config;
+	u32 op;
+	u32 mfd;
+	u32 mfn;
+	u32 mfn_minus;
+	u32 mfn_plus;
+	u32 hfs_op;
+	u32 hfs_mfd;
+	u32 hfs_mfn;
+	u32 mfn_togc;
+	u32 destat;
+};
+
+/* Register maping of CCM*/
+struct mxc_ccm_reg {
+	u32 ccr;	/* 0x0000 */
+	u32 ccdr;
+	u32 csr;
+	u32 ccsr;
+	u32 cacrr;	/* 0x0010*/
+	u32 cbcdr;
+	u32 cbcmr;
+	u32 cscmr1;
+	u32 cscmr2;	/* 0x0020 */
+	u32 cscdr1;
+	u32 cs1cdr;
+	u32 cs2cdr;
+	u32 cdcdr;	/* 0x0030 */
+	u32 chscdr;
+	u32 cscdr2;
+	u32 cscdr3;
+	u32 cscdr4;	/* 0x0040 */
+	u32 cwdr;
+	u32 cdhipr;
+	u32 cdcr;
+	u32 ctor;	/* 0x0050 */
+	u32 clpcr;
+	u32 cisr;
+	u32 cimr;
+	u32 ccosr;	/* 0x0060 */
+	u32 cgpr;
+	u32 CCGR0;
+	u32 CCGR1;
+	u32 CCGR2;	/* 0x0070 */
+	u32 CCGR3;
+	u32 CCGR4;
+	u32 CCGR5;
+	u32 CCGR6;	/* 0x0080 */
+	u32 cmeor;
+};
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET		0
+#define MXC_CCM_CACRR_ARM_PODF_MASK		0x7
+
+/* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
+#define MXC_CCM_CBCDR_EMI_PODF_OFFSET		22
+#define MXC_CCM_CBCDR_EMI_PODF_MASK		(0x7 << 22)
+#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET		19
+#define MXC_CCM_CBCDR_AXI_B_PODF_MASK		(0x7 << 19)
+#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET		16
+#define MXC_CCM_CBCDR_AXI_A_PODF_MASK		(0x7 << 16)
+#define MXC_CCM_CBCDR_NFC_PODF_OFFSET		13
+#define MXC_CCM_CBCDR_NFC_PODF_MASK		(0x7 << 13)
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET		10
+#define MXC_CCM_CBCDR_AHB_PODF_MASK		(0x7 << 10)
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET		8
+#define MXC_CCM_CBCDR_IPG_PODF_MASK		(0x3 << 8)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET	6
+#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK		(0x3 << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET	3
+#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK		(0x7 << 3)
+#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET	0
+#define MXC_CCM_CBCDR_PERCLK_PODF_MASK		0x7
+
+/* Define the bits in register CSCMR1 */
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET		30
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK		(0x3 << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET		28
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK		(0x3 << 28)
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET		26
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL			(0x1 << 26)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET		24
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK		(0x3 << 24)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET		22
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK		(0x3 << 22)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET	20
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK	(0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL			(0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 18)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET	16
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK	(0x3 << 16)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		14
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		12
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL			(0x1 << 11)
+#define MXC_CCM_CSCMR1_VPU_RCLK_SEL			(0x1 << 10)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET		8
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CSCMR1_TVE_CLK_SEL			(0x1 << 7)
+#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL			(0x1 << 6)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET		4
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK		(0x3 << 4)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET		2
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK		(0x3 << 2)
+#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL		(0x1 << 1)
+#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL		0x1
+
+/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET		25
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK		(0x7 << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET		19
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK		(0x3F << 19)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET		16
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK		(0x7 << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET		9
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK		(0x3F << 9)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET		6
+#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK		(0x7 << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET		0
+#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK		0x3F
+
+/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET		14
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET		12
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET		10
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK			(0x3 << 10)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET		8
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET		6
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK		(0x3 << 6)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET		4
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK			(0x3 << 4)
+#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL		(0x1 << 1)
+#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL		(0x1 << 0)
+
+/* Define the bits in register CSCDR1 */
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET	22
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK	(0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET	19
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK	(0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET	16
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK	(0x7 << 16)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET		14
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK		(0x3 << 14)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET	11
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK	(0x7 << 11)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		8
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET		3
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK		(0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x7
+
+#endif				/* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/include/asm-arm/arch-mx51/imx-regs.h b/include/asm-arm/arch-mx51/imx-regs.h
new file mode 100644
index 0000000000..3887d3cec4
--- /dev/null
+++ b/include/asm-arm/arch-mx51/imx-regs.h
@@ -0,0 +1,261 @@
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MXC_MX51_H__
+#define __ASM_ARCH_MXC_MX51_H__
+
+#define __REG(x)	(*((volatile u32 *)(x)))
+#define __REG16(x)	(*((volatile u16 *)(x)))
+#define __REG8(x)	(*((volatile u8 *)(x)))
+/*
+ * IRAM
+ */
+#define IRAM_BASE_ADDR		0x1FFE8000	/* internal ram */
+/*
+ * Graphics Memory of GPU
+ */
+#define GPU_BASE_ADDR		0x20000000
+#define GPU_CTRL_BASE_ADDR	0x30000000
+#define IPU_CTRL_BASE_ADDR	0x40000000
+/*
+ * Debug
+ */
+#define DEBUG_BASE_ADDR		0x60000000
+#define ETB_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00001000)
+#define ETM_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00002000)
+#define TPIU_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00003000)
+#define CTI0_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00004000)
+#define CTI1_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00005000)
+#define CTI2_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00006000)
+#define CTI3_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00007000)
+#define CORTEX_DBG_BASE_ADDR	(DEBUG_BASE_ADDR + 0x00008000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define SPBA0_BASE_ADDR 	0x70000000
+
+#define MMC_SDHC1_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00004000)
+#define MMC_SDHC2_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00008000)
+#define UART3_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x0000C000)
+#define CSPI1_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x00010000)
+#define SSI2_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00014000)
+#define MMC_SDHC3_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00020000)
+#define MMC_SDHC4_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00024000)
+#define SPDIF_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00028000)
+#define ATA_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00030000)
+#define SLIM_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00034000)
+#define HSI2C_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00038000)
+#define SPBA_CTRL_BASE_ADDR	(SPBA0_BASE_ADDR + 0x0003C000)
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR 	0x73F00000
+
+#define OTG_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00080000)
+#define GPIO1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00084000)
+#define GPIO2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00088000)
+#define GPIO3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0008C000)
+#define GPIO4_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00090000)
+#define KPP_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00094000)
+#define WDOG1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00098000)
+#define WDOG2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0009C000)
+#define GPT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A0000)
+#define SRTC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A4000)
+#define IOMUXC_BASE_ADDR	(AIPS1_BASE_ADDR + 0x000A8000)
+#define EPIT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000AC000)
+#define EPIT2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B0000)
+#define PWM1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B4000)
+#define PWM2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B8000)
+#define UART1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000BC000)
+#define UART2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000C0000)
+#define SRC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D0000)
+#define CCM_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D4000)
+#define GPC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D8000)
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR	0x83F00000
+
+#define PLL1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00080000)
+#define PLL2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00084000)
+#define PLL3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00088000)
+#define AHBMAX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x00094000)
+#define IIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00098000)
+#define CSU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0009C000)
+#define ARM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A0000)
+#define OWIRE_BASE_ADDR 	(AIPS2_BASE_ADDR + 0x000A4000)
+#define FIRI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A8000)
+#define CSPI2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000AC000)
+#define SDMA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B0000)
+#define SCC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B4000)
+#define ROMCP_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B8000)
+#define RTIC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000BC000)
+#define CSPI3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C0000)
+#define I2C2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C4000)
+#define I2C1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C8000)
+#define SSI1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000CC000)
+#define AUDMUX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D0000)
+#define M4IF_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000D8000)
+#define ESDCTL_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D9000)
+#define WEIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DA000)
+#define NFC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DB000)
+#define EMI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DBF00)
+#define MIPI_HSC_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000DC000)
+#define ATA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E0000)
+#define SIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E4000)
+#define SSI3BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E8000)
+#define FEC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000EC000)
+#define TVE_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F0000)
+#define VPU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F4000)
+#define SAHARA_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000F8000)
+
+#define TZIC_BASE_ADDR		0x8FFFC000
+
+/*
+ * Memory regions and CS
+ */
+#define CSD0_BASE_ADDR		0x90000000
+#define CSD1_BASE_ADDR		0xA0000000
+#define CS0_BASE_ADDR		0xB0000000
+#define CS1_BASE_ADDR		0xB8000000
+#define CS2_BASE_ADDR		0xC0000000
+#define CS3_BASE_ADDR		0xC8000000
+#define CS4_BASE_ADDR		0xCC000000
+#define CS5_BASE_ADDR		0xCE000000
+
+/*
+ * NFC
+ */
+#define NFC_BASE_ADDR_AXI	0xCFFF0000	/* NAND flash AXI */
+
+/*!
+ * Number of GPIO port as defined in the IC Spec
+ */
+#define GPIO_PORT_NUM		4
+/*!
+ * Number of GPIO pins per port
+ */
+#define GPIO_NUM_PIN            32
+
+#define IIM_SREV	0x24
+#define ROM_SI_REV	0x48
+
+#define NFC_BUF_SIZE	0x1000
+
+/* M4IF */
+#define M4IF_FBPM0	0x40
+#define M4IF_FIDBP	0x48
+
+/* Assuming 24MHz input clock with doubler ON */
+/*                            MFI         PDF */
+#define DP_OP_850	((8 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_850	(48 - 1)
+#define DP_MFN_850	41
+
+#define DP_OP_800	((8 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_800	(3 - 1)
+#define DP_MFN_800	1
+
+#define DP_OP_700	((7 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_700	(24 - 1)
+#define DP_MFN_700	7
+
+#define DP_OP_665	((6 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_665	(96 - 1)
+#define DP_MFN_665	89
+
+#define DP_OP_532	((5 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_532	(24 - 1)
+#define DP_MFN_532	13
+
+#define DP_OP_400	((8 << 4) + ((2 - 1)  << 0))
+#define DP_MFD_400	(3 - 1)
+#define DP_MFN_400	1
+
+#define DP_OP_216	((6 << 4) + ((3 - 1)  << 0))
+#define DP_MFD_216	(4 - 1)
+#define DP_MFN_216	3
+
+#define CHIP_REV_1_0            0x10
+#define CHIP_REV_1_1            0x11
+#define CHIP_REV_2_0            0x20
+#define CHIP_REV_2_5		0x25
+#define CHIP_REV_3_0            0x30
+
+#define BOARD_REV_1_0           0x0
+#define BOARD_REV_2_0           0x1
+
+#ifndef __ASSEMBLY__
+
+struct clkctl {
+	u32	ccr;
+	u32	ccdr;
+	u32	csr;
+	u32	ccsr;
+	u32	cacrr;
+	u32	cbcdr;
+	u32	cbcmr;
+	u32	cscmr1;
+	u32	cscmr2;
+	u32	cscdr1;
+	u32	cs1cdr;
+	u32	cs2cdr;
+	u32	cdcdr;
+	u32	chsccdr;
+	u32	cscdr2;
+	u32	cscdr3;
+	u32	cscdr4;
+	u32	cwdr;
+	u32	cdhipr;
+	u32	cdcr;
+	u32	ctor;
+	u32	clpcr;
+	u32	cisr;
+	u32	cimr;
+	u32	ccosr;
+	u32	cgpr;
+	u32	ccgr0;
+	u32	ccgr1;
+	u32	ccgr2;
+	u32	ccgr3;
+	u32	ccgr4;
+	u32	ccgr5;
+	u32	ccgr6;
+	u32	cmeor;
+};
+
+/* WEIM registers */
+struct weim {
+	u32	csgcr1;
+	u32	csgcr2;
+	u32	csrcr1;
+	u32	csrcr2;
+	u32	cswcr1;
+	u32	cswcr2;
+};
+
+#endif /* __ASSEMBLER__*/
+
+#endif				/*  __ASM_ARCH_MXC_MX51_H__ */
diff --git a/include/asm-arm/arch-mx51/iomux.h b/include/asm-arm/arch-mx51/iomux.h
new file mode 100644
index 0000000000..a41c387c7c
--- /dev/null
+++ b/include/asm-arm/arch-mx51/iomux.h
@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MACH_MX51_IOMUX_H__
+#define __MACH_MX51_IOMUX_H__
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx51_pins.h>
+
+typedef unsigned int iomux_pin_name_t;
+
+/* various IOMUX output functions */
+typedef enum iomux_config {
+	IOMUX_CONFIG_ALT0,	/*!< used as alternate function 0 */
+	IOMUX_CONFIG_ALT1,	/*!< used as alternate function 1 */
+	IOMUX_CONFIG_ALT2,	/*!< used as alternate function 2 */
+	IOMUX_CONFIG_ALT3,	/*!< used as alternate function 3 */
+	IOMUX_CONFIG_ALT4,	/*!< used as alternate function 4 */
+	IOMUX_CONFIG_ALT5,	/*!< used as alternate function 5 */
+	IOMUX_CONFIG_ALT6,	/*!< used as alternate function 6 */
+	IOMUX_CONFIG_ALT7,	/*!< used as alternate function 7 */
+	IOMUX_CONFIG_GPIO,	/*!< added to help user use GPIO mode */
+	IOMUX_CONFIG_SION = 0x1 << 4,	/*!< used as LOOPBACK:MUX SION bit */
+} iomux_pin_cfg_t;
+
+/* various IOMUX pad functions */
+typedef enum iomux_pad_config {
+	PAD_CTL_SRE_SLOW = 0x0 << 0,	/* Slow slew rate */
+	PAD_CTL_SRE_FAST = 0x1 << 0,	/* Fast slew rate */
+	PAD_CTL_DRV_LOW = 0x0 << 1,	/* Low drive strength */
+	PAD_CTL_DRV_MEDIUM = 0x1 << 1,	/* Medium drive strength */
+	PAD_CTL_DRV_HIGH = 0x2 << 1,	/* High drive strength */
+	PAD_CTL_DRV_MAX = 0x3 << 1,	/* Max drive strength */
+	PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,	/* Opendrain disable */
+	PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,/* Opendrain enable */
+	PAD_CTL_100K_PD = 0x0 << 4,	/* 100Kohm pulldown */
+	PAD_CTL_47K_PU = 0x1 << 4,	/* 47Kohm pullup */
+	PAD_CTL_100K_PU = 0x2 << 4,	/* 100Kohm pullup */
+	PAD_CTL_22K_PU = 0x3 << 4,	/* 22Kohm pullup */
+	PAD_CTL_PUE_KEEPER = 0x0 << 6,	/* enable pulldown */
+	PAD_CTL_PUE_PULL = 0x1 << 6,	/* enable pullup */
+	PAD_CTL_PKE_NONE = 0x0 << 7,	/* Disable pullup/pulldown */
+	PAD_CTL_PKE_ENABLE = 0x1 << 7,	/* Enable pullup/pulldown */
+	PAD_CTL_HYS_NONE = 0x0 << 8,	/* Hysteresis disabled */
+	PAD_CTL_HYS_ENABLE = 0x1 << 8,	/* Hysteresis enabled */
+	PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */
+	PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */
+	PAD_CTL_DRV_VOT_LOW = 0x0 << 13, /* Low voltage mode */
+	PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */
+} iomux_pad_config_t;
+
+/* various IOMUX input select register index */
+typedef enum iomux_input_select {
+	MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
+	MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
+	MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
+	MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
+	MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
+	MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
+	MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
+	MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
+	MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
+	MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
+	MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
+	MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
+	MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
+	MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
+	MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
+	MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
+	MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT,
+	/* TO2 */
+	MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
+	MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
+	MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
+	MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
+	MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
+	MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
+	MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
+	MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
+	MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
+	MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
+	/* TO2 */
+	MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
+	MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
+	MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
+	MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
+	MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
+	MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
+	MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
+	MUX_IN_FEC_FEC_COL_SELECT_INPUT,
+	MUX_IN_FEC_FEC_CRS_SELECT_INPUT,
+	MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
+	MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
+	MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
+	MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT,
+	MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT,
+	MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
+	MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
+	MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
+	MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT,
+	MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
+	MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
+	MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
+	MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
+	MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
+	MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
+	MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
+	MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
+	/* TO2 */
+	MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
+	MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
+	MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
+	/* TO2 */
+	MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
+	/* TO2 */
+	MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
+	MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
+	MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
+	MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
+	MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
+	MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
+
+	MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
+
+	MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
+
+	MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
+	MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
+	MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT,
+	MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
+	MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
+	MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
+	MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
+	MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
+	MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
+	MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
+	MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
+	MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
+	MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
+	MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
+	MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
+	MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
+	MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
+	MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
+	MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
+	MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
+	MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
+	MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
+	MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
+	MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
+	MUX_INPUT_NUM_MUX,
+} iomux_input_select_t;
+
+/* various IOMUX input functions */
+typedef enum iomux_input_config {
+	INPUT_CTL_PATH0 = 0x0,
+	INPUT_CTL_PATH1,
+	INPUT_CTL_PATH2,
+	INPUT_CTL_PATH3,
+	INPUT_CTL_PATH4,
+	INPUT_CTL_PATH5,
+	INPUT_CTL_PATH6,
+	INPUT_CTL_PATH7,
+} iomux_input_config_t;
+
+void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
+void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
+void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
+unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
+void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
+
+#endif				/*  __MACH_MX51_IOMUX_H__ */
diff --git a/include/asm-arm/arch-mx51/mx51_pins.h b/include/asm-arm/arch-mx51/mx51_pins.h
new file mode 100644
index 0000000000..ca26f4166b
--- /dev/null
+++ b/include/asm-arm/arch-mx51/mx51_pins.h
@@ -0,0 +1,374 @@
+/*
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MXC_MX51_PINS_H__
+#define __ASM_ARCH_MXC_MX51_PINS_H__
+
+#ifndef __ASSEMBLY__
+
+/*
+ * In order to identify pins more effectively, each mux-controlled pin's
+ * enumerated value is constructed in the following way:
+ *
+ * -------------------------------------------------------------------
+ * 31-29 | 28 - 24 |  23 - 21 | 20  - 10| 9 - 0
+ * -------------------------------------------------------------------
+ * IO_P  |  IO_I   | GPIO_I   | PAD_I   | MUX_I
+ * -------------------------------------------------------------------
+ *
+ * Bit 0 to 9 contains MUX_I used to identify the register
+ * offset (0-based. base is IOMUX_module_base) defined in the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
+ * similar field definitions are used for the pad control register.
+ * The IOMUX controller can be split in two parts. At the begeinning,
+ * there is the register definitions for the multiplexing each pin.
+ * Then there is a set of registers (PAD_I) to configure each pin
+ * (pullup, pulldown, etc).
+ * PAD_I defines the offset of the pad register for each pin.
+ * GPIO_I defines, if available, the number of gpio that can be
+ * connected to that pad
+ * IO_I defines the multiplexer mode required to set the pad in gpio mode
+ * IO_P defines the gpio structure (gpio1..gpio4) the pad belongs
+ *
+ * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
+ *    ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
+ * It means the mux control register is at register offset 0x28. The pad control
+ * register offset is: 0x250 and also occupy the least significant bits
+ * within the register.
+ */
+
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * MUX control register offset
+ */
+#define MUX_I			0
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * PAD control register offset
+ */
+#define PAD_I			10
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent which
+ * mux mode is for GPIO (0-based)
+ */
+#define GPIO_I			21
+
+#define MUX_IO_P                29
+#define MUX_IO_I                24
+#define IOMUX_TO_GPIO(pin)      ((((unsigned int)pin >> MUX_IO_P) * \
+					GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
+					((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
+#define IOMUX_TO_IRQ(pin)       (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
+#define GPIO_TO_PORT(n)         (n / GPIO_NUM_PIN)
+#define GPIO_TO_INDEX(n)        (n % GPIO_NUM_PIN)
+
+#define NON_GPIO_PORT		0x7
+#define PIN_TO_MUX_MASK		((1 << (PAD_I - MUX_I)) - 1)
+#define PIN_TO_PAD_MASK		((1 << (GPIO_I - PAD_I)) - 1)
+#define PIN_TO_ALT_GPIO_MASK		((1 << (MUX_IO_I - GPIO_I)) - 1)
+
+#define NON_MUX_I		PIN_TO_MUX_MASK
+#define MUX_I_START		0x001C
+#define PAD_I_START		0x3F0
+#define INPUT_CTL_START		0x8C4
+#define INPUT_CTL_START_TO1	0x928
+#define MUX_I_END		(PAD_I_START - 4)
+
+#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
+	(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
+	((mi) << MUX_I) | \
+	((pi - PAD_I_START) << PAD_I) | \
+	((ga) << GPIO_I))
+
+#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
+	_MXC_BUILD_PIN(gp, gi, ga, mi, pi)
+
+#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
+	_MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
+
+#define PIN_TO_IOMUX_MUX(pin)	((pin >> MUX_I) & PIN_TO_MUX_MASK)
+#define PIN_TO_IOMUX_PAD(pin)	((pin >> PAD_I) & PIN_TO_PAD_MASK)
+#define PIN_TO_ALT_GPIO(pin)	((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
+#define PIN_TO_IOMUX_INDEX(pin)	(PIN_TO_IOMUX_MUX(pin) >> 2)
+
+/*
+ * This enumeration is constructed based on the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
+ * value is constructed based on the rules described above.
+ */
+enum iomux_pins {
+	MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
+	MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
+	MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
+	MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
+	MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
+	MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
+	MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
+	MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
+	MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
+	MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
+	MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
+	MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
+	MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
+	MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
+	MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
+	MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
+	MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
+	MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
+	MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
+	MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
+	MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
+	MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
+	MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
+	MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
+	MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
+	MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
+	MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
+	MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
+	MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
+	MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
+	MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
+	MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
+	MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
+	MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
+	MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
+	MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
+	MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
+	MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
+	MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
+	MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
+	MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
+	MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
+	MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
+	MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
+	MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
+	MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
+	MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
+	MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
+	MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
+	MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
+	MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
+	MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
+	MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
+	MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
+	MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
+	MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
+	MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
+	MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
+	MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
+	MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
+	MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
+	MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
+	MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
+	MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
+	MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
+	MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
+	MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
+	MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
+	MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514),
+	MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
+	MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
+	MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
+	MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
+	MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
+	MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
+	MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
+	MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
+	MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
+	MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
+	MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
+	MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
+	MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
+	MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
+	MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
+	MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
+	MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
+	MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
+	MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
+	MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
+	MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
+	MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
+	MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
+	MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
+	MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
+	MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
+	MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
+	MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
+	MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
+	MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
+	MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
+	MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
+	MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
+	MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
+	MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
+	MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
+	MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
+	MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
+	MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
+	MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
+	MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
+	MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC),
+	MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0),
+	MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
+	MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
+	MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
+	MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
+	MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
+	MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4),
+	MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8),
+	MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC),
+	MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0),
+	MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
+	MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
+	MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
+	MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
+	MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
+	MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
+	MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
+	MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
+	MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
+	MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
+	MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
+	MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
+	MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
+	MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
+	MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
+	MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
+	MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
+	MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
+	MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
+	MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
+	MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
+	MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
+	MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
+	MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
+	MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
+	MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
+	MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
+	MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
+	MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
+	MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
+	MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
+	MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
+	MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
+	MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
+	MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
+	MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
+	MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
+	MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
+	MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
+	MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
+	MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
+	MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
+	MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
+	MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
+	MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
+	MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
+	MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
+	MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
+	MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
+	MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
+	MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
+	MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
+	MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
+	MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
+	MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
+	MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
+	MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
+	MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
+	MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
+	MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
+	MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
+	MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
+	MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
+	MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
+	MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
+	MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
+	MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
+	MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
+	MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
+	MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
+	MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
+	MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
+	MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
+	MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
+	MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
+	MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
+	MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
+	MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
+	MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
+	MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
+	MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
+	MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
+	MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
+	MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
+	MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
+	MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
+	MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
+	MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
+	MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
+	MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
+	MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
+	MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
+	MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
+	MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
+	MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
+	MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
+	MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
+	MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
+	MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
+	MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
+	MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
+	MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
+	MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
+	MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788),
+	MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
+	MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
+	MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
+	MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
+	MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
+	MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
+	MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
+	MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
+	MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
+	MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
+	MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
+	MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
+	MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
+	MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
+	MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
+	MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
+	MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
+	MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
+	MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
+	MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
+	MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
+	MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
+	MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
+	MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
+	MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
+	MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
+	MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
+};
+
+#endif				/* __ASSEMBLY__ */
+#endif				/* __ASM_ARCH_MXC_MX51_PINS_H__ */
diff --git a/include/asm-arm/arch-mx51/sys_proto.h b/include/asm-arm/arch-mx51/sys_proto.h
new file mode 100644
index 0000000000..bf500a8b32
--- /dev/null
+++ b/include/asm-arm/arch-mx51/sys_proto.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+u32 get_cpu_rev(void);
+#define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
+
+#endif
diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h
index 8115a24b78..02cfe4584a 100644
--- a/include/asm-arm/global_data.h
+++ b/include/asm-arm/global_data.h
@@ -44,6 +44,9 @@ typedef	struct	global_data {
 #ifdef CONFIG_VFD
 	unsigned char	vfd_type;	/* display type */
 #endif
+#ifdef CONFIG_FSL_ESDHC
+	unsigned long	sdhc_clk;
+#endif
 #if 0
 	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
 	unsigned long	bus_clk;
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index fec3a7eace..0a4b5be715 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -113,6 +113,61 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
 #define __raw_base_readl(base,off)	__arch_base_getl(base,off)
 
 /*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define out_arch(type,endian,a,v)	__raw_write##type(cpu_to_##endian(v),a)
+#define in_arch(type,endian,a)		endian##_to_cpu(__raw_read##type(a))
+
+#define out_le32(a,v)	out_arch(l,le32,a,v)
+#define out_le16(a,v)	out_arch(w,le16,a,v)
+
+#define in_le32(a)	in_arch(l,le32,a)
+#define in_le16(a)	in_arch(w,le16,a)
+
+#define out_be32(a,v)	out_arch(l,be32,a,v)
+#define out_be16(a,v)	out_arch(w,be16,a,v)
+
+#define in_be32(a)	in_arch(l,be32,a)
+#define in_be16(a)	in_arch(w,be16,a)
+
+#define out_8(a,v)	__raw_writeb(v,a)
+#define in_8(a)		__raw_readb(a)
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+/*
  * Now, pick up the machine-defined IO definitions
  */
 #if 0	/* XXX###XXX */
diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index 3b4632788b..4622557b57 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
@@ -2253,7 +2253,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_ORATISMADI           2269
 #define MACH_TYPE_ORATISOT16           2270
 #define MACH_TYPE_ORATISDESK           2271
-#define MACH_TYPE_V2P_CA9              2272
+#define MACH_TYPE_VEXPRESS             2272
 #define MACH_TYPE_SINTEXO              2273
 #define MACH_TYPE_CM3389               2274
 #define MACH_TYPE_OMAP3_CIO            2275
@@ -2621,6 +2621,84 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_LUX_SFT9             2638
 #define MACH_TYPE_NEMID_TB             2639
 #define MACH_TYPE_TERRIER              2640
+#define MACH_TYPE_TURBOT               2641
+#define MACH_TYPE_SANDDAB              2642
+#define MACH_TYPE_MX35_CICADA          2643
+#define MACH_TYPE_GHI2703D             2644
+#define MACH_TYPE_LUX_SFX9             2645
+#define MACH_TYPE_LUX_SF9G             2646
+#define MACH_TYPE_LUX_EDK9             2647
+#define MACH_TYPE_HW90240              2648
+#define MACH_TYPE_DM365_LEOPARD        2649
+#define MACH_TYPE_MITYOMAPL138         2650
+#define MACH_TYPE_SCAT110              2651
+#define MACH_TYPE_ACER_A1              2652
+#define MACH_TYPE_CMCONTROL            2653
+#define MACH_TYPE_PELCO_LAMAR          2654
+#define MACH_TYPE_RFP43                2655
+#define MACH_TYPE_SK86R0301            2656
+#define MACH_TYPE_CTPXA                2657
+#define MACH_TYPE_EPB_ARM9_A           2658
+#define MACH_TYPE_GURUPLUG             2659
+#define MACH_TYPE_SPEAR310             2660
+#define MACH_TYPE_SPEAR320             2661
+#define MACH_TYPE_ROBOTX               2662
+#define MACH_TYPE_LSXHL                2663
+#define MACH_TYPE_SMARTLITE            2664
+#define MACH_TYPE_CWS2                 2665
+#define MACH_TYPE_M619                 2666
+#define MACH_TYPE_SMARTVIEW            2667
+#define MACH_TYPE_LSA_SALSA            2668
+#define MACH_TYPE_KIZBOX               2669
+#define MACH_TYPE_HTCCHARMER           2670
+#define MACH_TYPE_GUF_NESO_LT          2671
+#define MACH_TYPE_PM9G45               2672
+#define MACH_TYPE_HTCPANTHER           2673
+#define MACH_TYPE_HTCPANTHER_CDMA      2674
+#define MACH_TYPE_REB01                2675
+#define MACH_TYPE_AQUILA               2676
+#define MACH_TYPE_SPARK_SLS_HW2        2677
+#define MACH_TYPE_ESATA_SHEEVAPLUG     2678
+#define MACH_TYPE_SURF7X30             2679
+#define MACH_TYPE_MICRO2440            2680
+#define MACH_TYPE_AM2440               2681
+#define MACH_TYPE_TQ2440               2682
+#define MACH_TYPE_LPC2478OEM           2683
+#define MACH_TYPE_AK880X               2684
+#define MACH_TYPE_COBRA3530            2685
+#define MACH_TYPE_PMPPB                2686
+#define MACH_TYPE_U6715                2687
+#define MACH_TYPE_AXAR1500_SENDER      2688
+#define MACH_TYPE_G30_DVB              2689
+#define MACH_TYPE_VC088X               2690
+#define MACH_TYPE_MIOA702              2691
+#define MACH_TYPE_HPMIN                2692
+#define MACH_TYPE_AK880XAK             2693
+#define MACH_TYPE_ARM926TOMAP850       2694
+#define MACH_TYPE_LKEVM                2695
+#define MACH_TYPE_MW6410               2696
+#define MACH_TYPE_TERASTATION_WXL      2697
+#define MACH_TYPE_CPU8000E             2698
+#define MACH_TYPE_CATANIA              2699
+#define MACH_TYPE_TOKYO                2700
+#define MACH_TYPE_MSM7201A_SURF        2701
+#define MACH_TYPE_MSM7201A_FFA         2702
+#define MACH_TYPE_MSM7X25_SURF         2703
+#define MACH_TYPE_MSM7X25_FFA          2704
+#define MACH_TYPE_MSM7X27_SURF         2705
+#define MACH_TYPE_MSM7X27_FFA          2706
+#define MACH_TYPE_MSM7X30_FFA          2707
+#define MACH_TYPE_QSD8X50_SURF         2708
+#define MACH_TYPE_QSD8X50_COMET        2709
+#define MACH_TYPE_QSD8X50_FFA          2710
+#define MACH_TYPE_QSD8X50A_SURF        2711
+#define MACH_TYPE_QSD8X50A_FFA         2712
+#define MACH_TYPE_XGCP10               2713
+#define MACH_TYPE_MCGWUMTS2A           2714
+#define MACH_TYPE_MOBIKT               2715
+#define MACH_TYPE_MX53_EVK             2716
+#define MACH_TYPE_IGEP0030             2717
+#define MACH_TYPE_AXELL_H40_H50_CTRL   2718
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type
@@ -29514,16 +29592,16 @@ extern unsigned int __machine_arch_type;
 # define machine_is_oratisdesk()	(0)
 #endif
 
-#ifdef CONFIG_MACH_V2P_CA9
+#ifdef CONFIG_MACH_VEXPRESS
 # ifdef machine_arch_type
 #  undef machine_arch_type
 #  define machine_arch_type	__machine_arch_type
 # else
-#  define machine_arch_type	MACH_TYPE_V2P_CA9
+#  define machine_arch_type	MACH_TYPE_VEXPRESS
 # endif
-# define machine_is_v2_ca9()	(machine_arch_type == MACH_TYPE_V2P_CA9)
+# define machine_is_vexpress()	(machine_arch_type == MACH_TYPE_VEXPRESS)
 #else
-# define machine_is_v2_ca9()	(0)
+# define machine_is_vexpress()	(0)
 #endif
 
 #ifdef CONFIG_MACH_SINTEXO
@@ -33901,9 +33979,9 @@ extern unsigned int __machine_arch_type;
 # else
 #  define machine_arch_type	MACH_TYPE_LUX_SFT9
 # endif
-# define machine_is_lux_sft9()	(machine_arch_type == MACH_TYPE_LUX_SFT9)
+# define machine_is_lux_sf9()	(machine_arch_type == MACH_TYPE_LUX_SFT9)
 #else
-# define machine_is_lux_sft9()	(0)
+# define machine_is_lux_sf9()	(0)
 #endif
 
 #ifdef CONFIG_MACH_NEMID_TB
@@ -33930,6 +34008,942 @@ extern unsigned int __machine_arch_type;
 # define machine_is_terrier()	(0)
 #endif
 
+#ifdef CONFIG_MACH_TURBOT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TURBOT
+# endif
+# define machine_is_turbot()	(machine_arch_type == MACH_TYPE_TURBOT)
+#else
+# define machine_is_turbot()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SANDDAB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SANDDAB
+# endif
+# define machine_is_sanddab()	(machine_arch_type == MACH_TYPE_SANDDAB)
+#else
+# define machine_is_sanddab()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX35_CICADA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX35_CICADA
+# endif
+# define machine_is_mx35_cicada()	(machine_arch_type == MACH_TYPE_MX35_CICADA)
+#else
+# define machine_is_mx35_cicada()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GHI2703D
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GHI2703D
+# endif
+# define machine_is_ghi2703d()	(machine_arch_type == MACH_TYPE_GHI2703D)
+#else
+# define machine_is_ghi2703d()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LUX_SFX9
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LUX_SFX9
+# endif
+# define machine_is_lux_sfx9()	(machine_arch_type == MACH_TYPE_LUX_SFX9)
+#else
+# define machine_is_lux_sfx9()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LUX_SF9G
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LUX_SF9G
+# endif
+# define machine_is_lux_sf9g()	(machine_arch_type == MACH_TYPE_LUX_SF9G)
+#else
+# define machine_is_lux_sf9g()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LUX_EDK9
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LUX_EDK9
+# endif
+# define machine_is_lux_edk9()	(machine_arch_type == MACH_TYPE_LUX_EDK9)
+#else
+# define machine_is_lux_edk9()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HW90240
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HW90240
+# endif
+# define machine_is_hw90240()	(machine_arch_type == MACH_TYPE_HW90240)
+#else
+# define machine_is_hw90240()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DM365_LEOPARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DM365_LEOPARD
+# endif
+# define machine_is_dm365_leopard()	(machine_arch_type == MACH_TYPE_DM365_LEOPARD)
+#else
+# define machine_is_dm365_leopard()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MITYOMAPL138
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MITYOMAPL138
+# endif
+# define machine_is_mityomapl138()	(machine_arch_type == MACH_TYPE_MITYOMAPL138)
+#else
+# define machine_is_mityomapl138()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SCAT110
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SCAT110
+# endif
+# define machine_is_scat110()	(machine_arch_type == MACH_TYPE_SCAT110)
+#else
+# define machine_is_scat110()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_A1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACER_A1
+# endif
+# define machine_is_acer_a1()	(machine_arch_type == MACH_TYPE_ACER_A1)
+#else
+# define machine_is_acer_a1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CMCONTROL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CMCONTROL
+# endif
+# define machine_is_cmcontrol()	(machine_arch_type == MACH_TYPE_CMCONTROL)
+#else
+# define machine_is_cmcontrol()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PELCO_LAMAR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PELCO_LAMAR
+# endif
+# define machine_is_pelco_lamar()	(machine_arch_type == MACH_TYPE_PELCO_LAMAR)
+#else
+# define machine_is_pelco_lamar()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RFP43
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RFP43
+# endif
+# define machine_is_rfp43()	(machine_arch_type == MACH_TYPE_RFP43)
+#else
+# define machine_is_rfp43()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SK86R0301
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SK86R0301
+# endif
+# define machine_is_sk86r0301()	(machine_arch_type == MACH_TYPE_SK86R0301)
+#else
+# define machine_is_sk86r0301()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CTPXA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CTPXA
+# endif
+# define machine_is_ctpxa()	(machine_arch_type == MACH_TYPE_CTPXA)
+#else
+# define machine_is_ctpxa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EPB_ARM9_A
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EPB_ARM9_A
+# endif
+# define machine_is_epb_arm9_a()	(machine_arch_type == MACH_TYPE_EPB_ARM9_A)
+#else
+# define machine_is_epb_arm9_a()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GURUPLUG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GURUPLUG
+# endif
+# define machine_is_guruplug()	(machine_arch_type == MACH_TYPE_GURUPLUG)
+#else
+# define machine_is_guruplug()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPEAR310
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPEAR310
+# endif
+# define machine_is_spear310()	(machine_arch_type == MACH_TYPE_SPEAR310)
+#else
+# define machine_is_spear310()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPEAR320
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPEAR320
+# endif
+# define machine_is_spear320()	(machine_arch_type == MACH_TYPE_SPEAR320)
+#else
+# define machine_is_spear320()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ROBOTX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ROBOTX
+# endif
+# define machine_is_robotx()	(machine_arch_type == MACH_TYPE_ROBOTX)
+#else
+# define machine_is_robotx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LSXHL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LSXHL
+# endif
+# define machine_is_lsxhl()	(machine_arch_type == MACH_TYPE_LSXHL)
+#else
+# define machine_is_lsxhl()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTLITE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMARTLITE
+# endif
+# define machine_is_smartlite()	(machine_arch_type == MACH_TYPE_SMARTLITE)
+#else
+# define machine_is_smartlite()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CWS2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CWS2
+# endif
+# define machine_is_cws2()	(machine_arch_type == MACH_TYPE_CWS2)
+#else
+# define machine_is_cws2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_M619
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_M619
+# endif
+# define machine_is_m619()	(machine_arch_type == MACH_TYPE_M619)
+#else
+# define machine_is_m619()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTVIEW
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMARTVIEW
+# endif
+# define machine_is_smartview()	(machine_arch_type == MACH_TYPE_SMARTVIEW)
+#else
+# define machine_is_smartview()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LSA_SALSA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LSA_SALSA
+# endif
+# define machine_is_lsa_salsa()	(machine_arch_type == MACH_TYPE_LSA_SALSA)
+#else
+# define machine_is_lsa_salsa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KIZBOX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KIZBOX
+# endif
+# define machine_is_kizbox()	(machine_arch_type == MACH_TYPE_KIZBOX)
+#else
+# define machine_is_kizbox()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTCCHARMER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTCCHARMER
+# endif
+# define machine_is_htccharmer()	(machine_arch_type == MACH_TYPE_HTCCHARMER)
+#else
+# define machine_is_htccharmer()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GUF_NESO_LT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GUF_NESO_LT
+# endif
+# define machine_is_guf_neso_lt()	(machine_arch_type == MACH_TYPE_GUF_NESO_LT)
+#else
+# define machine_is_guf_neso_lt()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PM9G45
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PM9G45
+# endif
+# define machine_is_pm9g45()	(machine_arch_type == MACH_TYPE_PM9G45)
+#else
+# define machine_is_pm9g45()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTCPANTHER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTCPANTHER
+# endif
+# define machine_is_htcpanther()	(machine_arch_type == MACH_TYPE_HTCPANTHER)
+#else
+# define machine_is_htcpanther()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTCPANTHER_CDMA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTCPANTHER_CDMA
+# endif
+# define machine_is_htcpanther_cdma()	(machine_arch_type == MACH_TYPE_HTCPANTHER_CDMA)
+#else
+# define machine_is_htcpanther_cdma()	(0)
+#endif
+
+#ifdef CONFIG_MACH_REB01
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_REB01
+# endif
+# define machine_is_reb01()	(machine_arch_type == MACH_TYPE_REB01)
+#else
+# define machine_is_reb01()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AQUILA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AQUILA
+# endif
+# define machine_is_aquila()	(machine_arch_type == MACH_TYPE_AQUILA)
+#else
+# define machine_is_aquila()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPARK_SLS_HW2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPARK_SLS_HW2
+# endif
+# define machine_is_spark_sls_hw2()	(machine_arch_type == MACH_TYPE_SPARK_SLS_HW2)
+#else
+# define machine_is_spark_sls_hw2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESATA_SHEEVAPLUG
+# endif
+# define machine_is_sheeva_esata()	(machine_arch_type == MACH_TYPE_ESATA_SHEEVAPLUG)
+#else
+# define machine_is_sheeva_esata()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SURF7X30
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SURF7X30
+# endif
+# define machine_is_msm7x30_surf()	(machine_arch_type == MACH_TYPE_SURF7X30)
+#else
+# define machine_is_msm7x30_surf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MICRO2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MICRO2440
+# endif
+# define machine_is_micro2440()	(machine_arch_type == MACH_TYPE_MICRO2440)
+#else
+# define machine_is_micro2440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AM2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AM2440
+# endif
+# define machine_is_am2440()	(machine_arch_type == MACH_TYPE_AM2440)
+#else
+# define machine_is_am2440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TQ2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TQ2440
+# endif
+# define machine_is_tq2440()	(machine_arch_type == MACH_TYPE_TQ2440)
+#else
+# define machine_is_tq2440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LPC2478OEM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LPC2478OEM
+# endif
+# define machine_is_lpc2478oem()	(machine_arch_type == MACH_TYPE_LPC2478OEM)
+#else
+# define machine_is_lpc2478oem()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AK880X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AK880X
+# endif
+# define machine_is_ak880x()	(machine_arch_type == MACH_TYPE_AK880X)
+#else
+# define machine_is_ak880x()	(0)
+#endif
+
+#ifdef CONFIG_MACH_COBRA3530
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COBRA3530
+# endif
+# define machine_is_cobra3530()	(machine_arch_type == MACH_TYPE_COBRA3530)
+#else
+# define machine_is_cobra3530()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PMPPB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PMPPB
+# endif
+# define machine_is_pmppb()	(machine_arch_type == MACH_TYPE_PMPPB)
+#else
+# define machine_is_pmppb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_U6715
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_U6715
+# endif
+# define machine_is_u6715()	(machine_arch_type == MACH_TYPE_U6715)
+#else
+# define machine_is_u6715()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AXAR1500_SENDER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AXAR1500_SENDER
+# endif
+# define machine_is_axar1500_sender()	(machine_arch_type == MACH_TYPE_AXAR1500_SENDER)
+#else
+# define machine_is_axar1500_sender()	(0)
+#endif
+
+#ifdef CONFIG_MACH_G30_DVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_G30_DVB
+# endif
+# define machine_is_g30_dvb()	(machine_arch_type == MACH_TYPE_G30_DVB)
+#else
+# define machine_is_g30_dvb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VC088X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VC088X
+# endif
+# define machine_is_vc088x()	(machine_arch_type == MACH_TYPE_VC088X)
+#else
+# define machine_is_vc088x()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MIOA702
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MIOA702
+# endif
+# define machine_is_mioa702()	(machine_arch_type == MACH_TYPE_MIOA702)
+#else
+# define machine_is_mioa702()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HPMIN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HPMIN
+# endif
+# define machine_is_hpmin()	(machine_arch_type == MACH_TYPE_HPMIN)
+#else
+# define machine_is_hpmin()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AK880XAK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AK880XAK
+# endif
+# define machine_is_ak880xak()	(machine_arch_type == MACH_TYPE_AK880XAK)
+#else
+# define machine_is_ak880xak()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARM926TOMAP850
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARM926TOMAP850
+# endif
+# define machine_is_arm926tomap850()	(machine_arch_type == MACH_TYPE_ARM926TOMAP850)
+#else
+# define machine_is_arm926tomap850()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LKEVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LKEVM
+# endif
+# define machine_is_lkevm()	(machine_arch_type == MACH_TYPE_LKEVM)
+#else
+# define machine_is_lkevm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MW6410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MW6410
+# endif
+# define machine_is_mw6410()	(machine_arch_type == MACH_TYPE_MW6410)
+#else
+# define machine_is_mw6410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TERASTATION_WXL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TERASTATION_WXL
+# endif
+# define machine_is_terastation_wxl()	(machine_arch_type == MACH_TYPE_TERASTATION_WXL)
+#else
+# define machine_is_terastation_wxl()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CPU8000E
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CPU8000E
+# endif
+# define machine_is_cpu8000e()	(machine_arch_type == MACH_TYPE_CPU8000E)
+#else
+# define machine_is_cpu8000e()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CATANIA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CATANIA
+# endif
+# define machine_is_catania()	(machine_arch_type == MACH_TYPE_CATANIA)
+#else
+# define machine_is_catania()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TOKYO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TOKYO
+# endif
+# define machine_is_tokyo()	(machine_arch_type == MACH_TYPE_TOKYO)
+#else
+# define machine_is_tokyo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7201A_SURF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7201A_SURF
+# endif
+# define machine_is_msm7201a_surf()	(machine_arch_type == MACH_TYPE_MSM7201A_SURF)
+#else
+# define machine_is_msm7201a_surf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7201A_FFA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7201A_FFA
+# endif
+# define machine_is_msm7201a_ffa()	(machine_arch_type == MACH_TYPE_MSM7201A_FFA)
+#else
+# define machine_is_msm7201a_ffa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7X25_SURF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7X25_SURF
+# endif
+# define machine_is_msm7x25_surf()	(machine_arch_type == MACH_TYPE_MSM7X25_SURF)
+#else
+# define machine_is_msm7x25_surf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7X25_FFA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7X25_FFA
+# endif
+# define machine_is_msm7x25_ffa()	(machine_arch_type == MACH_TYPE_MSM7X25_FFA)
+#else
+# define machine_is_msm7x25_ffa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7X27_SURF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7X27_SURF
+# endif
+# define machine_is_msm7x27_surf()	(machine_arch_type == MACH_TYPE_MSM7X27_SURF)
+#else
+# define machine_is_msm7x27_surf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7X27_FFA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7X27_FFA
+# endif
+# define machine_is_msm7x27_ffa()	(machine_arch_type == MACH_TYPE_MSM7X27_FFA)
+#else
+# define machine_is_msm7x27_ffa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7X30_FFA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7X30_FFA
+# endif
+# define machine_is_msm7x30_ffa()	(machine_arch_type == MACH_TYPE_MSM7X30_FFA)
+#else
+# define machine_is_msm7x30_ffa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QSD8X50_SURF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QSD8X50_SURF
+# endif
+# define machine_is_qsd8x50_surf()	(machine_arch_type == MACH_TYPE_QSD8X50_SURF)
+#else
+# define machine_is_qsd8x50_surf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QSD8X50_COMET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QSD8X50_COMET
+# endif
+# define machine_is_qsd8x50_comet()	(machine_arch_type == MACH_TYPE_QSD8X50_COMET)
+#else
+# define machine_is_qsd8x50_comet()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QSD8X50_FFA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QSD8X50_FFA
+# endif
+# define machine_is_qsd8x50_ffa()	(machine_arch_type == MACH_TYPE_QSD8X50_FFA)
+#else
+# define machine_is_qsd8x50_ffa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QSD8X50A_SURF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QSD8X50A_SURF
+# endif
+# define machine_is_qsd8x50a_surf()	(machine_arch_type == MACH_TYPE_QSD8X50A_SURF)
+#else
+# define machine_is_qsd8x50a_surf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QSD8X50A_FFA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QSD8X50A_FFA
+# endif
+# define machine_is_qsd8x50a_ffa()	(machine_arch_type == MACH_TYPE_QSD8X50A_FFA)
+#else
+# define machine_is_qsd8x50a_ffa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_XGCP10
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XGCP10
+# endif
+# define machine_is_adx_xgcp10()	(machine_arch_type == MACH_TYPE_XGCP10)
+#else
+# define machine_is_adx_xgcp10()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MCGWUMTS2A
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MCGWUMTS2A
+# endif
+# define machine_is_mcgwumts2a()	(machine_arch_type == MACH_TYPE_MCGWUMTS2A)
+#else
+# define machine_is_mcgwumts2a()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MOBIKT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MOBIKT
+# endif
+# define machine_is_mobikt()	(machine_arch_type == MACH_TYPE_MOBIKT)
+#else
+# define machine_is_mobikt()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX53_EVK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX53_EVK
+# endif
+# define machine_is_mx53_evk()	(machine_arch_type == MACH_TYPE_MX53_EVK)
+#else
+# define machine_is_mx53_evk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IGEP0030
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IGEP0030
+# endif
+# define machine_is_igep0030()	(machine_arch_type == MACH_TYPE_IGEP0030)
+#else
+# define machine_is_igep0030()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AXELL_H40_H50_CTRL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AXELL_H40_H50_CTRL
+# endif
+# define machine_is_axell_h40_h50_ctrl()	(machine_arch_type == MACH_TYPE_AXELL_H40_H50_CTRL)
+#else
+# define machine_is_axell_h40_h50_ctrl()	(0)
+#endif
+
 /*
  * These have not yet been registered
  */
diff --git a/include/asm-m68k/unaligned.h b/include/asm-m68k/unaligned.h
new file mode 100644
index 0000000000..328aa0c316
--- /dev/null
+++ b/include/asm-m68k/unaligned.h
@@ -0,0 +1,15 @@
+#ifndef _ASM_M68K_UNALIGNED_H
+#define _ASM_M68K_UNALIGNED_H
+
+#ifdef CONFIG_COLDFIRE
+#include <linux/unaligned/be_byteshift.h>
+#else
+#include <linux/unaligned/access_ok.h>
+#endif
+
+#include <linux/unaligned/generic.h>
+
+#define get_unaligned	__get_unaligned_be
+#define put_unaligned	__put_unaligned_be
+
+#endif /* _ASM_M68K_UNALIGNED_H */
diff --git a/include/asm-ppc/ppc4xx-ebc.h b/include/asm-ppc/ppc4xx-ebc.h
index 9680f70d6b..9c17e46252 100644
--- a/include/asm-ppc/ppc4xx-ebc.h
+++ b/include/asm-ppc/ppc4xx-ebc.h
@@ -25,14 +25,24 @@
 #define _PPC4xx_EBC_H_
 
 /*
- * Currently there are two register layout versions for the
- * IBM EBC core used on 4xx PPC's:
+ * Currently there are two register layout versions for the IBM EBC core
+ * used on 4xx PPC's. The following grouping lists the first layout.
+ * Within this group there is a slight variation concerning the bit field
+ * position of the EMPL and EMPH fields:
  */
 #if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
     defined(CONFIG_405EP) || \
     defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define CONFIG_EBC_PPC4xx_IBM_VER1
+#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
+    defined(CONFIG_405EP)
+#define EBC_CFG_EMPH_POS	8
+#define EBC_CFG_EMPL_POS	6
+#else
+#define EBC_CFG_EMPH_POS	6
+#define EBC_CFG_EMPL_POS	8
+#endif
 #endif
 
 /*
@@ -143,10 +153,12 @@
 #define EBC_CFG_EBTC_MASK	PPC_REG_VAL(0, 0x1)
 #define EBC_CFG_EBTC_HI		PPC_REG_VAL(0, 0x0)
 #define EBC_CFG_EBTC_DRIVEN	PPC_REG_VAL(0, 0x1)
-#define EBC_CFG_EMPH_MASK	PPC_REG_VAL(6, 0x3)
-#define EBC_CFG_EMPH_ENCODE(n)	PPC_REG_VAL(6, (static_cast(u32, n)) & 0x3)
-#define EBC_CFG_EMPL_MASK	PPC_REG_VAL(8, 0x3)
-#define EBC_CFG_EMPL_ENCODE(n)	PPC_REG_VAL(8, (static_cast(u32, n)) & 0x3)
+#define EBC_CFG_EMPH_MASK	PPC_REG_VAL(EBC_CFG_EMPH_POS, 0x3)
+#define EBC_CFG_EMPH_ENCODE(n)	PPC_REG_VAL(EBC_CFG_EMPH_POS, \
+						(static_cast(u32, n)) & 0x3)
+#define EBC_CFG_EMPL_MASK	PPC_REG_VAL(EBC_CFG_EMPL_POS, 0x3)
+#define EBC_CFG_EMPL_ENCODE(n)	PPC_REG_VAL(EBC_CFG_EMPH_POS, \
+						(static_cast(u32, n)) & 0x3)
 #define EBC_CFG_CSTC_MASK	PPC_REG_VAL(9, 0x1)
 #define EBC_CFG_CSTC_HI		PPC_REG_VAL(9, 0x0)
 #define EBC_CFG_CSTC_DRIVEN	PPC_REG_VAL(9, 0x1)
diff --git a/include/asm-sh/unaligned-sh4a.h b/include/asm-sh/unaligned-sh4a.h
new file mode 100644
index 0000000000..9f4dd252c9
--- /dev/null
+++ b/include/asm-sh/unaligned-sh4a.h
@@ -0,0 +1,258 @@
+#ifndef __ASM_SH_UNALIGNED_SH4A_H
+#define __ASM_SH_UNALIGNED_SH4A_H
+
+/*
+ * SH-4A has support for unaligned 32-bit loads, and 32-bit loads only.
+ * Support for 64-bit accesses are done through shifting and masking
+ * relative to the endianness. Unaligned stores are not supported by the
+ * instruction encoding, so these continue to use the packed
+ * struct.
+ *
+ * The same note as with the movli.l/movco.l pair applies here, as long
+ * as the load is gauranteed to be inlined, nothing else will hook in to
+ * r0 and we get the return value for free.
+ *
+ * NOTE: Due to the fact we require r0 encoding, care should be taken to
+ * avoid mixing these heavily with other r0 consumers, such as the atomic
+ * ops. Failure to adhere to this can result in the compiler running out
+ * of spill registers and blowing up when building at low optimization
+ * levels. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34777.
+ */
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+static __always_inline u32 __get_unaligned_cpu32(const u8 *p)
+{
+	unsigned long unaligned;
+
+	__asm__ __volatile__ (
+		"movua.l	@%1, %0\n\t"
+		 : "=z" (unaligned)
+		 : "r" (p)
+	);
+
+	return unaligned;
+}
+
+struct __una_u16 { u16 x __attribute__((packed)); };
+struct __una_u32 { u32 x __attribute__((packed)); };
+struct __una_u64 { u64 x __attribute__((packed)); };
+
+static inline u16 __get_unaligned_cpu16(const u8 *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return p[0] | p[1] << 8;
+#else
+	return p[0] << 8 | p[1];
+#endif
+}
+
+/*
+ * Even though movua.l supports auto-increment on the read side, it can
+ * only store to r0 due to instruction encoding constraints, so just let
+ * the compiler sort it out on its own.
+ */
+static inline u64 __get_unaligned_cpu64(const u8 *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (u64)__get_unaligned_cpu32(p + 4) << 32 |
+		    __get_unaligned_cpu32(p);
+#else
+	return (u64)__get_unaligned_cpu32(p) << 32 |
+		    __get_unaligned_cpu32(p + 4);
+#endif
+}
+
+static inline u16 get_unaligned_le16(const void *p)
+{
+	return le16_to_cpu(__get_unaligned_cpu16(p));
+}
+
+static inline u32 get_unaligned_le32(const void *p)
+{
+	return le32_to_cpu(__get_unaligned_cpu32(p));
+}
+
+static inline u64 get_unaligned_le64(const void *p)
+{
+	return le64_to_cpu(__get_unaligned_cpu64(p));
+}
+
+static inline u16 get_unaligned_be16(const void *p)
+{
+	return be16_to_cpu(__get_unaligned_cpu16(p));
+}
+
+static inline u32 get_unaligned_be32(const void *p)
+{
+	return be32_to_cpu(__get_unaligned_cpu32(p));
+}
+
+static inline u64 get_unaligned_be64(const void *p)
+{
+	return be64_to_cpu(__get_unaligned_cpu64(p));
+}
+
+static inline void __put_le16_noalign(u8 *p, u16 val)
+{
+	*p++ = val;
+	*p++ = val >> 8;
+}
+
+static inline void __put_le32_noalign(u8 *p, u32 val)
+{
+	__put_le16_noalign(p, val);
+	__put_le16_noalign(p + 2, val >> 16);
+}
+
+static inline void __put_le64_noalign(u8 *p, u64 val)
+{
+	__put_le32_noalign(p, val);
+	__put_le32_noalign(p + 4, val >> 32);
+}
+
+static inline void __put_be16_noalign(u8 *p, u16 val)
+{
+	*p++ = val >> 8;
+	*p++ = val;
+}
+
+static inline void __put_be32_noalign(u8 *p, u32 val)
+{
+	__put_be16_noalign(p, val >> 16);
+	__put_be16_noalign(p + 2, val);
+}
+
+static inline void __put_be64_noalign(u8 *p, u64 val)
+{
+	__put_be32_noalign(p, val >> 32);
+	__put_be32_noalign(p + 4, val);
+}
+
+static inline void put_unaligned_le16(u16 val, void *p)
+{
+#ifdef __LITTLE_ENDIAN
+	((struct __una_u16 *)p)->x = val;
+#else
+	__put_le16_noalign(p, val);
+#endif
+}
+
+static inline void put_unaligned_le32(u32 val, void *p)
+{
+#ifdef __LITTLE_ENDIAN
+	((struct __una_u32 *)p)->x = val;
+#else
+	__put_le32_noalign(p, val);
+#endif
+}
+
+static inline void put_unaligned_le64(u64 val, void *p)
+{
+#ifdef __LITTLE_ENDIAN
+	((struct __una_u64 *)p)->x = val;
+#else
+	__put_le64_noalign(p, val);
+#endif
+}
+
+static inline void put_unaligned_be16(u16 val, void *p)
+{
+#ifdef __BIG_ENDIAN
+	((struct __una_u16 *)p)->x = val;
+#else
+	__put_be16_noalign(p, val);
+#endif
+}
+
+static inline void put_unaligned_be32(u32 val, void *p)
+{
+#ifdef __BIG_ENDIAN
+	((struct __una_u32 *)p)->x = val;
+#else
+	__put_be32_noalign(p, val);
+#endif
+}
+
+static inline void put_unaligned_be64(u64 val, void *p)
+{
+#ifdef __BIG_ENDIAN
+	((struct __una_u64 *)p)->x = val;
+#else
+	__put_be64_noalign(p, val);
+#endif
+}
+
+/*
+ * Cause a link-time error if we try an unaligned access other than
+ * 1,2,4 or 8 bytes long
+ */
+extern void __bad_unaligned_access_size(void);
+
+#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr),			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)),	\
+	__bad_unaligned_access_size()))));					\
+	}))
+
+#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr),			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)),	\
+	__bad_unaligned_access_size()))));					\
+	}))
+
+#define __put_unaligned_le(val, ptr) ({					\
+	void *__gu_p = (ptr);						\
+	switch (sizeof(*(ptr))) {					\
+	case 1:								\
+		*(u8 *)__gu_p = (__force u8)(val);			\
+		break;							\
+	case 2:								\
+		put_unaligned_le16((__force u16)(val), __gu_p);		\
+		break;							\
+	case 4:								\
+		put_unaligned_le32((__force u32)(val), __gu_p);		\
+		break;							\
+	case 8:								\
+		put_unaligned_le64((__force u64)(val), __gu_p);		\
+		break;							\
+	default:							\
+		__bad_unaligned_access_size();				\
+		break;							\
+	}								\
+	(void)0; })
+
+#define __put_unaligned_be(val, ptr) ({					\
+	void *__gu_p = (ptr);						\
+	switch (sizeof(*(ptr))) {					\
+	case 1:								\
+		*(u8 *)__gu_p = (__force u8)(val);			\
+		break;							\
+	case 2:								\
+		put_unaligned_be16((__force u16)(val), __gu_p);		\
+		break;							\
+	case 4:								\
+		put_unaligned_be32((__force u32)(val), __gu_p);		\
+		break;							\
+	case 8:								\
+		put_unaligned_be64((__force u64)(val), __gu_p);		\
+		break;							\
+	default:							\
+		__bad_unaligned_access_size();				\
+		break;							\
+	}								\
+	(void)0; })
+
+#ifdef __LITTLE_ENDIAN
+# define get_unaligned __get_unaligned_le
+# define put_unaligned __put_unaligned_le
+#else
+# define get_unaligned __get_unaligned_be
+# define put_unaligned __put_unaligned_be
+#endif
+
+#endif /* __ASM_SH_UNALIGNED_SH4A_H */
diff --git a/include/asm-sh/unaligned.h b/include/asm-sh/unaligned.h
new file mode 100644
index 0000000000..2e0d164050
--- /dev/null
+++ b/include/asm-sh/unaligned.h
@@ -0,0 +1,25 @@
+#ifndef _ASM_SH_UNALIGNED_H
+#define _ASM_SH_UNALIGNED_H
+
+/* Copy from linux-kernel. */
+
+#ifdef CONFIG_CPU_SH4A
+/* SH-4A can handle unaligned loads in a relatively neutered fashion. */
+#include <asm/unaligned-sh4a.h>
+#else
+/* Otherwise, SH can't handle unaligned accesses. */
+#include <compiler.h>
+#if defined(__BIG_ENDIAN__)
+#define get_unaligned   __get_unaligned_be
+#define put_unaligned   __put_unaligned_be
+#elif defined(__LITTLE_ENDIAN__)
+#define get_unaligned   __get_unaligned_le
+#define put_unaligned   __put_unaligned_le
+#endif
+
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/generic.h>
+#endif
+
+#endif /* _ASM_SH_UNALIGNED_H */
diff --git a/include/configs/AR405.h b/include/configs/AR405.h
index 73e34bdab2..52ead43aa4 100644
--- a/include/configs/AR405.h
+++ b/include/configs/AR405.h
@@ -93,6 +93,7 @@
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_MII
+#undef CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_BSP
 
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 0a4ba29150..1478ec8c3c 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -580,13 +580,6 @@
  */
 #define CONFIG_ENV_OVERWRITE
 
-#define CONFIG_ETHADDR		00:E0:0C:00:95:01
-#define CONFIG_ETH1ADDR		00:E0:0C:00:95:02
-
-#define CONFIG_IPADDR		10.0.0.2
-#define CONFIG_SERVERIP		10.0.0.1
-#define CONFIG_GATEWAYIP	10.0.0.1
-#define CONFIG_NETMASK		255.0.0.0
 #define CONFIG_NETDEV		eth1
 
 #define CONFIG_HOSTNAME		mpc8313erdb
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index cfed4ca9f8..a8570ce55a 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -616,9 +616,7 @@
 
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR		04:00:00:00:00:0A
 #define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		04:00:00:00:00:0B
 #endif
 
 #define CONFIG_BAUDRATE 115200
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 356586c428..4046f80b5a 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -347,7 +347,8 @@
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	4
-#define CONFIG_SYS_UEC1_INTERFACE_MODE	ENET_100_MII
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE	MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
 #endif
 
 #define CONFIG_UEC_ETH2		/* ETH4 */
@@ -358,7 +359,8 @@
 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK3
 #define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR	0
-#define CONFIG_SYS_UEC2_INTERFACE_MODE	ENET_100_MII
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE	MII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
 #endif
 
 /*
@@ -523,17 +525,11 @@
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_HAS_ETH0				/* add support for "ethaddr" */
-#define CONFIG_ETHADDR	00:04:9f:ef:03:01
 #define CONFIG_HAS_ETH1				/* add support for "eth1addr" */
-#define CONFIG_ETH1ADDR	00:04:9f:ef:03:02
 
 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
 #define CONFIG_SYS_I2C_MAC_OFFSET	0x7f00	/* MAC address offset in I2C EEPROM */
 
-#define CONFIG_IPADDR		10.0.0.2
-#define CONFIG_SERVERIP		10.0.0.1
-#define CONFIG_GATEWAYIP	10.0.0.1
-#define CONFIG_NETMASK		255.0.0.0
 #define CONFIG_NETDEV		eth1
 
 #define CONFIG_HOSTNAME		mpc8323erdb
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index f17f9c7c37..2ad5f60094 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -362,7 +362,8 @@
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	3
-#define CONFIG_SYS_UEC1_INTERFACE_MODE	ENET_100_MII
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE	MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
 #endif
 
 #define CONFIG_UEC_ETH2		/* ETH4 */
@@ -373,7 +374,8 @@
 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK8
 #define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR	4
-#define CONFIG_SYS_UEC2_INTERFACE_MODE	ENET_100_MII
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE	MII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
 #endif
 
 /*
@@ -542,9 +544,7 @@
 
 #if defined(CONFIG_UEC_ETH)
 #define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR	00:04:9f:ef:03:01
 #define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR	00:04:9f:ef:03:02
 #endif
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 6361c45950..bf28d9eaba 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -685,22 +685,14 @@
 #define CONFIG_ENV_OVERWRITE
 
 #if defined(CONFIG_TSEC_ENET)
-#define CONFIG_ETHADDR		00:04:9f:ef:23:33
 #define CONFIG_HAS_ETH1
 #define CONFIG_HAS_ETH0
-#define CONFIG_ETH1ADDR		00:E0:0C:00:7E:21
 #endif
 
-#define CONFIG_IPADDR		192.168.1.253
-
 #define CONFIG_HOSTNAME		mpc8349emds
 #define CONFIG_ROOTPATH		/nfsroot/rootfs
 #define CONFIG_BOOTFILE		uImage
 
-#define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_GATEWAYIP	192.168.1.1
-#define CONFIG_NETMASK		255.255.255.0
-
 #define CONFIG_LOADADDR		800000	/* default location for tftp and bootm */
 
 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index eaa59fde41..52e2851620 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -678,18 +678,6 @@ boards, we say we have two, but don't display a message if we find only one. */
  */
 #define CONFIG_ENV_OVERWRITE
 
-#ifdef CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR		00:E0:0C:00:8C:01
-#endif
-
-#ifdef CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		00:E0:0C:00:8C:02
-#endif
-
-#define CONFIG_IPADDR		192.168.1.253
-#define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_GATEWAYIP	192.168.1.1
-#define CONFIG_NETMASK		255.255.252.0
 #define CONFIG_NETDEV		eth0
 
 #ifdef CONFIG_MPC8349ITX
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 852015512c..b9b5eaba2e 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -400,7 +400,8 @@
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK9
 #define CONFIG_SYS_UEC1_ETH_TYPE	GIGA_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	0
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 #endif
 
 #define CONFIG_UEC_ETH2		/* GETH2 */
@@ -411,7 +412,8 @@
 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK4
 #define CONFIG_SYS_UEC2_ETH_TYPE	GIGA_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR	1
-#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 #endif
 
 /*
@@ -585,9 +587,7 @@
 
 #if defined(CONFIG_UEC_ETH)
 #define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR	00:04:9f:ef:01:01
 #define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
 #endif
 
 #define CONFIG_BAUDRATE 115200
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 1d1f94f3f9..c7bc9cddb8 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -318,7 +318,8 @@
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK9
 #define CONFIG_SYS_UEC1_ETH_TYPE	GIGA_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	2
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_RXID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 #endif
 
 #define CONFIG_UEC_ETH2		/* GETH2 */
@@ -329,7 +330,8 @@
 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK4
 #define CONFIG_SYS_UEC2_ETH_TYPE	GIGA_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR	4
-#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_RXID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 #endif
 
 /*
@@ -504,10 +506,6 @@
 #define CONFIG_HAS_ETH1
 #define CONFIG_HAS_ETH2
 #define CONFIG_HAS_ETH3
-#define CONFIG_ETHADDR	00:04:9f:ef:01:01
-#define CONFIG_ETH1ADDR	00:04:9f:ef:01:02
-#define CONFIG_ETH2ADDR	00:04:9f:ef:01:03
-#define CONFIG_ETH3ADDR	00:04:9f:ef:01:04
 #endif
 
 #define CONFIG_BAUDRATE 115200
@@ -516,10 +514,6 @@
 #define CONFIG_HOSTNAME	mpc8360erdk
 #define CONFIG_BOOTFILE	uImage
 
-#define CONFIG_IPADDR		10.0.0.99
-#define CONFIG_SERVERIP		10.0.0.2
-#define CONFIG_GATEWAYIP	10.0.0.2
-#define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_ROOTPATH		/nfsroot/
 
 #define	CONFIG_BOOTDELAY 2	/* -1 disables auto-boot */
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 63f1d855e0..65d49ecd92 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -637,9 +637,7 @@ extern int board_pci_host_broken(void);
 
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR		00:E0:0C:00:83:79
 #define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		00:E0:0C:00:83:78
 #endif
 
 #define CONFIG_BAUDRATE 115200
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 913184c828..ca60272263 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -643,20 +643,8 @@
  */
 #define CONFIG_ENV_OVERWRITE
 
-#ifdef CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR		00:04:9f:ef:04:01
-#endif
-
-#ifdef CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		00:04:9f:ef:04:02
-#endif
-
 #define CONFIG_HAS_FSL_DR_USB
 
-#define CONFIG_IPADDR		10.0.0.2
-#define CONFIG_SERVERIP		10.0.0.1
-#define CONFIG_GATEWAYIP	10.0.0.1
-#define CONFIG_NETMASK		255.0.0.0
 #define CONFIG_NETDEV		eth1
 
 #define CONFIG_HOSTNAME		mpc837x_rdb
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 128a7e13f8..6973538a8c 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -333,7 +333,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16
 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR       7
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 #endif
 
 #define CONFIG_UEC_ETH2         /* GETH2 */
@@ -344,7 +345,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16
 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR       1
-#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 #endif
 #endif /* CONFIG_QE */
 
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index ae2fc19f4b..9b81703741 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -62,6 +62,12 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_L2_CACHE				/* toggle L2 cache	*/
 #define CONFIG_BTB				/* toggle branch predition */
 
+#ifdef CONFIG_MK_NAND
+#define CONFIG_NAND_U_BOOT		1
+#define CONFIG_RAMBOOT_NAND		1
+#define CONFIG_RAMBOOT_TEXT_BASE	0xf8f82000
+#endif
+
 /*
  * Only possible on E500 Version 2 or newer cores.
  */
@@ -74,16 +80,29 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 
 /*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(512 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+/*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
 #define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR
 						/* physical addr of CCSRBAR */
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR
 						/* PQII uses CONFIG_SYS_IMMR */
 
+#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSRBAR_DEFAULT	CONFIG_SYS_CCSRBAR
+#else
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#endif
+
 #define CONFIG_SYS_PCI1_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
 
@@ -152,8 +171,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_BCSR_BASE_PHYS	CONFIG_SYS_BCSR_BASE
 
 /*Chip select 0 - Flash*/
-#define CONFIG_SYS_BR0_PRELIM		0xfe000801
-#define	CONFIG_SYS_OR0_PRELIM		0xfe000ff7
+#define CONFIG_FLASH_BR_PRELIM		0xfe000801
+#define	CONFIG_FLASH_OR_PRELIM		0xfe000ff7
 
 /*Chip select 1 - BCSR*/
 #define CONFIG_SYS_BR1_PRELIM		0xf8000801
@@ -175,12 +194,33 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
+#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 
 /* Chip select 3 - NAND */
+#ifndef CONFIG_NAND_SPL
 #define CONFIG_SYS_NAND_BASE		0xFC000000
+#else
+#define CONFIG_SYS_NAND_BASE		0xFFF00000
+#endif
+
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START \
+	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE, }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
@@ -200,8 +240,18 @@ extern unsigned long get_clock_freq(void);
 				| OR_FCM_SCY_1 \
 				| OR_FCM_TRLX \
 				| OR_FCM_EHTR)
+
+#ifdef CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_NAND_BR_PRELIM	/* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_NAND_OR_PRELIM	/* NAND Options */
+#define CONFIG_SYS_BR3_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
 #define CONFIG_SYS_BR3_PRELIM	CONFIG_NAND_BR_PRELIM /* NAND Base Address */
 #define CONFIG_SYS_OR3_PRELIM	CONFIG_NAND_OR_PRELIM /* NAND Options */
+#endif
 
 /*
  * SDRAM on the LocalBus
@@ -326,12 +376,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR       7
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16	/* CLK16 for RMII */
 #define CONFIG_SYS_UEC1_ETH_TYPE       FAST_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR       8	/* 0x8 for RMII */
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 #endif /* CONFIG_UEC_ETH1 */
 
@@ -345,12 +397,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR       1
-#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16	/* CLK 16 for RMII */
 #define CONFIG_SYS_UEC2_ETH_TYPE       FAST_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR       0x9	/* 0x9 for RMII */
-#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_RMII
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 #endif /* CONFIG_UEC_ETH2 */
 
@@ -364,12 +418,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
 #define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC3_PHY_ADDR       2
-#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 #define CONFIG_SYS_UEC3_TX_CLK		QE_CLK16 /* CLK_16 for RMII */
 #define CONFIG_SYS_UEC3_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC3_PHY_ADDR	0xA     /* 0xA for RMII */
-#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_100_RMII
+#define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 #endif /* CONFIG_UEC_ETH3 */
 
@@ -383,12 +439,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
 #define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC4_PHY_ADDR       3
-#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 #define CONFIG_SYS_UEC4_TX_CLK		QE_CLK16 /* CLK16 for RMII */
 #define CONFIG_SYS_UEC4_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC4_PHY_ADDR	0xB     /* 0xB for RMII */
-#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII
+#define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 #endif /* CONFIG_UEC_ETH4 */
 
@@ -401,7 +459,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC6_TX_CLK         QE_CLK_NONE
 #define CONFIG_SYS_UEC6_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC6_PHY_ADDR       4
-#define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII
+#define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII
+#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
 #endif /* CONFIG_UEC_ETH6 */
 
 #undef CONFIG_UEC_ETH8         /* GETH8 */
@@ -413,7 +472,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC8_TX_CLK         QE_CLK_NONE
 #define CONFIG_SYS_UEC8_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC8_PHY_ADDR       6
-#define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII
+#define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII
+#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
 #endif /* CONFIG_UEC_ETH8 */
 
 #endif /* CONFIG_QE */
@@ -437,10 +497,18 @@ extern unsigned long get_clock_freq(void);
 /*
  * Environment
  */
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_ENV_IS_IN_NAND	1
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
+#else
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* 256K(one sector) for env */
 #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 6310cfc339..89799af3f3 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -287,12 +287,8 @@
 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 	"addmisc=setenv bootargs ${bootargs} mem=${mem}\0"		\
 	"nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
-	"nand_boot=run nandargs addip addtty addmisc;bootm ${kernel_addr}\0" \
 	"nand_boot_fdt=run nandargs addip addtty addmisc;"		\
 		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"run nfsargs addip addtty addmisc;"			\
-		"bootm\0"						\
 	"net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};"		\
 		"tftp  ${fdt_addr_r} ${fdt_file};"			\
 		"run nfsargs addip addtty addmisc;"			\
@@ -353,7 +349,6 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
-#define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_FAT
@@ -366,7 +361,6 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_USB
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
 
 /* POST support */
 #define CONFIG_POST		(CONFIG_SYS_POST_MEMORY |	\
diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h
index 58b8c8c395..24484fd0c8 100644
--- a/include/configs/afeb9260.h
+++ b/include/configs/afeb9260.h
@@ -26,8 +26,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		18429952	/* from 18.432 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK		18429952	/* from 18.432 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_AT91SAM9260	1	/* It's an Atmel AT91SAM9260 SoC*/
@@ -45,6 +47,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index 322718f441..44c287033f 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -27,8 +27,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		12000000	/* 12 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
@@ -47,6 +49,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index 590c69a19c..d39e8f28a9 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -25,6 +25,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 #define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
 #define AT91C_MASTER_CLOCK	59904000	/* peripheral clock (AT91C_MASTER_CLOCK / 3) */
@@ -122,7 +124,14 @@
 #define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
 #define CONFIG_SYS_MEMTEST_END			CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
 
-#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_MULTI		1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#else
+#define CONFIG_DRIVER_ETHER		1
+#endif
+
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_AT91C_USE_RMII
 
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index b4f075ebc5..145c3c37da 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -26,6 +26,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 /*
  * from 18.432 MHz crystal
@@ -145,7 +147,13 @@
 /*
  * Network Driver Setting
  */
-#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_MULTI		1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#else
+#define CONFIG_DRIVER_ETHER		1
+#endif
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_AT91C_USE_RMII
 
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 0509011252..b89242b3a1 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -27,8 +27,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		18432000	/* 18.432 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
@@ -52,6 +54,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index fbf7389b90..df8181b755 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -27,8 +27,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		18432000	/* 18.432 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
@@ -50,6 +52,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 571351ca7d..5cafa1ef4a 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -28,7 +28,7 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		16367660	/* 16.367 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	16367660	/* 16.367 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
@@ -49,6 +49,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
@@ -69,9 +70,9 @@
 
 /* LED */
 #define CONFIG_AT91_LED
-#define	CONFIG_RED_LED		AT91_PIN_PB7	/* this is the power led */
-#define	CONFIG_GREEN_LED	AT91_PIN_PB8	/* this is the user1 led */
-#define	CONFIG_YELLOW_LED	AT91_PIN_PC29	/* this is the user2 led */
+#define	CONFIG_RED_LED		AT91_PIO_PORTB, 7	/* the power led */
+#define	CONFIG_GREEN_LED	AT91_PIO_PORTB, 8	/* the user1 led */
+#define	CONFIG_YELLOW_LED	AT91_PIO_PORTC, 29	/* the user2 led */
 
 #define CONFIG_BOOTDELAY	3
 
@@ -147,39 +148,36 @@
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define MASTER_PLL_MUL		171
 #define MASTER_PLL_DIV		14
+#define MASTER_PLL_OUT		3
 
 /* clocks */
 #define CONFIG_SYS_MOR_VAL						\
-		(AT91_PMC_MOSCEN |					\
-		 (255 << 8))		/* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL						\
-		(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
-		 AT91_PMC_OUT |						\
-		 AT91_PMC_PLLCOUNT |	/* PLL Counter */		\
-		 (2 << 28) |		/* PLL Clock Frequency Range */	\
-		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+		(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
+#define CONFIG_SYS_PLLAR_VAL					\
+	(AT91_PMC_PLLAR_29 |					\
+	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |			\
+	AT91_PMC_PLLXR_PLLCOUNT(63) |				\
+	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | 		\
+	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
 
 /* PCK/2 = MCK Master Clock from PLLA */
 #define	CONFIG_SYS_MCKR1_VAL		\
-		(AT91_PMC_CSS_SLOW |	\
-		 AT91_PMC_PRES_1 |	\
-		 AT91SAM9_PMC_MDIV_2 |	\
-		 AT91_PMC_PDIV_1)
+	(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |	\
+	 AT91_PMC_MCKR_MDIV_2)
+
 /* PCK/2 = MCK Master Clock from PLLA */
 #define	CONFIG_SYS_MCKR2_VAL		\
-		(AT91_PMC_CSS_PLLA |	\
-		 AT91_PMC_PRES_1 |	\
-		 AT91SAM9_PMC_MDIV_2 |	\
-		 AT91_PMC_PDIV_1)
+	(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | 	\
+	AT91_PMC_MCKR_MDIV_2)
 
 /* define PDC[31:16] as DATA[31:16] */
 #define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
 /* no pull-up for D[31:16] */
 #define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
-	(AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |	\
-	 AT91_MATRIX_EBI0_CS1A_SDRAMC)
+#define CONFIG_SYS_MATRIX_EBICSA_VAL					\
+	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
+	 AT91_MATRIX_CSA_EBI_CS1A)
 
 /* SDRAM */
 /* SDRAMC_MR Mode register */
@@ -221,33 +219,32 @@
 #define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
 
 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL					\
-		(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |	\
-		 AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
-#define CONFIG_SYS_SMC0_PULSE0_VAL					\
-		(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |	\
-		 AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
+#define CONFIG_SYS_SMC0_SETUP0_VAL				\
+	(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
+	 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL				\
+	(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
+	 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
 #define CONFIG_SYS_SMC0_CYCLE0_VAL	\
-		(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
+	(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
 #define CONFIG_SYS_SMC0_MODE0_VAL				\
-		(AT91_SMC_READMODE | AT91_SMC_WRITEMODE |	\
-		 AT91_SMC_DBW_16 |				\
-		 AT91_SMC_TDFMODE |				\
-		 AT91_SMC_TDF_(6))
+	(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |		\
+	 AT91_SMC_MODE_DBW_16 |					\
+	 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
 
 /* user reset enable */
 #define CONFIG_SYS_RSTC_RMR_VAL			\
 		(AT91_RSTC_KEY |		\
-		AT91_RSTC_PROCRST |		\
-		AT91_RSTC_RSTTYP_WAKEUP |	\
-		AT91_RSTC_RSTTYP_WATCHDOG)
+		AT91_RSTC_MR_URSTEN |		\
+		AT91_RSTC_MR_ERSTL(15))
 
 /* Disable Watchdog */
 #define CONFIG_SYS_WDTC_WDMR_VAL				\
-		(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |	\
-		 AT91_WDT_WDV |					\
-		 AT91_WDT_WDDIS |				\
-		 AT91_WDT_WDD)
+		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
+		 AT91_WDT_MR_WDV(0xfff) |			\
+		 AT91_WDT_MR_WDDIS |				\
+		 AT91_WDT_MR_WDD(0xfff))
+
 #endif
 
 #else
@@ -264,9 +261,15 @@
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTD, 15
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTA, 22
+/*
+#define CONFIG_SYS_NAND_ENABLE_PIN  AT91_PIN_PD15
+#define CONFIG_SYS_NAND_READY_PIN  AT91_PIN_PA22
+*/
+
 
+#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
 #endif
 
 /* Ethernet */
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 06184e78ec..44c5496b63 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -27,8 +27,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		12000000	/* from 12 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* from 12 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
@@ -50,6 +52,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 6fad75d6be..e8fcd66c94 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -27,8 +27,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		12000000	/* 12 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
@@ -47,6 +49,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index be478b24e4..ffe83f091c 100644
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -25,6 +25,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 #define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
 #define AT91C_MASTER_CLOCK	(AT91C_MAIN_CLOCK/3)	/* peripheral clock */
@@ -152,7 +154,13 @@
 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
 #define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
 
-#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_MULTI		1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#else
+#define CONFIG_DRIVER_ETHER		1
+#endif
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_AT91C_USE_RMII
 
diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h
index 4ef8566ea2..fb6f79a423 100644
--- a/include/configs/cpu9260.h
+++ b/include/configs/cpu9260.h
@@ -31,9 +31,11 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 #define CONFIG_DISPLAY_CPUINFO	1
 
-#define AT91_MAIN_CLOCK		18432000
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1
@@ -242,6 +244,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h
index 8746f702da..b4fda76731 100644
--- a/include/configs/cpuat91.h
+++ b/include/configs/cpuat91.h
@@ -26,6 +26,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 #ifdef CONFIG_CPUAT91_RAM
 #define CONFIG_SKIP_LOWLEVEL_INIT	1
 #define CONFIG_SKIP_RELOCATE_UBOOT	1
@@ -128,7 +130,13 @@
 #define CONFIG_SYS_MEMTEST_END			\
 	(CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512 * 1024)
 
-#define CONFIG_DRIVER_ETHER			1
+#define CONFIG_NET_MULTI		1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#else
+#define CONFIG_DRIVER_ETHER		1
+#endif
 #define CONFIG_NET_RETRY_COUNT			20
 #define CONFIG_AT91C_USE_RMII			1
 #define CONFIG_PHY_ADDRESS			(1 << 5)
diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index f4fd808e46..efa2780992 100644
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -26,6 +26,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 #define AT91C_MAIN_CLOCK	184320000	/* from 3.6864 MHz crystal (3686400 * 50) */
 #define AT91C_MASTER_CLOCK	46080000	/* (AT91C_MAIN_CLOCK/4)	peripheral clock */
@@ -126,7 +128,13 @@
 #define CONFIG_SYS_ALT_MEMTEST			1
 #define CONFIG_SYS_MEMTEST_SCRATCH		CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 4
 
-#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_MULTI		1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#else
+#define CONFIG_DRIVER_ETHER		1
+#endif
 #define CONFIG_NET_RETRY_COUNT		20
 #undef CONFIG_AT91C_USE_RMII
 
diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h
index 432cd57a70..0f58e11e74 100644
--- a/include/configs/da830evm.h
+++ b/include/configs/da830evm.h
@@ -27,6 +27,7 @@
 /*
  * Board
  */
+#define CONFIG_DRIVER_TI_EMAC
 
 /*
  * SoC Configuration
@@ -103,14 +104,15 @@
 #define CONFIG_NAND_DAVINCI
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
-#define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
-#define CONFIG_ENV_SIZE			(128 << 10)
+#define CONFIG_ENV_OFFSET		(512 << 10)
+#define CONFIG_ENV_SIZE			(512 << 10)
 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 #define CONFIG_SYS_NAND_CS		3
 #define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 #define CONFIG_SYS_CLE_MASK		0x10
 #define CONFIG_SYS_ALE_MASK		0x8
-#define CONFIG_SYS_NAND_HW_ECC
 #define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
 #define NAND_MAX_CHIPS			1
 #define DEF_BOOTM			""
@@ -216,8 +218,7 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_UBI
-#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE
 #endif
 
 #ifdef CONFIG_USE_SPIFLASH
@@ -268,4 +269,15 @@
 #endif /* CONFIG_MUSB_UDC */
 
 #endif /* CONFIG_USB_DA8XX */
+
+#ifdef CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT		"nand0=davinci_nand.1"
+#define PART_BOOT		"512k(bootloader)ro,"
+#define PART_PARAMS		"512k(params)ro,"
+#define PART_KERNEL		"4m(kernel),"
+#define PART_REST		"-(filesystem)"
+#define MTDPARTS_DEFAULT        \
+	"mtdparts=davinci_nand.1:" PART_BOOT PART_PARAMS PART_KERNEL PART_REST
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h
index c6e1d107fd..6f99ae087d 100644
--- a/include/configs/davinci_dm365evm.h
+++ b/include/configs/davinci_dm365evm.h
@@ -85,6 +85,44 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_MAX_CHIPS	2
 
+#define PINMUX4_USBDRVBUS_BITCLEAR       0x3000
+#define PINMUX4_USBDRVBUS_BITSET         0x2000
+
+/* USB Configuration */
+#define CONFIG_USB_DAVINCI
+#define CONFIG_MUSB_HCD
+
+#ifdef CONFIG_USB_DAVINCI
+#define CONFIG_CMD_USB         /* include support for usb      */
+#define CONFIG_CMD_STORAGE     /* include support for usb      */
+#define CONFIG_CMD_FAT         /* include support for FAT/storage*/
+#define CONFIG_DOS_PARTITION   /* include support for FAT/storage*/
+#endif
+
+#ifdef CONFIG_MUSB_HCD         /* include support for usb host */
+#define CONFIG_CMD_USB         /* include support for usb cmd */
+#define CONFIG_USB_STORAGE     /* MSC class support */
+#define CONFIG_CMD_STORAGE     /* inclue support for usb-storage cmd */
+#define CONFIG_CMD_FAT         /* inclue support for FAT/storage */
+#define CONFIG_DOS_PARTITION   /* inclue support for FAT/storage */
+
+#ifdef CONFIG_USB_KEYBOARD     /* HID class support */
+#define CONFIG_SYS_USB_EVENT_POLL
+
+#define CONFIG_PREBOOT "usb start"
+#endif /* CONFIG_USB_KEYBOARD */
+#endif /* CONFIG_MUSB_HCD */
+
+#ifdef CONFIG_MUSB_UDC
+#define CONFIG_USB_DEVICE              1
+#define CONFIG_USB_TTY                 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV   1
+#define CONFIG_USBD_VENDORID           0x0451
+#define CONFIG_USBD_PRODUCTID          0x5678
+#define CONFIG_USBD_MANUFACTURER       "Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME       "DM365VM"
+#endif /* CONFIG_MUSB_UDC */
+
 /* U-Boot command configuration */
 #include <config_cmd_default.h>
 
diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h
new file mode 100644
index 0000000000..4ff4a85cb5
--- /dev/null
+++ b/include/configs/eb_cpux9k2.h
@@ -0,0 +1,415 @@
+/*
+ * (C) Copyright 2008-2009
+ * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
+ * Jens Scharsig <esw@bus-elektronik.de>
+ *
+ * Configuation settings for the EB+CPUx9K2 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CONFIG_EB_CPUx9K2_H_
+#define _CONFIG_EB_CPUx9K2_H_
+
+/*--------------------------------------------------------------------------*/
+
+#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
+#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
+#define CONFIG_EB_CPUX9K2	1	/* on an EP+CPUX9K2 Board	*/
+#define USE_920T_MMU		1
+
+#define CONFIG_VERSION_VARIABLE 1
+#define CONFIG_IDENT_STRING	" on EB+CPUx9K2"
+
+#include <asm/arch/hardware.h>	/* needed for port definitions */
+
+#define CONFIG_MISC_INIT_R
+
+/*--------------------------------------------------------------------------*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
+
+#define CONFIG_SYS_BOOT_SIZE		0x00 /* 0 KBytes */
+#define CONFIG_SYS_U_BOOT_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_U_BOOT_SIZE		0x60000 /* 384 KBytes */
+
+
+#define CONFIG_BOOT_RETRY_TIME		30
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_PROMPT	"U-Boot> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+
+#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
+
+/*
+ * ARM asynchronous clock
+ */
+
+#define AT91C_MAIN_CLOCK	179404800	/* from 12.288 MHz * 73 / 5 */
+#define AT91C_MASTER_CLOCK	(AT91C_MAIN_CLOCK / 3)
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_HZ_CLOCK 	(AT91C_MASTER_CLOCK / 2)
+
+#define AT91_SLOW_CLOCK			32768		/* slow clock */
+
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR	1
+/* flash */
+#define CONFIG_SYS_EBI_CFGR_VAL		0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL		0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define CONFIG_SYS_PLLAR_VAL		0x20483E05 /* 179.4048 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL		0x104C3E0A /* 47.3088 MHz (for USB) */
+#define CONFIG_SYS_MCKR_VAL		0x00000202 /* PCK/3 = MCK Clock */
+
+/*
+ * Size of malloc() pool
+ */
+
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 520*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * sdram
+ */
+
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM 			0x20000000
+#define PHYS_SDRAM_SIZE			0x04000000  /* 64 megs */
+
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					PHYS_SDRAM_SIZE - 0x00400000 - \
+					CONFIG_SYS_MALLOC_LEN)
+
+#define CONFIG_SYS_PIOC_ASR_VAL		0xFFFF0000 /* PIOC as D16/D31 */
+#define CONFIG_SYS_PIOC_BSR_VAL		0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL		0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL		0x00000002 /* CS1=SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL		0x2188c159 /* set up the SDRAM */
+#define CONFIG_SYS_SDRAM		0x20000000 /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM1		0x20000080 /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM_VAL		0x00000000 /* value written to SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL		0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1		0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2		0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3		0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL		0x000002E0 /* Write refresh rate */
+
+/*
+ * Command line configuration
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_I2C_CMD_NO_FLAT
+#define CONFIG_I2C_CMD_TREE
+
+#define CONFIG_SYS_LONGHELP
+
+/*
+ * Filesystems
+ */
+
+#define CONFIG_JFFS2_NAND		1
+
+#ifndef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV 		"nand0"
+#define CONFIG_JFFS2_PART_OFFSET 	0
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#else
+#define MTDIDS_DEFAULT		"nor0=0,nand0=1"
+#define MTDPARTS_DEFAULT	"mtdparts="				\
+					"0:"				\
+					"384k(U-Boot),"			\
+					"128k(Env),"			\
+					"128k(Splash)," 		\
+					"4M(Kernel),"			\
+					"-(FS)"				\
+					";"				\
+					"1:"				\
+					"-(jffs2)"
+#endif /* CONFIG_JFFS2_CMDLINE */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART/CONSOLE
+ */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 19200, 38400, 57600, 9600 }
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AT91RM9200_USART
+#define CONFIG_DBGU			/* define DBGU as console */
+
+/*
+ * network
+ */
+#define CONFIG_NET_MULTI		1
+
+#define CONFIG_NET_RETRY_COUNT		10
+#define CONFIG_RESET_PHY_R		1
+
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_DRIVER_AT91EMAC_QUIET	1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#define CONFIG_MII			1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * I2C-Bus
+ */
+
+#define CONFIG_SYS_I2C_SPEED		50000
+#define CONFIG_SYS_I2C_SLAVE		0 		/* not used */
+
+#ifndef CONFIG_HARD_I2C
+#define CONFIG_SOFT_I2C
+
+/* Software  I2C driver configuration */
+
+#define AT91_PIN_SDA			(1<<25)		/* AT91C_PIO_PA25 */
+#define AT91_PIN_SCL			(1<<26)		/* AT91C_PIO_PA26 */
+
+#define CONFIG_SYS_I2C_INIT_BOARD
+
+#define I2C_INIT	i2c_init_board();
+#define I2C_ACTIVE	writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
+#define I2C_TRISTATE	writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
+#define I2C_READ	((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
+#define I2C_SDA(bit)						\
+	if (bit)						\
+		writel(AT91_PMX_AA_TWD, &pio->pioa.sodr);	\
+	else							\
+		writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
+#define I2C_SCL(bit)						\
+	if (bit)						\
+		writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr);	\
+	else							\
+		writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);
+
+#define I2C_DELAY	udelay(2500000/CONFIG_SYS_I2C_SPEED)
+
+#endif	/* CONFIG_HARD_I2C */
+
+/* I2C-RTC */
+
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_DS1338
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#endif
+
+/* EEPROM */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+
+/* FLASH organization */
+
+/*  NOR-FLASH */
+
+#define CONFIG_FLASH_CFI_DRIVER	1
+
+#define PHYS_FLASH_1			0x10000000
+#define PHYS_FLASH_SIZE			0x01000000  /* 16 megs main flash */
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_PROTECTION	1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#define CONFIG_SYS_FLASH_ERASE_TOUT	6000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	2000
+
+/* NAND */
+
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_DBW_8		1
+
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+
+/* Status LED's */
+
+#define CONFIG_STATUS_LED		1
+#define CONFIG_BOARD_SPECIFIC_LED	1
+
+#define STATUS_LED_BOOT			1
+#define STATUS_LED_ACTIVE		0
+
+#define STATUS_LED_BIT			1	/* AT91C_PIO_PD0 green LED */
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_STATE 		STATUS_LED_OFF		/* BLINKING */
+#define STATUS_LED_BIT1			2	/* AT91C_PIO_PD1  red LED */
+#define STATUS_LED_STATE1		STATUS_LED_ON		/* BLINKING */
+#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 4)
+
+#define	CONFIG_VIDEO			1
+
+/* Options */
+
+#ifdef CONFIG_VIDEO
+
+#define CONFIG_VIDEO_VCXK			1
+
+#define CONFIG_SPLASH_SCREEN			1
+
+#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN	4
+#define CONFIG_SYS_VCXK_BASE	0x30000000
+
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN		(1<<3)
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT	piob
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR		odr
+
+#define CONFIG_SYS_VCXK_ENABLE_PIN		(1<<5)
+#define CONFIG_SYS_VCXK_ENABLE_PORT		piob
+#define CONFIG_SYS_VCXK_ENABLE_DDR		oer
+
+#define CONFIG_SYS_VCXK_REQUEST_PIN		(1<<2)
+#define CONFIG_SYS_VCXK_REQUEST_PORT		piob
+#define CONFIG_SYS_VCXK_REQUEST_DDR		oer
+
+#define CONFIG_SYS_VCXK_INVERT_PIN		(1<<4)
+#define CONFIG_SYS_VCXK_INVERT_PORT		piob
+#define CONFIG_SYS_VCXK_INVERT_DDR		oer
+
+#define CONFIG_SYS_VCXK_RESET_PIN		(1<<6)
+#define CONFIG_SYS_VCXK_RESET_PORT		piob
+#define CONFIG_SYS_VCXK_RESET_DDR		oer
+
+#endif	/* CONFIG_VIDEO */
+
+/* Environment */
+
+#define CONFIG_BOOTDELAY		5
+
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x60000)
+#define CONFIG_ENV_SIZE			0x20000 /* sectors are 128K here */
+
+#define CONFIG_BAUDRATE 		115200
+
+#define CONFIG_BOOTCOMMAND		"run nfsboot"
+
+#define CONFIG_NFSBOOTCOMMAND 						\
+		"dhcp $(copy_addr) uImage_cpux9k2;"			\
+		"run bootargsdefaults;"					\
+		"set bootargs $(bootargs) boot=nfs "			\
+		";echo $(bootargs)"					\
+	";bootm"
+
+#define CONFIG_EXTRA_ENV_SETTINGS 					\
+	"displaywidth=256\0"						\
+	"displayheight=512\0"						\
+	"displaybsteps=1023\0"						\
+	"ubootaddr=10000000\0"						\
+	"splashimage=10080000\0"					\
+	"kerneladdr=100A0000\0"						\
+	"kernelsize=00400000\0"						\
+	"rootfsaddr=104A0000\0"						\
+	"copy_addr=21200000\0"						\
+	"rootfssize=00B60000\0"						\
+	"bootargsdefaults=set bootargs "				\
+		"console=ttyS0,115200 "					\
+		"video=vcxk_fb:xres:${displaywidth},"			\
+			"yres:${displayheight},"			\
+			"bres:${displaybsteps} "			\
+		"mem=62M "						\
+		"panic=10 "						\
+		"uboot=\\\"${ver}\\\" "					\
+		"\0"							\
+	"update_kernel=protect off $(kerneladdr) +$(kernelsize);"	\
+		"dhcp $(copy_addr) uImage_cpux9k2;"			\
+		"erase $(kerneladdr) +$(kernelsize);"			\
+		"cp.b $(fileaddr) $(kerneladdr) $(filesize);"		\
+		"protect on $(kerneladdr) +$(kernelsize)"		\
+		"\0"							\
+	"update_root=protect off $(rootfsaddr) +$(rootfssize);"		\
+		"dhcp $(copy_addr) rfs;"				\
+		"erase $(rootfsaddr) +$(rootfssize);"			\
+		"cp.b $(fileaddr) $(rootfsaddr) $(filesize);"		\
+		"\0"							\
+	"update_uboot=protect off 10000000 1005FFFF;"			\
+		"dhcp $(copy_addr) u-boot_eb_cpux9k2;"			\
+		"erase 10000000 1005FFFF;"				\
+		"cp.b $(fileaddr) $(ubootaddr) $(filesize);"		\
+		"protect on 10000000 1005FFFF;reset\0"			\
+	"update_splash=protect off $(splashimage) +20000;"		\
+		"dhcp $(copy_addr) splash_eb_cpux9k2.bmp;"		\
+		"erase $(splashimage) +20000;"				\
+		"cp.b $(fileaddr) 10080000 $(filesize);"		\
+		"protect on $(splashimage) +20000;reset\0"		\
+	"emergency=run bootargsdefaults;"				\
+		"set bootargs $(bootargs) root=initramfs boot=emergency " \
+		";bootm $(kerneladdr)\0"				\
+	"netemergency=run bootargsdefaults;"				\
+		"dhcp $(copy_addr) uImage_cpux9k2;"			\
+		"set bootargs $(bootargs) root=initramfs boot=emergency " \
+		";bootm $(copy_addr)\0"					\
+	"norboot=run bootargsdefaults;"					\
+		"set bootargs $(bootargs) root=initramfs boot=local "	\
+		";bootm $(kerneladdr)\0"				\
+	"nandboot=run bootargsdefaults;"				\
+		"set bootargs $(bootargs) root=initramfs boot=nand "	\
+		";bootm $(kerneladdr)\0"				\
+	"uu=run update_uboot\0"						\
+	"ur=run update_root;run nk\0"					\
+	"nk=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \
+		"boot=local "						\
+		";echo $(bootargs)"					\
+		";dhcp uImage_cpux9k2;bootm\0"				\
+	"nn=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \
+		"boot=nand "						\
+		";echo $(bootargs)"					\
+		";dhcp uImage_cpux9k2;bootm\0"				\
+	" "
+
+/*--------------------------------------------------------------------------*/
+
+#endif
+
+/* EOF */
diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h
index 7dd81e69cb..41ec1d52e3 100644
--- a/include/configs/kb9202.h
+++ b/include/configs/kb9202.h
@@ -29,6 +29,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 #define AT91C_MAIN_CLOCK	180000000	/* from 10 MHz crystal */
 #define AT91C_MASTER_CLOCK	60000000	/* peripheral clock (AT91C_MASTER_CLOCK / 3) */
@@ -115,7 +117,13 @@
 #define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
 #define CONFIG_SYS_MEMTEST_END			CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - (512*1024)
 
-#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_MULTI		1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#else
+#define CONFIG_DRIVER_ETHER		1
+#endif
 #define CONFIG_NET_RETRY_COUNT		20
 
 #define CONFIG_SYS_FLASH_BASE			0x10000000
diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h
new file mode 100644
index 0000000000..a928c2cfbb
--- /dev/null
+++ b/include/configs/km_arm.h
@@ -0,0 +1,191 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* for linking errors see http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
+
+#ifndef _CONFIG_KM_ARM_H
+#define _CONFIG_KM_ARM_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL
+#define CONFIG_ARM926EJS		/* Basic Architecture */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KIRKWOOD			/* SOC Family Name */
+#define CONFIG_KW88F6281		/* SOC Name */
+#define CONFIG_MACH_SUEN3		/* Machine type */
+
+/* include common defines/options for all Keymile boards */
+#include "keymile-common.h"
+#undef CONFIG_CMD_DTT
+#undef CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
+#undef  CONFIG_KIRKWOOD_PCIE_INIT	/* Disable PCIE Port0 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX	1	/* Console on UART0 */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_BOOTMAPSZ	(8 << 20)	/* Initial Memmap for Linux */
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG		/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 	/* enable memory tag */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+
+/*
+ * Without NOR FLASH we need this
+ */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+
+/*
+ * NAND Flash configuration
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_NAND_KIRKWOOD
+#define CONFIG_SYS_NAND_BASE		0xd8000000
+
+#define BOOTFLASH_START		0x0
+
+#define CONFIG_KM_CONSOLE_TTY	"ttyS0"
+
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET	/* some code reduction */
+#define CONFIG_ARCH_CPU_INIT		/* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT		/* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO		/* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS	4
+#define CONFIG_STACKSIZE	0x00100000	/* regular stack- 1M */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
+
+/*
+ * Ethernet Driver configuration
+ */
+#define CONFIG_NETCONSOLE	/* include NetConsole support   */
+#define CONFIG_NET_MULTI	/* specify more that one ports available */
+#define CONFIG_MII		/* expose smi ove miiphy interface */
+#define CONFIG_KIRKWOOD_EGIGA	/* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define CONFIG_KIRKWOOD_EGIGA_PORTS	{1,0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_RESET_PHY_R	/* use reset_phy() to init 88E1118 PHY */
+
+/*
+ * UBI related stuff
+ */
+#define CONFIG_SYS_USE_UBI
+
+/*
+ * I2C related stuff
+ */
+#undef	CONFIG_HARD_I2C		/* I2C with hardware support */
+#define	CONFIG_SOFT_I2C		/* I2C bit-banged	*/
+
+#if defined(CONFIG_HARD_I2C)
+#define	CONFIG_I2C_KIRKWOOD
+#define	CONFIG_I2C_KW_REG_BASE		KW_TWSI_BASE
+#define	CONFIG_SYS_I2C_SLAVE		0x0
+#define	CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#define	CONFIG_KIRKWOOD_GPIO		/* Enable GPIO Support */
+#if defined(CONFIG_SOFT_I2C)
+#ifndef __ASSEMBLY__
+#include <asm/arch-kirkwood/gpio.h>
+extern void __set_direction(unsigned pin, int high);
+void set_sda (int state);
+void set_scl (int state);
+int get_sda (void);
+int get_scl (void);
+#define SUEN3_SDA_PIN	8
+#define SUEN3_SCL_PIN	9
+#define SUEN3_ENV_WP	38
+
+#define I2C_ACTIVE	__set_direction(SUEN3_SDA_PIN, 0)
+#define I2C_TRISTATE	__set_direction(SUEN3_SDA_PIN, 1)
+#define I2C_READ	(kw_gpio_get_value(SUEN3_SDA_PIN) ? 1 : 0)
+#define I2C_SDA(bit)	kw_gpio_set_value(SUEN3_SDA_PIN, bit);
+#define I2C_SCL(bit)	kw_gpio_set_value(SUEN3_SCL_PIN, bit);
+#endif
+
+#define I2C_DELAY	udelay(3)	/* 1/4 I2C clock duration */
+#define I2C_SOFT_DECLARATIONS
+
+#define	CONFIG_SYS_I2C_SLAVE		0x0
+#define	CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+#if defined(CONFIG_SYS_NO_FLASH)
+#define CONFIG_KM_UBI_PARTITION_NAME   "ubi0"
+#undef	CONFIG_FLASH_CFI_MTD
+#undef	CONFIG_JFFS2_CMDLINE
+#endif
+
+#endif /* _CONFIG_KM_ARM_H */
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 0327b971b5..d27b75b647 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -295,7 +295,8 @@
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	0
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 #endif
 
 /*
diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h
index 5c066426cf..26c2bcb689 100644
--- a/include/configs/m501sk.h
+++ b/include/configs/m501sk.h
@@ -27,6 +27,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
 #define AT91C_MAIN_CLOCK	179712000
@@ -34,6 +36,7 @@
 #define AT91C_MASTER_CLOCK	59904000
 #define AT91_SLOW_CLOCK	32768 /* slow clock */
 
+#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
 #define CONFIG_AT91RM9200DK	1 /* on an AT91RM9200DK Board    */
 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
 #define CONFIG_CMDLINE_TAG	1 /* enable passing of ATAGs    */
@@ -166,7 +169,13 @@
 /* CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */
 #define CONFIG_SYS_MEMTEST_END	0x00100000
 
-#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_MULTI		1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#else
+#define CONFIG_DRIVER_ETHER		1
+#endif
 #define CONFIG_NET_RETRY_COUNT	20
 #define CONFIG_AT91C_USE_RMII
 
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index c3255fad64..d002b97510 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -31,6 +31,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* Common stuff */
 #define CONFIG_SYS_HZ			1000	/* decrementer freq */
 #define CONFIG_MEESC			1	/* Board is esd MEESC */
@@ -57,6 +59,7 @@
  */
 
 /* Console output */
+#define CONFIG_AT91_GPIO			1
 #define CONFIG_ATMEL_USART			1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
index 0c2ee6057e..3138b493cd 100644
--- a/include/configs/mp2usb.h
+++ b/include/configs/mp2usb.h
@@ -28,6 +28,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 #define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 45) */
 #define AT91C_MASTER_CLOCK	(AT91C_MAIN_CLOCK/3)	/* peripheral clock */
@@ -181,7 +183,13 @@
 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
 #define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
 
-#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_MULTI		1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#else
+#define CONFIG_DRIVER_ETHER		1
+#endif
 #define CONFIG_NET_RETRY_COUNT		20
 #undef CONFIG_AT91C_USE_RMII
 
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
new file mode 100644
index 0000000000..903fe6da7e
--- /dev/null
+++ b/include/configs/mx51evk.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX51EVK Board
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+ /* High Level Configuration Options */
+
+#define CONFIG_MX51	/* in a mx51 */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_MX51_HCLK_FREQ		24000000	/* RedBoot says 26MHz */
+#define CONFIG_MX51_CLK32		32768
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_L2_OFF
+
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX51_UART1
+
+/*
+ * MMC Configs
+ * */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	2
+
+#define CONFIG_MMC
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Eth Configs
+ */
+#define CONFIG_HAS_ETH1
+#define CONFIG_NET_MULTI
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_PRIME	"FEC0"
+
+#define CONFIG_LOADADDR		0x90800000	/* loadaddr env var */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+		"netdev=eth0\0"						\
+		"uboot_addr=0xa0000000\0"				\
+		"uboot=u-boot.bin\0"			\
+		"loadaddr=0x90800000\0"			\
+		"bootargs_base=setenv bootargs console=tty "\
+			"console=ttymxc0,${baudrate}\0"\
+		"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+			"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+		"bootcmd=run bootcmd_net\0"				\
+		"bootcmd_net=run bootargs_base bootargs_nfs; "		\
+			"tftpboot ${loadaddr} ${kernel}; bootm\0"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"MX51EVK U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0x90000000
+#define CONFIG_SYS_MEMTEST_END         0x10000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_CMDLINE_EDITING
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SECT_SIZE    (128 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_IS_NOWHERE
+
+#endif
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index 884dc0937d..c63c84650f 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -27,17 +27,13 @@
 
 #include <configs/omap1510.h>
 
-/*
- * High Level Configuration Options
- * (easy to change)
- */
 #define CONFIG_ARM925T	1		/* This is an arm925t CPU */
 #define CONFIG_OMAP	1		/* in a TI OMAP core */
 #define CONFIG_OMAP1510 1		/* which is in a 5910 */
 
 /* Input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ	150000000	/* 150MHz input clock */
-#define CONFIG_XTAL_FREQ	12000000
+#define CONFIG_SYS_CLK_FREQ		150000000	/* 150MHz */
+#define CONFIG_XTAL_FREQ		12000000	/*  12MHz */
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
@@ -54,10 +50,10 @@
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	(64 * 1024 * 1024)
-#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1 */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x10000000
+#define PHYS_SDRAM_1_SIZE		(64 * 1024 * 1024)
+#define PHYS_FLASH_1			0x00000000
 
 #define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
@@ -66,23 +62,23 @@
  * Environment settings
  */
 #define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR		0x4000
-#define CONFIG_ENV_SIZE		(8 * 1024)
-#define CONFIG_ENV_SECT_SIZE	(8 * 1024)
-#define CONFIG_ENV_ADDR_REDUND	0x6000
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+#define CONFIG_ENV_ADDR			0x4000
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(8 * 1024)
+#define CONFIG_ENV_ADDR_REDUND		0x6000
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
 #define CONFIG_ENV_OVERWRITE
 
 /*
  * Size of malloc() pool
  */
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 
 /*
  * The stack size is set up in start.S using the settings below
  */
-#define CONFIG_STACKSIZE	(1 * 1024 * 1024)	/* regular stack */
+#define CONFIG_STACKSIZE		(1 * 1024 * 1024)
 
 /*
  * Hardware drivers
@@ -90,8 +86,8 @@
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		(CONFIG_XTAL_FREQ)	/* can be 12M/32Khz or 48Mhz  */
-#define CONFIG_SYS_NS16550_COM1		OMAP1510_UART1_BASE	/* uart1 */
+#define CONFIG_SYS_NS16550_CLK		(CONFIG_XTAL_FREQ)
+#define CONFIG_SYS_NS16550_COM1		OMAP1510_UART1_BASE
 
 #define CONFIG_NET_MULTI
 #define CONFIG_SMC91111
@@ -128,19 +124,18 @@
 /*#define CONFIG_SKIP_LOWLEVEL_INIT */
 
 /*
- * partitions (mtdparts command line support)
+ * Partitions (mtdparts command line support)
  */
 #define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_MTD_DEVICE
 #define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=omapflash.0,nand0=omapnand.0"
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=gen_nand.0"
 #define MTDPARTS_DEFAULT	"mtdparts=" \
-	"omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \
-	"omapnand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)"
-
+	"physmap-flash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \
+	"gen_nand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)"
 
 /*
- * Command line configuration.
+ * Command line configuration
  */
 #define CONFIG_CMD_BDI
 #define CONFIG_CMD_BOOTD
@@ -156,7 +151,6 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_RUN
 
-
 /*
  * BOOTP options
  */
@@ -173,26 +167,27 @@
 #define CONFIG_SYS_AUTOLOAD		"n"		/* No autoload */
 #define CONFIG_BOOTCOMMAND	"run fboot"
 #define CONFIG_PREBOOT		"run setup"
-#define	CONFIG_EXTRA_ENV_SETTINGS						\
-	"autostart=yes\0"							\
-	"ospart=0\0"								\
-	"setup=setenv bootargs console=ttyS0,$baudrate "			\
-		"$mtdparts\0"							\
-	"setpart="								\
-	"if test -n $swapos; then "						\
-		"setenv swapos; saveenv; "					\
-	"else "									\
-		"if test $ospart -eq 0; then setenv ospart 1;"			\
-			"else setenv ospart 0;		fi; "			\
-	"fi\0"									\
-	"nfsargs=setenv bootargs $bootargs "					\
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off "	\
-		"nfsroot=$rootpath root=/dev/nfs\0"				\
-	"flashargs=run setpart;setenv bootargs $bootargs "			\
-		"root=mtd:rootfs$ospart ro "					\
-		"rootfstype=jffs2\0"						\
-	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0"		\
-	"fboot=run flashargs;nboot kernel$ospart\0"				\
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"autostart=yes\0"						\
+	"ospart=0\0"							\
+	"setup=setenv bootargs console=ttyS0,$baudrate $mtdparts\0"	\
+	"setpart="							\
+	"if test -n $swapos; then "					\
+		"setenv swapos; saveenv; "				\
+		"if test $ospart -eq 0; then "				\
+			"setenv ospart 1; "				\
+		"else "							\
+			"setenv ospart 0; "				\
+		"fi; "							\
+	"fi\0"								\
+	"nfsargs=setenv bootargs $bootargs "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
+		"nfsroot=$rootpath root=/dev/nfs\0"			\
+	"flashargs=run setpart;setenv bootargs $bootargs "		\
+		"root=mtd:rootfs$ospart ro "				\
+		"rootfstype=jffs2\0"					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0"	\
+	"fboot=run flashargs;nboot kernel$ospart\0"			\
 	"nboot=bootp;run nfsargs;tftp\0"
 
 #if 0	/* feel free to disable for development */
@@ -205,12 +200,13 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"# "		/* Monitor Command Prompt	*/
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"# "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+	 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
@@ -218,9 +214,9 @@
 
 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
 #define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
-				(CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE)
+	(CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE)
 
-#define CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1 + 0x400000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		(PHYS_SDRAM_1 + 0x400000)
 
 /* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
  * This time is further subdivided by a local divisor.
@@ -229,9 +225,9 @@
 #define CONFIG_SYS_PTV			7
 #define CONFIG_SYS_HZ			1000
 
-#define OMAP5910_DPLL_DIV	1
-#define OMAP5910_DPLL_MUL	((CONFIG_SYS_CLK_FREQ * \
-				 (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
+#define OMAP5910_DPLL_DIV		1
+#define OMAP5910_DPLL_MUL		\
+	((CONFIG_SYS_CLK_FREQ * (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
 
 #define OMAP5910_ARM_PER_DIV	2	/* CKL/4 */
 #define OMAP5910_LCD_DIV	2	/* CKL/4 */
@@ -241,7 +237,7 @@
 #define OMAP5910_DSP_MMU_DIV	1	/* CKL/2 */
 #define OMAP5910_ARM_TIM_SEL	1	/* CKL used for MPU timers */
 
-#define OMAP5910_ARM_EN_CLK	0x03d6	/* 0000 0011 1101 0110b  Clock Enable */
+#define OMAP5910_ARM_EN_CLK	0x03d6	/* 0000 0011 1101 0110b */
 #define OMAP5910_ARM_CKCTL	((OMAP5910_ARM_PER_DIV)  |	\
 				 (OMAP5910_LCD_DIV << 2) |	\
 				 (OMAP5910_ARM_DIV << 4) |	\
diff --git a/include/configs/otc570.h b/include/configs/otc570.h
index bedaf13431..8e27ebae9e 100644
--- a/include/configs/otc570.h
+++ b/include/configs/otc570.h
@@ -55,6 +55,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO		1
 
 /* Console output */
 #define CONFIG_ATMEL_USART		1
@@ -96,24 +97,22 @@
 #ifdef CONFIG_SOFT_I2C
 #define CONFIG_I2C_CMD_TREE		1
 #define CONFIG_I2C_MULTI_BUS		1
-/* Enable peripheral clock and configure data and clock pins for pio */
+/* Configure data and clock pins for pio */
 #define I2C_INIT { \
-	at91_sys_write(AT91_PMC_PCER,	1 << AT91SAM9263_ID_PIOB |	\
-					1 << AT91SAM9263_ID_PIOCDE);	\
-	at91_set_gpio_output(AT91_PIN_PB4, 0);				\
-	at91_set_gpio_output(AT91_PIN_PB5, 0);				\
+	at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \
+	at91_set_pio_output(AT91_PIO_PORTB, 5, 0); \
 }
 /* Configure data pin as output */
-#define I2C_ACTIVE			at91_set_gpio_output(AT91_PIN_PB4, 0)
+#define I2C_ACTIVE		at91_set_pio_output(AT91_PIO_PORTB, 4, 0)
 /* Configure data pin as input */
-#define I2C_TRISTATE			at91_set_gpio_input(AT91_PIN_PB4, 0)
+#define I2C_TRISTATE		at91_set_pio_input(AT91_PIO_PORTB, 4, 0)
 /* Read data pin */
-#define I2C_READ			at91_get_gpio_value(AT91_PIN_PB4)
+#define I2C_READ		at91_get_pio_value(AT91_PIO_PORTB, 4)
 /* Set data pin */
-#define I2C_SDA(bit)			at91_set_gpio_value(AT91_PIN_PB4, bit)
+#define I2C_SDA(bit)		at91_set_pio_value(AT91_PIO_PORTB, 4, bit)
 /* Set clock pin */
-#define I2C_SCL(bit)			at91_set_gpio_value(AT91_PIN_PB5, bit)
-#define I2C_DELAY			udelay(2) /* 1/4 I2C clock duration */
+#define I2C_SCL(bit)		at91_set_pio_value(AT91_PIO_PORTB, 5, bit)
+#define I2C_DELAY		udelay(2) /* 1/4 I2C clock duration */
 #endif /* CONFIG_SOFT_I2C */
 
 #define CONFIG_BOOTDELAY		3
@@ -173,8 +172,8 @@
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTD, 15
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTA, 22
 #define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
 #endif
 
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 399d15f9fe..47bb8c09aa 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -28,15 +28,17 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
-#define AT91_CPU_NAME		"AT91SAM9261"
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9261"
 
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define MASTER_PLL_DIV		15
 #define MASTER_PLL_MUL		162
 #define MAIN_PLL_DIV		2
-#define AT91_MAIN_CLOCK		18432000
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
 
 #define CONFIG_SYS_HZ		1000
 
@@ -157,6 +159,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 0af1280370..807dba8f42 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -28,6 +28,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
@@ -35,7 +37,7 @@
 #define MASTER_PLL_DIV		6
 #define MASTER_PLL_MUL		65
 #define MAIN_PLL_DIV		2	/* 2 or 4 */
-#define AT91_MAIN_CLOCK	18432000
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
 
 #define CONFIG_SYS_HZ		1000
 
@@ -171,6 +173,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h
index f4b34775a6..b9f27cc95b 100644
--- a/include/configs/sbc35_a9g20.h
+++ b/include/configs/sbc35_a9g20.h
@@ -26,6 +26,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 #if defined(CONFIG_SBC35_A9G20_NANDFLASH) || defined(CONFIG_SBC35_A9G20_EEPROM)
 #define CONFIG_SBC35_A9G20
 #endif
@@ -39,7 +41,7 @@
 #endif
 
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		12000000	/* 12.000 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12.000 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
@@ -57,6 +59,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART
 #define CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 7bef1195d3..4ea65ce164 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -631,21 +631,13 @@
 
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR		00:a0:1e:a0:13:8d
 #define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		00:a0:1e:a0:13:8e
 #endif
 
-#define CONFIG_IPADDR		192.168.1.234
-
 #define CONFIG_HOSTNAME		SBC8349
 #define CONFIG_ROOTPATH		/tftpboot/rootfs
 #define CONFIG_BOOTFILE		uImage
 
-#define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_GATEWAYIP	192.168.1.1
-#define CONFIG_NETMASK		255.255.255.0
-
 #define CONFIG_LOADADDR		800000	/* default location for tftp and bootm */
 
 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
diff --git a/include/configs/suen3.h b/include/configs/suen3.h
new file mode 100644
index 0000000000..b2730a3cec
--- /dev/null
+++ b/include/configs/suen3.h
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * for linking errors see
+ * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
+ */
+
+#ifndef _CONFIG_SUEN3_H
+#define _CONFIG_SUEN3_H
+
+/* include common defines/options for all arm based Keymile boards */
+#include "km_arm.h"
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nKeymile SUEN3"
+
+#define CONFIG_HOSTNAME			suen3
+
+/*
+ *  Environment variables configurations
+ */
+#define CONFIG_ENV_IS_IN_EEPROM		/* use EEPROM for environment vars */
+#define CONFIG_SYS_DEF_EEPROM_ADDR	0x50
+#define CONFIG_ENV_EEPROM_IS_ON_I2C	1
+#define CONFIG_SYS_EEPROM_WREN		1
+#define CONFIG_ENV_OFFSET		0x0 /* no bracets! */
+#undef	CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE			(0x2000 - CONFIG_ENV_OFFSET)
+#define CONFIG_I2C_ENV_EEPROM_BUS	"pca9547:70:d\0"
+
+/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND	0x2000 /* no bracets! */
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+
+#define CONFIG_CMD_SF
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_HARD_SPI
+#define CONFIG_KIRKWOOD_SPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		50000000	/* 50Mhz */
+
+#define FLASH_GPIO_PIN			0x00010000
+
+#define MTDIDS_DEFAULT		"nand0=orion_nand"
+/* test-only: partitioning needs some tuning, this is just for tests */
+#define MTDPARTS_DEFAULT	"mtdparts="				\
+	"orion_nand:"							\
+		"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
+
+#define	CONFIG_KM_DEF_ENV_UPDATE					\
+	"update="							\
+		"spi on;sf probe 0;sf erase 0 50000;"			\
+		"sf write ${u-boot_addr_r} 0 ${filesize};"		\
+		"spi off\0"
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_DEF_ENV						\
+	"memsize=0x8000000\0"						\
+	"newenv=setenv addr 0x100000 && "				\
+		"i2c dev 1; mw.b ${addr} 0 4 && "			\
+		"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)	\
+		" ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && "		\
+		"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)	\
+		" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0"	\
+	"rootpath=/opt/eldk/arm\0"					\
+	"EEprom_ivm=pca9544a:70:9\0"					\
+	""
+
+#endif /* _CONFIG_SUEN3_H */
diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h
index 4ad081b0ba..5af2af3d1c 100644
--- a/include/configs/tny_a9260.h
+++ b/include/configs/tny_a9260.h
@@ -30,6 +30,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 #if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9260_EEPROM)
 #define CONFIG_TNY_A9260
 #elif defined(CONFIG_TNY_A9G20_NANDFLASH) || defined(CONFIG_TNY_A9G20_EEPROM)
@@ -49,7 +51,7 @@
 #endif
 
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		12000000	/* 12 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core */
@@ -66,6 +68,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/tx25.h b/include/configs/tx25.h
new file mode 100644
index 0000000000..c8188ca525
--- /dev/null
+++ b/include/configs/tx25.h
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+/*
+ * KARO TX25 board - SoC Configuration
+ */
+#define CONFIG_ARM926EJS			/* arm926ejs CPU core */
+#define CONFIG_MX25
+#define CONFIG_TX25
+#define CONFIG_MX25_CLK32		32000	/* OSC32K frequency */
+#define CONFIG_SYS_HZ			1000
+
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* 256 kB for U-Boot */
+
+/* NAND BOOT is the only boot method */
+#define CONFIG_NAND_U_BOOT
+
+#ifdef CONFIG_NAND_SPL
+/* Start copying real U-boot from the second page */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x800
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x30000
+/* Load U-Boot to this address */
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x81f00000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_SPARE_SIZE	64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_SIZE		(128 * 1024 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#else
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#endif
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Memory Info
+ */
+/* malloc() len */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
+/* reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+/*
+ * Board has 2 32MB banks of DRAM but there is a bug when using
+ * both so only the first is configured
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+
+#define PHYS_SDRAM_1		0x80000000
+#define PHYS_SDRAM_1_SIZE	0x02000000
+#if (CONFIG_NR_DRAM_BANKS == 2)
+#define PHYS_SDRAM_2		0x90000000
+#define PHYS_SDRAM_2_SIZE	0x02000000
+#endif
+/* 8MB DRAM test */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1+0x0800000)
+#define CONFIG_STACKSIZE	(256 * 1024)	/* regular stack */
+
+/*
+ * Serial Info
+ */
+#define CONFIG_MXC_UART		1
+#define CONFIG_SYS_MX25_UART1	1
+#define CONFIG_CONS_INDEX	1	/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200	/* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Flash & Environment
+ */
+/* No NOR flash present */
+#define CONFIG_SYS_NO_FLASH	1
+#define	CONFIG_ENV_IS_IN_NAND
+#define	CONFIG_ENV_OFFSET	CONFIG_SYS_MONITOR_LEN
+#define CONFIG_ENV_SIZE		(128 * 1024)	/* 128 kB NAND block size */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+
+/* NAND */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE	(0xBB000000)
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(0xBB000000)
+#define CONFIG_JFFS2_NAND
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+/* U-Boot general configuration */
+#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size  */
+/* Print buffer sz */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+		sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	32	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+/* U-Boot commands */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_NAND
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0x1f
+#define CONFIG_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_MULTI
+#define BOARD_LATE_INIT
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_LOADADDR		0x81000000	/* loadaddr env var */
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttymxc0,${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"u-boot=tx25/u-boot.bin\0"					\
+	"kernel_addr_r=" xstr(CONFIG_LOADADDR) "\0"			\
+	"hostname=tx25\0"						\
+	"bootfile=tx25/uImage\0"					\
+	"rootpath=/opt/eldk/arm\0"					\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm\0"						\
+	"bootcmd=run net_nfs\0"						\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=nand erase 0 40000;nand write ${loadaddr} 0 40000\0"	\
+	"upd=run load update\0"						\
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index dbc15b297f..7603300ae1 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -118,7 +118,7 @@
 #define CONFIG_SYS_FLASH_BASE		0xffc00000	/* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE		4		/* flash size in MB */
 #define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | \
-					 (2 << BR_PS_SHIFT) |	/*  32bit */ \
+					 (2 << BR_PS_SHIFT) |	/*  16bit */ \
 					 BR_V)			/* valid */
 
 #define CONFIG_SYS_OR0_PRELIM		0xffc06ff7	/*   4 MB flash size */
@@ -128,7 +128,7 @@
 #define CONFIG_SYS_FLASH_BASE		0xf8000000	/* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE		128		/* flash size in MB */
 #define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | \
-					 (2 << BR_PS_SHIFT) |	/*  32bit */ \
+					 (2 << BR_PS_SHIFT) |	/*  16bit */ \
 					 BR_V)			/* valid */
 
 #define CONFIG_SYS_OR0_PRELIM		0xf8006ff7	/* 128 MB flash size */
diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h
index 0dde65d12a..d46717cd25 100644
--- a/include/configs/voiceblue.h
+++ b/include/configs/voiceblue.h
@@ -31,8 +31,8 @@
 #define CONFIG_OMAP1510 1		/* which is in a 5910 */
 
 /* Input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ	150000000	/* 150MHz input clock */
-#define CONFIG_XTAL_FREQ	12000000
+#define CONFIG_SYS_CLK_FREQ		150000000	/* 150MHz */
+#define CONFIG_XTAL_FREQ		12000000	/*  12MHz */
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
@@ -48,55 +48,53 @@
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	(64 * 1024 * 1024)
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x10000000
+#define PHYS_SDRAM_1_SIZE		(64 * 1024 * 1024)
+#define PHYS_FLASH_1			0x0000000
 
-#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1 */
-
-#define CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1 + 0x400000	/* default load address */
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI			/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER		/* Use the common driver */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
-
-/* FIXME: Does not work on AMD flash */
-/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */	/* use buffered writes (20x faster) */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max # of sectors on one chip */
-
-#define CONFIG_SYS_MONITOR_BASE	PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
 
 /*
  * Environment settings
  */
 #define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE		(8 * 1024)
-#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
 
 #define CONFIG_ENV_OVERWRITE
 
 /*
  * Size of malloc() pool and stack
  */
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-#define CONFIG_STACKSIZE	(1 * 1024 * 1024)
-#define PHYS_SDRAM_1_RESERVED	(CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE)
+#define CONFIG_STACKSIZE		(1 * 1024 * 1024)
 
 /*
  * Hardware drivers
  */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(CONFIG_XTAL_FREQ)
+#define CONFIG_SYS_NS16550_COM1		OMAP1510_UART1_BASE
+
 #define CONFIG_NET_MULTI
 #define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE	0x08000300
+#define CONFIG_SMC91111_BASE		0x08000300
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 #define CONFIG_HARD_I2C
 #define CONFIG_SYS_I2C_SPEED		100000
@@ -104,24 +102,16 @@
 #define CONFIG_DRIVER_OMAP1510_I2C
 
 #define CONFIG_RTC_DS1307
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
 
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		(CONFIG_XTAL_FREQ)	/* can be 12M/32Khz or 48Mhz  */
-#define CONFIG_SYS_NS16550_COM1	OMAP1510_UART1_BASE	/* uart1 */
 
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		115200
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 
 /*
- * Command line configuration.
+ * Command line configuration
  */
 #include <config_cmd_default.h>
 
@@ -138,7 +128,6 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_RUN
 
-
 /*
  * BOOTP options
  */
@@ -147,36 +136,39 @@
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_BOOTPATH
 
-
 #define CONFIG_LOOPW
 
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow to break in always */
-#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs*/
-#define CONFIG_SYS_AUTOLOAD		"n"		/* No autoload */
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs*/
+#define CONFIG_SYS_AUTOLOAD		"n"
 #define CONFIG_BOOTCOMMAND	"run nboot"
 #define CONFIG_PREBOOT		"run setup"
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-	"silent=1\0"						\
-	"ospart=0\0"						\
-	"bootfile=/boot/uImage\0"				\
-	"setpart="						\
-	"if test -n $swapos; then "				\
-		"setenv swapos; saveenv; "			\
-		"if test $ospart -eq 0; then setenv ospart 1; else setenv ospart 0; fi; "\
-	"fi\0"							\
-	"setup=setenv bootargs console=ttyS0,$baudrate "	\
-		"mtdparts=$mtdparts\0"				\
-	"nfsargs=setenv bootargs $bootargs "			\
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"silent=1\0"							\
+	"ospart=0\0"							\
+	"bootfile=/boot/uImage\0"					\
+	"setpart="							\
+	"if test -n $swapos; then "					\
+		"setenv swapos; saveenv; "				\
+		"if test $ospart -eq 0; then "				\
+			"setenv ospart 1; "				\
+		"else "							\
+			"setenv ospart 0; "				\
+		"fi; "							\
+	"fi\0"								\
+	"setup=setenv bootargs console=ttyS0,$baudrate "		\
+		"mtdparts=$mtdparts\0"					\
+	"nfsargs=setenv bootargs $bootargs "				\
 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
-		"nfsroot=$rootpath root=/dev/nfs\0"		\
-	"flashargs=run setpart; setenv bootargs $bootargs "	\
-		"root=mtd:data$ospart ro "			\
-		"rootfstype=jffs2\0"				\
-	"initrdargs=setenv bootargs $bootargs "			\
+		"nfsroot=$rootpath root=/dev/nfs\0"			\
+	"flashargs=run setpart; setenv bootargs $bootargs "		\
+		"root=mtd:data$ospart ro "				\
+		"rootfstype=jffs2\0"					\
+	"initrdargs=setenv bootargs $bootargs "				\
 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
-	"fboot=run flashargs; chpart data$ospart; fsload; bootm\0" \
-	"mboot=bootp; run initrdargs; tftp; bootm\0"		\
+	"fboot=run flashargs; chpart data$ospart; fsload; bootm\0"	\
+	"mboot=bootp; run initrdargs; tftp; bootm\0"			\
 	"nboot=bootp; run nfsargs; tftp; bootm\0"
 
 #define CONFIG_SILENT_CONSOLE		1	/* enable silent startup */
@@ -188,14 +180,14 @@
 #endif
 
 /*
- * JFFS2 partitions (mtdparts command line support)
+ * Partitions (mtdparts command line support)
  */
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
 #define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=omapflash.0"
-#define MTDPARTS_DEFAULT	"mtdparts=omapflash.0:256k(u-boot),64k(env),64k(r_env),16192k(data0),-(data1)"
-
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:" \
+	"256k(u-boot),64k(env),64k(r_env),16192k(data0),-(data1)"
 
 /*
  * Miscellaneous configurable options
@@ -203,26 +195,30 @@
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"# "		/* Monitor Command Prompt	*/
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - PHYS_SDRAM_1_RESERVED
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"# "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1)
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
+	(CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE))
+#define CONFIG_SYS_LOAD_ADDR		(PHYS_SDRAM_1 + 0x400000)
 
-/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
+/*
+ * The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
  * This time is further subdivided by a local divisor.
  */
-#define CONFIG_SYS_TIMERBASE	OMAP1510_TIMER1_BASE
-#define CONFIG_SYS_PTV		7	/* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_TIMERBASE		OMAP1510_TIMER1_BASE
+#define CONFIG_SYS_PTV			7	/* 2^(PTV+1), divide by 256 */
+#define CONFIG_SYS_HZ			1000
 
-#define OMAP5910_DPLL_DIV	1
-#define OMAP5910_DPLL_MUL	((CONFIG_SYS_CLK_FREQ * \
-				 (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
+#define OMAP5910_DPLL_DIV		1
+#define OMAP5910_DPLL_MUL		\
+	((CONFIG_SYS_CLK_FREQ * (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
 
 #define OMAP5910_ARM_PER_DIV	2	/* CKL/4 */
 #define OMAP5910_LCD_DIV	2	/* CKL/4 */
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index eac6a2bd48..01b7dec188 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -27,12 +27,15 @@
 #define	__FSL_ESDHC_H__
 
 #include <asm/errno.h>
+#include <asm/byteorder.h>
 
 /* FSL eSDHC-specific constants */
 #define SYSCTL			0x0002e02c
 #define SYSCTL_INITA		0x08000000
 #define SYSCTL_TIMEOUT_MASK	0x000f0000
 #define SYSCTL_CLOCK_MASK	0x0000fff0
+#define SYSCTL_RSTA		0x01000000
+#define SYSCTL_CKEN		0x00000008
 #define SYSCTL_PEREN		0x00000004
 #define SYSCTL_HCKEN		0x00000002
 #define SYSCTL_IPGEN		0x00000001
@@ -142,8 +145,32 @@
 #define ESDHC_HOSTCAPBLT_DMAS	0x00400000
 #define ESDHC_HOSTCAPBLT_HSS	0x00200000
 
+struct fsl_esdhc_cfg {
+	u32	esdhc_base;
+	u32	no_snoop;
+	u32	clk_enable;
+};
+
+/* Select the correct accessors depending on endianess */
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define esdhc_read32		in_le32
+#define esdhc_write32		out_le32
+#define esdhc_clrsetbits32	clrsetbits_le32
+#define esdhc_clrbits32		clrbits_le32
+#define esdhc_setbits32		setbits_le32
+#elif __BYTE_ORDER == __BIG_ENDIAN
+#define esdhc_read32		in_be32
+#define esdhc_write32		out_be32
+#define esdhc_clrsetbits32	clrsetbits_be32
+#define esdhc_clrbits32		clrbits_be32
+#define esdhc_setbits32		setbits_be32
+#else
+#error "Endianess is not defined: please fix to continue"
+#endif
+
 #ifdef CONFIG_FSL_ESDHC
 int fsl_esdhc_mmc_init(bd_t *bis);
+int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
 void fdt_fixup_esdhc(void *blob, bd_t *bd);
 #else
 static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h
index da5be379d1..279aaa55de 100644
--- a/include/fsl_nfc.h
+++ b/include/fsl_nfc.h
@@ -1,5 +1,4 @@
 /*
- *
  * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -25,21 +24,57 @@
 #define __FSL_NFC_H
 
 /*
+ * TODO: Use same register defs for nand_spl mxc nand driver
+ * and mtd mxc nand driver.
+ *
  * Register map and bit definitions for the Freescale NAND Flash
- * Controller present in i.MX31 and other devices.
+ * Controller present in various i.MX devices.
+ *
+ * MX31 and MX27 have version 1 which has
+ * 	4 512 byte main buffers and
+ * 	4 16 byte spare buffers
+ * 	to support up to 2K byte pagesize nand.
+ * 	Reading or writing a 2K page requires 4 FDI/FDO cycles.
+ *
+ * MX25 has version 1.1 which has
+ * 	8 512 byte main buffers and
+ * 	8 64 byte spare buffers
+ * 	to support up to 4K byte pagesize nand.
+ * 	Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
+ *      Also some of registers are moved and/or changed meaning as seen below.
  */
+#if defined(CONFIG_MX31) || defined(CONFIG_MX27)
+#define MXC_NFC_V1
+#elif defined(CONFIG_MX25)
+#define MXC_NFC_V1_1
+#else
+#warning "MXC NFC version not defined"
+#endif
+
+#if defined(MXC_NFC_V1)
+#define NAND_MXC_NR_BUFS		4
+#define NAND_MXC_SPARE_BUF_SIZE		16
+#define NAND_MXC_REG_OFFSET		0xe00
+#define NAND_MXC_2K_MULTI_CYCLE		1
+#elif defined(MXC_NFC_V1_1)
+#define NAND_MXC_NR_BUFS		8
+#define NAND_MXC_SPARE_BUF_SIZE		64
+#define NAND_MXC_REG_OFFSET		0x1e00
+#else
+#error "define CONFIG_NAND_MXC_VXXX to use the mxc spl_nand driver"
+#endif
 
 struct fsl_nfc_regs {
-	u32 main_area0[128]; /* @0x000 */
-	u32 main_area1[128];
-	u32 main_area2[128];
-	u32 main_area3[128];
-	u32 spare_area0[4];
-	u32 spare_area1[4];
-	u32 spare_area2[4];
-	u32 spare_area3[4];
-	u32 reserved1[64 - 16 + 64 * 5];
-	u16 bufsiz; /* @ 0xe00 */
+	u32 main_area[NAND_MXC_NR_BUFS][512/4];
+	u32 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE/4];
+	/*
+	 * reserved size is offset of nfc registers
+	 * minus total main and spare sizes
+	 */
+	u8 reserved1[NAND_MXC_REG_OFFSET
+		- NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
+#if defined(MXC_NFC_V1)
+	u16 bufsiz;
 	u16 reserved2;
 	u16 buffer_address;
 	u16 flash_add;
@@ -54,6 +89,30 @@ struct fsl_nfc_regs {
 	u16 nand_flash_wr_pr_st;
 	u16 nand_flash_config1;
 	u16 nand_flash_config2;
+#elif defined(MXC_NFC_V1_1)
+	u16 reserved2[2];
+	u16 buffer_address;
+	u16 flash_add;
+	u16 flash_cmd;
+	u16 configuration;
+	u16 ecc_status_result;
+	u16 ecc_status_result2;
+	u16 spare_area_size;
+	u16 nf_wr_prot;
+	u16 reserved3[2];
+	u16 nand_flash_wr_pr_st;
+	u16 nand_flash_config1;
+	u16 nand_flash_config2;
+	u16 reserved4;
+	u16 unlock_start_blk_add0;
+	u16 unlock_end_blk_add0;
+	u16 unlock_start_blk_add1;
+	u16 unlock_end_blk_add1;
+	u16 unlock_start_blk_add2;
+	u16 unlock_end_blk_add2;
+	u16 unlock_start_blk_add3;
+	u16 unlock_end_blk_add3;
+#endif
 };
 
 /*
@@ -98,6 +157,9 @@ struct fsl_nfc_regs {
  */
 #define NFC_INT		0x8000
 
+#ifdef MXC_NFC_V1_1
+#define NFC_4_8N_ECC	(1 << 0)
+#endif
 #define NFC_SP_EN	(1 << 2)
 #define NFC_ECC_EN	(1 << 3)
 #define NFC_INT_MSK	(1 << 4)
diff --git a/include/i2c.h b/include/i2c.h
index b75476980b..31088b675a 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -74,6 +74,11 @@
 #  define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
 # elif defined(CONFIG_8xx)
 #  define I2C_SOFT_DECLARATIONS	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+# elif (defined(CONFIG_AT91RM9200) || \
+	defined(CONFIG_AT91SAM9260) ||  defined(CONFIG_AT91SAM9261) || \
+	defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY)
+#  define I2C_SOFT_DECLARATIONS	at91_pio_t *pio	= (at91_pio_t *) AT91_PIO_BASE;
 # else
 #  define I2C_SOFT_DECLARATIONS
 # endif
diff --git a/include/mmc.h b/include/mmc.h
index 2dc69abb68..8973bc7658 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -272,6 +272,7 @@ int mmc_init(struct mmc *mmc);
 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
 struct mmc *find_mmc_device(int dev_num);
 void print_mmc_devices(char separator);
+int board_mmc_getcd(u8 *cd, struct mmc *mmc);
 
 #ifndef CONFIG_GENERIC_MMC
 int mmc_legacy_init(int verbose);
diff --git a/include/netdev.h b/include/netdev.h
index 1e0484fa41..1dd80f0593 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -42,6 +42,7 @@ int cpu_eth_init(bd_t *bis);
 
 /* Driver initialization prototypes */
 int au1x00_enet_initialize(bd_t*);
+int at91emac_register(bd_t *bis, unsigned long iobase);
 int bfin_EMAC_initialize(bd_t *bis);
 int cs8900_initialize(u8 dev_num, int base_addr);
 int dc21x4x_initialize(bd_t *bis);
diff --git a/include/nomadik.h b/include/nomadik.h
index d9405fd287..ea65b2d828 100644
--- a/include/nomadik.h
+++ b/include/nomadik.h
@@ -4,6 +4,7 @@
 #define __NOMADIK_H__
 
 /* Base addresses of our peripherals */
+#define NOMADIK_CLCDC_BASE	0x10120000	/* CLCD Controller */
 #define NOMADIK_SRC_BASE	0x101E0000	/* System and Reset Cnt */
 #define NOMADIK_PMU_BASE	0x101E9000	/* Power Management Unit */
 #define NOMADIK_MPMC_BASE	0x10110000	/* SDRAM Controller */
diff --git a/include/tsec.h b/include/tsec.h
index f56723a153..1e903659eb 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -153,6 +153,19 @@
 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK	0x0700
 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT	8
 
+#define MIIM_BCM54XX_SHD	0x1c	/* 0x1c shadow registers */
+#define MIIM_BCM54XX_SHD_WRITE	0x8000
+#define MIIM_BCM54XX_SHD_VAL(x)	((x & 0x1f) << 10)
+#define MIIM_BCM54XX_SHD_DATA(x)	((x & 0x3ff) << 0)
+#define MIIM_BCM54XX_SHD_WR_ENCODE(val, data)	\
+	(MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \
+	 MIIM_BCM54XX_SHD_DATA(data))
+
+#define MIIM_BCM54XX_EXP_DATA	0x15	/* Expansion register data */
+#define MIIM_BCM54XX_EXP_SEL	0x17	/* Expansion register select */
+#define MIIM_BCM54XX_EXP_SEL_SSD	0x0e00	/* Secondary SerDes select */
+#define MIIM_BCM54XX_EXP_SEL_ER	0x0f00	/* Expansion register select */
+
 /* Cicada Auxiliary Control/Status Register */
 #define MIIM_CIS8201_AUX_CONSTAT	0x1c
 #define MIIM_CIS8201_AUXCONSTAT_INIT	0x0004
@@ -571,9 +584,9 @@ typedef struct tsec
 
 /* This flag currently only has
  * meaning if we're using the eTSEC */
-#define TSEC_REDUCED	(1 << 1)
-
-#define TSEC_SGMII	(1 << 2)
+#define TSEC_REDUCED	(1 << 1)	/* MAC-PHY interface uses RGMII */
+#define TSEC_SGMII	(1 << 2)	/* MAC-PHY interface uses SGMII */
+#define TSEC_FIBER	(1 << 3)	/* PHY uses fiber, eg 1000 Base-X */
 
 struct tsec_private {
 	volatile tsec_t *regs;
@@ -644,7 +657,6 @@ struct tsec_info_struct {
 	u32 flags;
 };
 
-int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info);
 int tsec_standard_init(bd_t *bis);
 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);