* Add support for IceCube board (with MGT5100 and MPC5200 CPUs)U-Boot-0_4_4

* Add support for MGT5100 and MPC5200 processors

10 files changed, 807 insertions, 149 deletions

diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index e3aa25d75a..4253020cb3 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -46,6 +46,10 @@ typedef	struct	global_data {
 	unsigned long	scc_clk;
 	unsigned long	brg_clk;
 #endif
+#if defined(CONFIG_MPC5XXX)
+	unsigned long	ipb_clk;
+	unsigned long	pci_clk;
+#endif
 	unsigned long	ram_size;	/* RAM size */
 	unsigned long	reloc_off;	/* Relocation Offset */
 	unsigned long	reset_status;	/* reset status register at boot	*/
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index db563a5544..8014225dbc 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -41,6 +41,9 @@ typedef struct bd_info {
 #if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260)
 	unsigned long	bi_immr_base;	/* base of IMMR register */
 #endif
+#if defined(CONFIG_MPC5XXX)
+	unsigned long	bi_mbar_base;	/* base of internal registers */
+#endif
 	unsigned long	bi_bootflags;	/* boot / reboot flag (for LynxOS) */
 	unsigned long	bi_ip_addr;	/* IP Address */
 	unsigned char	bi_enetaddr[6];	/* Ethernet adress */
@@ -53,6 +56,10 @@ typedef struct bd_info {
 	unsigned long	bi_sccfreq;	/* SCC_CLK Freq, in MHz */
 	unsigned long	bi_vco;		/* VCO Out from PLL, in MHz */
 #endif
+#if defined(CONFIG_MPC5XXX)
+	unsigned long	bi_ipbfreq;	/* IPB Bus Freq, in MHz */
+	unsigned long	bi_pcifreq;	/* PCI Bus Freq, in MHz */
+#endif
 	unsigned long	bi_baudrate;	/* Console Baudrate */
 #if defined(CONFIG_405GP) || \
     defined(CONFIG_405CR) || \
diff --git a/include/common.h b/include/common.h
index 8a98de3f26..c8ad856a50 100644
--- a/include/common.h
+++ b/include/common.h
@@ -327,6 +327,9 @@ int	get_clocks (void);
 #if defined(CONFIG_8260)
 int	prt_8260_clks (void);
 #endif
+#if defined(CONFIG_MPC5XXX)
+int	prt_mpc5xxx_clks (void);
+#endif
 #ifdef CONFIG_4xx
 ulong	get_OPB_freq (void);
 ulong	get_PCI_freq (void);
diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h
index f1ffcb3190..4e7051947c 100644
--- a/include/configs/EXBITGEN.h
+++ b/include/configs/EXBITGEN.h
@@ -65,7 +65,7 @@
 /* Explanation:
    autbooting is altogether disabled and cannot be
    enabled if CONFIG_BOOTDELAY is negative.
-   If you want shorter bootdelay, then 
+   If you want shorter bootdelay, then
    - "setenv bootdelay <delay>" to the proper value
 */
 
@@ -111,11 +111,11 @@
 
 /* Default baud rate */
 #define CONFIG_BAUDRATE		115200
-	
+
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE      \
-        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-         57600, 115200, 230400, 460800, 921600 }
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
 
@@ -177,7 +177,7 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#ifdef CFG_ENV_IS_IN_FLASH 
+#ifdef CFG_ENV_IS_IN_FLASH
 #define CFG_ENV_OFFSET		0x00060000 /* Offset of Environment Sector      */
 #define	CFG_ENV_SIZE		0x00010000 /* Total Size of Environment Sector	*/
 #define CFG_ENV_SECT_SIZE	0x00010000 /* see README - env sector total size */
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
new file mode 100644
index 0000000000..e6d735a229
--- /dev/null
+++ b/include/configs/IceCube.h
@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5XXX		1	/* This is an MPC5xxx CPU */
+#define CONFIG_ICECUBE		1	/* ... on IceCube board */
+
+#define CFG_MPC5XXX_CLKIN	33333333 /* ... running at 33MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL & ~(CFG_CMD_NET))
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND	"bootm 100000"	/* autoboot command */
+#define CONFIG_BOOTARGS		"root=/dev/ram rw"
+
+/*
+ * I2C configuration
+ */
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE		0xff800000
+#define CFG_FLASH_SIZE		0x00800000
+
+/*
+ * Flash organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
+
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE		0x10000
+#define CFG_ENV_ADDR        (CFG_FLASH_BASE + 0x740000)
+#define CFG_ENV_SECT_SIZE   0x10000
+
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xf0000000
+#define CFG_SDRAM_BASE		0x00000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT 1
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#if 0
+#define CONFIG_NET_MULTI	1
+#define CONFIG_MPC5XXX_FEC	1
+#endif
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG	0x00000004
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x00047801
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h
index f902685b32..535ec79851 100644
--- a/include/configs/TOP860.h
+++ b/include/configs/TOP860.h
@@ -25,15 +25,15 @@
  * MA 02111-1307 USA
  */
 /*
- * TOP860 is a simple module:

- * 16-bit wide FLASH on CS0	(2MB or more)

- * 32-bit wide DRAM on CS2 (either 4MB or 16MB)

- * FEC with Am79C874 100-Base-T and Fiber Optic

- * Ports available, but we choose SMC1 for Console

+ * TOP860 is a simple module:
+ * 16-bit wide FLASH on CS0	(2MB or more)
+ * 32-bit wide DRAM on CS2 (either 4MB or 16MB)
+ * FEC with Am79C874 100-Base-T and Fiber Optic
+ * Ports available, but we choose SMC1 for Console
  * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
- * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock

- *

- * This config has been copied from MBX.h / MBX860T.h

+ * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
+ *
+ * This config has been copied from MBX.h / MBX860T.h
  */
 /*
  * board/config.h - configuration options, board specific
@@ -54,36 +54,36 @@
 #define CONFIG_MPC860T	1	/* even better... an FEC!	*/
 #define CONFIG_TOP860	1	/* ...on a TOP860 module	*/
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#define	CONFIG_IDENT_STRING " EMK TOP860"

+#define	CONFIG_IDENT_STRING " EMK TOP860"
 
 /*-----------------------------------------------------------------------
  * CLOCK settings
  */
-#define	CONFIG_SYSCLK	49152000

-#define	CFG_XTAL		32768

-#define	CONFIG_EBDF		1

-#define	CONFIG_COM		3

-#define	CONFIG_RTC_MPC8xx

-

+#define	CONFIG_SYSCLK	49152000
+#define	CFG_XTAL		32768
+#define	CONFIG_EBDF		1
+#define	CONFIG_COM		3
+#define	CONFIG_RTC_MPC8xx
+
 /*-----------------------------------------------------------------------
  * Physical memory map as defined by EMK
  */
 #define CFG_IMMR		0xFFF00000	/* Internal Memory Mapped Register */
-#define	CFG_FLASH_BASE	0x80000000	/* FLASH in final mapping */

-#define	CFG_DRAM_BASE	0x00000000	/* DRAM in final mapping */

-#define	CFG_FLASH_MAX	0x00400000	/* max FLASH to expect */

-#define	CFG_DRAM_MAX	0x01000000	/* max DRAM to expect */

-

+#define	CFG_FLASH_BASE	0x80000000	/* FLASH in final mapping */
+#define	CFG_DRAM_BASE	0x00000000	/* DRAM in final mapping */
+#define	CFG_FLASH_MAX	0x00400000	/* max FLASH to expect */
+#define	CFG_DRAM_MAX	0x01000000	/* max DRAM to expect */
+
 /*-----------------------------------------------------------------------
  * derived values
  */
-#define	CFG_MF			(CONFIG_SYSCLK/CFG_XTAL)

-#define	CFG_CPUCLOCK	CONFIG_SYSCLK

-#define	CFG_BRGCLOCK	CONFIG_SYSCLK

-#define	CFG_BUSCLOCK	(CONFIG_SYSCLK >> CONFIG_EBDF)

+#define	CFG_MF			(CONFIG_SYSCLK/CFG_XTAL)
+#define	CFG_CPUCLOCK	CONFIG_SYSCLK
+#define	CFG_BRGCLOCK	CONFIG_SYSCLK
+#define	CFG_BUSCLOCK	(CONFIG_SYSCLK >> CONFIG_EBDF)
 #define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-#define	CONFIG_8xx_GCLK_FREQ	CONFIG_SYSCLK

-

+#define	CONFIG_8xx_GCLK_FREQ	CONFIG_SYSCLK
+
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
@@ -92,8 +92,8 @@
 
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-

-#define	CFG_FLASH_CFI

+
+#define	CFG_FLASH_CFI
 
 /*-----------------------------------------------------------------------
  * Command interpreter
@@ -101,7 +101,7 @@
 #define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
 #undef	CONFIG_8xx_CONS_SMC2
 #define CONFIG_BAUDRATE		9600
-

+
 /*
  * Allow partial commands to be matched to uniqueness.
  */
@@ -125,8 +125,8 @@
 								CFG_CMD_BEDBUG	\
 						      )
 
-#define	CONFIG_AUTOSCRIPT		1

-#define	CFG_LOADS_BAUD_CHANGE	1

+#define	CONFIG_AUTOSCRIPT		1
+#define	CFG_LOADS_BAUD_CHANGE	1
 #undef	CONFIG_LOADS_ECHO			/* NO echo on for serial download	*/
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -134,19 +134,19 @@
 
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-

+
 #undef	CFG_HUSH_PARSER			/* Hush parse for U-Boot	*/
-

+
 #ifdef	CFG_HUSH_PARSER
  #define CFG_PROMPT_HUSH_PS2	"> "
 #endif
-

+
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
  #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-

+
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
@@ -156,63 +156,63 @@
  */
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-

+
 /*-----------------------------------------------------------------------
  * Environment handler
  * only the first 6k in EEPROM are available for user. Of that we use 256b
  */
-#define	CONFIG_SOFT_I2C

+#define	CONFIG_SOFT_I2C
 #define CFG_ENV_IS_IN_EEPROM	1	/* turn on EEPROM env feature */
 #define CFG_ENV_OFFSET		0x1000
-#define CFG_ENV_SIZE		0x0700

-#define CFG_I2C_EEPROM_ADDR 0x57

+#define CFG_ENV_SIZE		0x0700
+#define CFG_I2C_EEPROM_ADDR 0x57
 #define CFG_FACT_OFFSET		0x1800
-#define CFG_FACT_SIZE		0x0800

-#define CFG_I2C_FACT_ADDR	0x57

-#define CFG_EEPROM_PAGE_WRITE_BITS 3

-#define CFG_I2C_EEPROM_ADDR_LEN 2

+#define CFG_FACT_SIZE		0x0800
+#define CFG_I2C_FACT_ADDR	0x57
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_I2C_EEPROM_ADDR_LEN 2
 #define CFG_EEPROM_SIZE 0x2000
 #define	CFG_I2C_SPEED	100000
-#define	CFG_I2C_SLAVE	0xFE

-#define	CFG_EEPROM_PAGE_WRITE_DELAY_MS 12

-#define CONFIG_ENV_OVERWRITE

-#define CONFIG_MISC_INIT_R

-

-#if defined (CONFIG_SOFT_I2C)

-#define	SDA	0x00010

-#define	SCL	0x00020

-#define DIR immr->im_cpm.cp_pbdir

-#define DAT	immr->im_cpm.cp_pbdat

-#define PAR	immr->im_cpm.cp_pbpar

-#define	ODR	immr->im_cpm.cp_pbodr

-#define	I2C_INIT	{PAR&=~(SDA|SCL);ODR&=~(SDA|SCL);DAT|=(SDA|SCL);DIR|=(SDA|SCL);}

-#define	I2C_READ	((DAT&SDA)?1:0)

-#define	I2C_SDA(x)	{if(x)DAT|=SDA;else DAT&=~SDA;}

-#define	I2C_SCL(x)	{if(x)DAT|=SCL;else DAT&=~SCL;}

-#define	I2C_DELAY	{udelay(5);}

-#define	I2C_ACTIVE	 {DIR|=SDA;}

-#define	I2C_TRISTATE {DIR&=~SDA;}

+#define	CFG_I2C_SLAVE	0xFE
+#define	CFG_EEPROM_PAGE_WRITE_DELAY_MS 12
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_MISC_INIT_R
+
+#if defined (CONFIG_SOFT_I2C)
+#define	SDA	0x00010
+#define	SCL	0x00020
+#define DIR immr->im_cpm.cp_pbdir
+#define DAT	immr->im_cpm.cp_pbdat
+#define PAR	immr->im_cpm.cp_pbpar
+#define	ODR	immr->im_cpm.cp_pbodr
+#define	I2C_INIT	{PAR&=~(SDA|SCL);ODR&=~(SDA|SCL);DAT|=(SDA|SCL);DIR|=(SDA|SCL);}
+#define	I2C_READ	((DAT&SDA)?1:0)
+#define	I2C_SDA(x)	{if(x)DAT|=SDA;else DAT&=~SDA;}
+#define	I2C_SCL(x)	{if(x)DAT|=SCL;else DAT&=~SCL;}
+#define	I2C_DELAY	{udelay(5);}
+#define	I2C_ACTIVE	 {DIR|=SDA;}
+#define	I2C_TRISTATE {DIR&=~SDA;}
 #endif
 
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*-----------------------------------------------------------------------
  * defines we need to get FEC running
- */

+ */
 #define	CONFIG_NET_MULTI	1	/* the only way to get the FEC in */
 #define CONFIG_FEC_ENET 	1	/* Ethernet only via FEC	*/
-#define	FEC_ENET			1	/* eth.c needs it that way... */

+#define	FEC_ENET			1	/* eth.c needs it that way... */
 #define CFG_DISCOVER_PHY	1
 #define CONFIG_MII			1
 #define CONFIG_PHY_ADDR		31
-

+
 /*-----------------------------------------------------------------------
  * adresses
- */

+ */
 #define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #define CFG_MONITOR_BASE	TEXT_BASE
 #define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-

+
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
@@ -220,7 +220,7 @@
  */
 #define CFG_SDRAM_BASE		0x00000000
 #define CFG_FLASH_BASE		0x80000000
-

+
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
@@ -262,36 +262,36 @@
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
  *-----------------------------------------------------------------------
- * set up PLPRCR (PLL, Low-Power, and Reset Control Register)

- *	12	MF		calculated	Multiplication factor

- *	4	0		0000

- *	1	SPLSS	0			System PLL lock status sticky

- *	1	TEXPS	1			Timer expired status

- *	1	0		0

- *	1	TMIST	0			Timers interrupt status

- *	1	0		0

- *	1	CSRC	0			Clock source (0=DFNH, 1=DFNL)

- *	2	LPM		00			Low-power modes

- *	1	CSR		0			Checkstop reset enable

- *	1	LOLRE	0			Loss-of-lock reset enable

- *	1	FIOPD	0			Force I/O pull down

- *	5	0		00000			

+ * set up PLPRCR (PLL, Low-Power, and Reset Control Register)
+ *	12	MF		calculated	Multiplication factor
+ *	4	0		0000
+ *	1	SPLSS	0			System PLL lock status sticky
+ *	1	TEXPS	1			Timer expired status
+ *	1	0		0
+ *	1	TMIST	0			Timers interrupt status
+ *	1	0		0
+ *	1	CSRC	0			Clock source (0=DFNH, 1=DFNL)
+ *	2	LPM		00			Low-power modes
+ *	1	CSR		0			Checkstop reset enable
+ *	1	LOLRE	0			Loss-of-lock reset enable
+ *	1	FIOPD	0			Force I/O pull down
+ *	5	0		00000			
  */
 #define CFG_PLPRCR	(PLPRCR_TEXPS | ((CFG_MF-1)<<20))
-

+
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control				11-9
  * SYPCR can only be written once after reset!
  *-----------------------------------------------------------------------
- * set up SYPCR:

- *	16	SWTC	0xffff		Software watchdog timer count

- *	8	BMT		0xff 		Bus monitor timing

- *	1	BME		1			Bus monitor enable

- *	3	0		000

- *	1	SWF		1			Software watchdog freeze

- *	1	SWE		0/1			Software watchdog enable

- *	1	SWRI	0/1			Software watchdog reset/interrupt select (1=HRESET)

- *	1	SWP		0/1			Software watchdog prescale (1=/2048)

+ * set up SYPCR:
+ *	16	SWTC	0xffff		Software watchdog timer count
+ *	8	BMT		0xff 		Bus monitor timing
+ *	1	BME		1			Bus monitor enable
+ *	3	0		000
+ *	1	SWF		1			Software watchdog freeze
+ *	1	SWE		0/1			Software watchdog enable
+ *	1	SWRI	0/1			Software watchdog reset/interrupt select (1=HRESET)
+ *	1	SWP		0/1			Software watchdog prescale (1=/2048)
  */
 #if defined (CONFIG_WATCHDOG)
  #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
@@ -303,31 +303,31 @@
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration				11-6
  *-----------------------------------------------------------------------
- * set up SIUMCR

- *	1	EARB	0			External arbitration

- *	3	EARP	000			External arbitration request priority

- *	4	0		0000

- *	1	DSHW	0			Data show cycles

- *	2	DBGC	00			Debug pin configuration

- *	2	DBPC	00			Debug port pins configuration

- *	1	0		0

- *	1	FRC		0			FRZ pin configuration

- *	1	DLK		0			Debug register lock

- *	1	OPAR	0			Odd parity

- *	1	PNCS	0			Parity enable for non memory controller regions

- *	1	DPC		0			Data parity pins configuration

- *	1	MPRE	0			Multiprocessor reservation enable

- *	2	MLRC	11			Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)

- *	1	AEME	0			Async external master enable

- *	1	SEME	0			Sync external master enable

- *	1	BSC		0			Byte strobe configuration

- *	1	GB5E	0			GPL_B5 enable

- *	1	B2DD	0			Bank 2 double drive			

- *	1	B3DD	0			Bank 3 double drive			

- *	4	0		0000

+ * set up SIUMCR
+ *	1	EARB	0			External arbitration
+ *	3	EARP	000			External arbitration request priority
+ *	4	0		0000
+ *	1	DSHW	0			Data show cycles
+ *	2	DBGC	00			Debug pin configuration
+ *	2	DBPC	00			Debug port pins configuration
+ *	1	0		0
+ *	1	FRC		0			FRZ pin configuration
+ *	1	DLK		0			Debug register lock
+ *	1	OPAR	0			Odd parity
+ *	1	PNCS	0			Parity enable for non memory controller regions
+ *	1	DPC		0			Data parity pins configuration
+ *	1	MPRE	0			Multiprocessor reservation enable
+ *	2	MLRC	11			Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
+ *	1	AEME	0			Async external master enable
+ *	1	SEME	0			Sync external master enable
+ *	1	BSC		0			Byte strobe configuration
+ *	1	GB5E	0			GPL_B5 enable
+ *	1	B2DD	0			Bank 2 double drive			
+ *	1	B3DD	0			Bank 3 double drive			
+ *	4	0		0000
  */
 #define CFG_SIUMCR	(SIUMCR_MLRC11)
-

+
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
@@ -345,30 +345,30 @@
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
  *-----------------------------------------------------------------------
- * set up SCCR (System Clock and Reset Control Register)

- *	1	0		0

- *	2	COM		11			Clock output module (00=full, 01=half, 11=off)

- *	3	0		000

- *	1	TBS		1			Timebase source (0=OSCCLK, 1=GCLK2)

- *	1	RTDIV	0			Real-time clock divide (0=/4, 1=/512)

- *	1	RTSEL	0			Real-time clock select (0=OSCM, 1=EXTCLK)

- *	1	CRQEN	0			CPM request enable

- *	1	PRQEN	0			Power management request enable

- *	2	0		00

- *	2	EBDF	xx			External bus division factor

- *	2	0		00

- *	2	DFSYNC	00			Division factor for SYNCLK

- *	2	DFBRG	00			Division factor for BRGCLK

- *	3	DFNL	000			Division factor low frequency

- *	3	DFNH	000			Division factor high frequency

- *	5	0		00000

+ * set up SCCR (System Clock and Reset Control Register)
+ *	1	0		0
+ *	2	COM		11			Clock output module (00=full, 01=half, 11=off)
+ *	3	0		000
+ *	1	TBS		1			Timebase source (0=OSCCLK, 1=GCLK2)
+ *	1	RTDIV	0			Real-time clock divide (0=/4, 1=/512)
+ *	1	RTSEL	0			Real-time clock select (0=OSCM, 1=EXTCLK)
+ *	1	CRQEN	0			CPM request enable
+ *	1	PRQEN	0			Power management request enable
+ *	2	0		00
+ *	2	EBDF	xx			External bus division factor
+ *	2	0		00
+ *	2	DFSYNC	00			Division factor for SYNCLK
+ *	2	DFBRG	00			Division factor for BRGCLK
+ *	3	DFNL	000			Division factor low frequency
+ *	3	DFNH	000			Division factor high frequency
+ *	5	0		00000
  */
 #define SCCR_MASK	0
-#if CONFIG_EBDF

+#if CONFIG_EBDF
  #define CFG_SCCR	(SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
-#else

+#else
  #define CFG_SCCR	(SCCR_COM11 | SCCR_TBS)
-#endif

+#endif
 
 /*-----------------------------------------------------------------------
  * Chip Select 0 - FLASH
@@ -379,7 +379,7 @@
 #define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
 #define CFG_OR0_PRELIM	(-CFG_FLASH_MAX | CFG_OR_TIMING_FLASH)
 #define CFG_BR0_PRELIM	(CFG_FLASH_BASE | BR_PS_16 | BR_V )
-

+
 /*-----------------------------------------------------------------------
  * misc
  *-----------------------------------------------------------------------
@@ -408,11 +408,11 @@
 /*
  * BOOTP options
  */
-#undef	CONFIG_BOOTP_MASK

+#undef	CONFIG_BOOTP_MASK
 #define CONFIG_BOOTP_MASK				( CONFIG_BOOTP_DEFAULT		| \
 									  	  CONFIG_BOOTP_BOOTFILESIZE   \
-										)

-										

+										)
+										
 
 /*
  * Set default IP stuff just to get bootstrap entries into the
@@ -421,13 +421,13 @@
 #define CONFIG_ETHADDR					9a:52:63:15:85:25
 #define CONFIG_SERVERIP					10.0.4.200
 #define CONFIG_IPADDR					10.0.4.111
-

+
 /*-----------------------------------------------------------------------
  * Defaults for Autoscript
  */
 #define CFG_LOAD_ADDR		0x00100000	/* default load address */
 #define	CFG_TFTP_LOADADDR	0x00100000
-

+
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
@@ -435,5 +435,5 @@
  */
 #define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-

+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/omap1510.h b/include/configs/omap1510.h
index 001e21aea9..540630b593 100644
--- a/include/configs/omap1510.h
+++ b/include/configs/omap1510.h
@@ -521,7 +521,6 @@ typedef struct {
 #define WDTIM_CONTROL_ST	BIT7
 
 
-
 /* ---------------------------------------------------------------------------
  *  Differentiating processor versions for those who care.
  * ---------------------------------------------------------------------------
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
new file mode 100644
index 0000000000..e0f23676f1
--- /dev/null
+++ b/include/mpc5xxx.h
@@ -0,0 +1,467 @@
+/*
+ * include/asm-ppc/mpc5xxx.h
+ *
+ * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx
+ * embedded cpu chips
+ *
+ * 2003 (c) MontaVista, Software, Inc.
+ * Author: Dale Farnsworth <dfarnsworth@mvista.com>
+ *
+ * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASMPPC_MPC5XXX_H
+#define __ASMPPC_MPC5XXX_H
+
+/* Processor name */
+#if defined(CONFIG_MPC5200)
+#define CPU_ID_STR	"MPC5200"
+#elif defined(CONFIG_MGT5100)
+#define CPU_ID_STR	"MGT5100"
+#endif
+
+/* Exception offsets (PowerPC standard) */
+#define EXC_OFF_SYS_RESET	0x0100
+
+/* Internal memory map */
+
+#define MPC5XXX_CS0_START	(CFG_MBAR + 0x0004)
+#define MPC5XXX_CS0_STOP	(CFG_MBAR + 0x0008)
+#define MPC5XXX_CS1_START	(CFG_MBAR + 0x000c)
+#define MPC5XXX_CS1_STOP	(CFG_MBAR + 0x0010)
+#define MPC5XXX_CS2_START	(CFG_MBAR + 0x0014)
+#define MPC5XXX_CS2_STOP	(CFG_MBAR + 0x0018)
+#define MPC5XXX_CS3_START	(CFG_MBAR + 0x001c)
+#define MPC5XXX_CS3_STOP	(CFG_MBAR + 0x0020)
+#define MPC5XXX_CS4_START	(CFG_MBAR + 0x0024)
+#define MPC5XXX_CS4_STOP	(CFG_MBAR + 0x0028)
+#define MPC5XXX_CS5_START	(CFG_MBAR + 0x002c)
+#define MPC5XXX_CS5_STOP	(CFG_MBAR + 0x0030)
+#define MPC5XXX_BOOTCS_START	(CFG_MBAR + 0x004c)
+#define MPC5XXX_BOOTCS_STOP	(CFG_MBAR + 0x0050)
+#define MPC5XXX_ADDECR		(CFG_MBAR + 0x0054)
+
+#if defined(CONFIG_MGT5100)
+#define MPC5XXX_SDRAM_START	(CFG_MBAR + 0x0034)
+#define MPC5XXX_SDRAM_STOP	(CFG_MBAR + 0x0038)
+#elif defined(CONFIG_MPC5200)
+#define MPC5XXX_CS6_START	(CFG_MBAR + 0x0058)
+#define MPC5XXX_CS6_STOP	(CFG_MBAR + 0x005c)
+#define MPC5XXX_CS7_START	(CFG_MBAR + 0x0060)
+#define MPC5XXX_CS7_STOP	(CFG_MBAR + 0x0064)
+#define MPC5XXX_SDRAM_CS0CFG	(CFG_MBAR + 0x0034)
+#define MPC5XXX_SDRAM_CS1CFG	(CFG_MBAR + 0x0038)
+#endif
+
+#define MPC5XXX_SDRAM		(CFG_MBAR + 0x0100)
+#define MPC5XXX_CDM		(CFG_MBAR + 0x0200)
+#define MPC5XXX_LPB		(CFG_MBAR + 0x0300)
+#define MPC5XXX_ICTL		(CFG_MBAR + 0x0500)
+#define MPC5XXX_GPIO		(CFG_MBAR + 0x0b00)
+#define MPC5XXX_SDMA		(CFG_MBAR + 0x1200)
+#define MPC5XXX_XLBARB		(CFG_MBAR + 0x1f00)
+
+#if defined(CONFIG_MGT5100)
+#define	MPC5XXX_PSC1		(CFG_MBAR + 0x2000)
+#define	MPC5XXX_PSC2		(CFG_MBAR + 0x2400)
+#define	MPC5XXX_PSC3		(CFG_MBAR + 0x2800)
+#elif defined(CONFIG_MPC5200)
+#define	MPC5XXX_PSC1		(CFG_MBAR + 0x2000)
+#define	MPC5XXX_PSC2		(CFG_MBAR + 0x2200)
+#define	MPC5XXX_PSC3		(CFG_MBAR + 0x2400)
+#define	MPC5XXX_PSC4		(CFG_MBAR + 0x2600)
+#define	MPC5XXX_PSC5		(CFG_MBAR + 0x2800)
+#define	MPC5XXX_PSC6		(CFG_MBAR + 0x2c00)
+#endif
+
+#define	MPC5XXX_FEC		(CFG_MBAR + 0x3000)
+
+#if defined(CONFIG_MGT5100)
+#define MPC5XXX_SRAM		(CFG_MBAR + 0x4000)
+#define MPC5XXX_SRAM_SIZE	(8*1024)
+#elif defined(CONFIG_MPC5200)
+#define MPC5XXX_SRAM		(CFG_MBAR + 0x8000)
+#define MPC5XXX_SRAM_SIZE	(16*1024)
+#endif
+
+/* SDRAM Controller */
+#define MPC5XXX_SDRAM_MODE	(MPC5XXX_SDRAM + 0x0000)
+#define MPC5XXX_SDRAM_CTRL	(MPC5XXX_SDRAM + 0x0004)
+#define MPC5XXX_SDRAM_CONFIG1	(MPC5XXX_SDRAM + 0x0008)
+#define MPC5XXX_SDRAM_CONFIG2	(MPC5XXX_SDRAM + 0x000c)
+#if defined(CONFIG_MGT5100)
+#define MPC5XXX_SDRAM_XLBSEL	(MPC5XXX_SDRAM + 0x0010)
+#endif
+
+/* Clock Distribution Module */
+#define MPC5XXX_CDM_JTAGID	(MPC5XXX_CDM + 0x0000)
+#define MPC5XXX_CDM_PORCFG	(MPC5XXX_CDM + 0x0004)
+#define MPC5XXX_CDM_CFG		(MPC5XXX_CDM + 0x000c)
+#define MPC5XXX_CDM_SRESET	(MPC5XXX_CDM + 0x0020)
+
+/* Local Plus Bus interface */
+#define MPC5XXX_CS0_CFG		(MPC5XXX_LPB + 0x0000)
+#define MPC5XXX_CS1_CFG		(MPC5XXX_LPB + 0x0004)
+#define MPC5XXX_CS2_CFG		(MPC5XXX_LPB + 0x0008)
+#define MPC5XXX_CS3_CFG		(MPC5XXX_LPB + 0x000c)
+#define MPC5XXX_CS4_CFG		(MPC5XXX_LPB + 0x0010)
+#define MPC5XXX_CS5_CFG		(MPC5XXX_LPB + 0x0014)
+#define MPC5XXX_BOOTCS_CFG	MPC5XXX_CS0_CFG
+#define MPC5XXX_CS_CTRL		(MPC5XXX_LPB + 0x0018)
+#define MPC5XXX_CS_STATUS	(MPC5XXX_LPB + 0x001c)
+#if defined(CONFIG_MPC5200)
+#define MPC5XXX_CS6_CFG		(MPC5XXX_LPB + 0x0020)
+#define MPC5XXX_CS7_CFG		(MPC5XXX_LPB + 0x0024)
+#define MPC5XXX_CS_BURST	(MPC5XXX_LPB + 0x0028)
+#define MPC5XXX_CS_DEADCYCLE	(MPC5XXX_LPB + 0x002c)
+#endif
+
+/* GPIO registers */
+#define MPC5XXX_GPS_PORT_CONFIG	(MPC5XXX_GPIO + 0x0000)
+
+/* Interrupt Controller registers */
+#define MPC5XXX_ICTL_PER_MASK	(MPC5XXX_ICTL + 0x0000)
+#define MPC5XXX_ICTL_PER_PRIO1	(MPC5XXX_ICTL + 0x0004)
+#define MPC5XXX_ICTL_PER_PRIO2	(MPC5XXX_ICTL + 0x0008)
+#define MPC5XXX_ICTL_PER_PRIO3	(MPC5XXX_ICTL + 0x000c)
+#define MPC5XXX_ICTL_EXT	(MPC5XXX_ICTL + 0x0010)
+#define MPC5XXX_ICTL_CRIT	(MPC5XXX_ICTL + 0x0014)
+#define MPC5XXX_ICTL_MAIN_PRIO1	(MPC5XXX_ICTL + 0x0018)
+#define MPC5XXX_ICTL_MAIN_PRIO2	(MPC5XXX_ICTL + 0x001c)
+#define MPC5XXX_ICTL_STS	(MPC5XXX_ICTL + 0x0024)
+#define MPC5XXX_ICTL_CRIT_STS	(MPC5XXX_ICTL + 0x0028)
+#define MPC5XXX_ICTL_MAIN_STS	(MPC5XXX_ICTL + 0x002c)
+#define MPC5XXX_ICTL_PER_STS	(MPC5XXX_ICTL + 0x0030)
+#define MPC5XXX_ICTL_BUS_STS	(MPC5XXX_ICTL + 0x0038)
+
+/* Programmable Serial Controller (PSC) status register bits */
+#define PSC_SR_CDE		0x0080
+#define PSC_SR_RXRDY		0x0100
+#define PSC_SR_RXFULL		0x0200
+#define PSC_SR_TXRDY		0x0400
+#define PSC_SR_TXEMP		0x0800
+#define PSC_SR_OE		0x1000
+#define PSC_SR_PE		0x2000
+#define PSC_SR_FE		0x4000
+#define PSC_SR_RB		0x8000
+
+/* PSC Command values */
+#define PSC_RX_ENABLE		0x0001
+#define PSC_RX_DISABLE		0x0002
+#define PSC_TX_ENABLE		0x0004
+#define PSC_TX_DISABLE		0x0008
+#define PSC_SEL_MODE_REG_1	0x0010
+#define PSC_RST_RX		0x0020
+#define PSC_RST_TX		0x0030
+#define PSC_RST_ERR_STAT	0x0040
+#define PSC_RST_BRK_CHG_INT	0x0050
+#define PSC_START_BRK		0x0060
+#define PSC_STOP_BRK		0x0070
+
+/* PSC Rx FIFO status bits */
+#define PSC_RX_FIFO_ERR		0x0040
+#define PSC_RX_FIFO_UF		0x0020
+#define PSC_RX_FIFO_OF		0x0010
+#define PSC_RX_FIFO_FR		0x0008
+#define PSC_RX_FIFO_FULL	0x0004
+#define PSC_RX_FIFO_ALARM	0x0002
+#define PSC_RX_FIFO_EMPTY	0x0001
+
+/* PSC interrupt mask bits */
+#define PSC_IMR_TXRDY		0x0100
+#define PSC_IMR_RXRDY		0x0200
+#define PSC_IMR_DB		0x0400
+#define PSC_IMR_IPC		0x8000
+
+/* PSC input port change bits */
+#define PSC_IPCR_CTS		0x01
+#define PSC_IPCR_DCD		0x02
+
+/* PSC mode fields */
+#define PSC_MODE_5_BITS		0x00
+#define PSC_MODE_6_BITS		0x01
+#define PSC_MODE_7_BITS		0x02
+#define PSC_MODE_8_BITS		0x03
+#define PSC_MODE_PAREVEN	0x00
+#define PSC_MODE_PARODD		0x04
+#define PSC_MODE_PARFORCE	0x08
+#define PSC_MODE_PARNONE	0x10
+#define PSC_MODE_ERR		0x20
+#define PSC_MODE_FFULL		0x40
+#define PSC_MODE_RXRTS		0x80
+
+#define PSC_MODE_ONE_STOP_5_BITS	0x00
+#define PSC_MODE_ONE_STOP		0x07
+#define PSC_MODE_TWO_STOP		0x0f
+
+#ifndef __ASSEMBLY__
+struct mpc5xxx_psc {
+	volatile u8	mode;		/* PSC + 0x00 */
+	volatile u8	reserved0[3];
+	union {				/* PSC + 0x04 */
+		volatile u16	status;
+		volatile u16	clock_select;
+	} sr_csr;
+#define psc_status	sr_csr.status
+#define psc_clock_select sr_csr.clock_select
+	volatile u16	reserved1;
+	volatile u8	command;	/* PSC + 0x08 */
+	volatile u8	reserved2[3];
+	union {				/* PSC + 0x0c */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} buffer;
+#define psc_buffer_8	buffer.buffer_8
+#define psc_buffer_16	buffer.buffer_16
+#define psc_buffer_32	buffer.buffer_32
+	union {				/* PSC + 0x10 */
+		volatile u8	ipcr;
+		volatile u8	acr;
+	} ipcr_acr;
+#define psc_ipcr	ipcr_acr.ipcr
+#define psc_acr		ipcr_acr.acr
+	volatile u8	reserved3[3];
+	union {				/* PSC + 0x14 */
+		volatile u16	isr;
+		volatile u16	imr;
+	} isr_imr;
+#define psc_isr		isr_imr.isr
+#define psc_imr		isr_imr.imr
+	volatile u16	reserved4;
+	volatile u8	ctur;		/* PSC + 0x18 */
+	volatile u8	reserved5[3];
+	volatile u8	ctlr;		/* PSC + 0x1c */
+	volatile u8	reserved6[19];
+	volatile u8	ivr;		/* PSC + 0x30 */
+	volatile u8	reserved7[3];
+	volatile u8	ip;		/* PSC + 0x34 */
+	volatile u8	reserved8[3];
+	volatile u8	op1;		/* PSC + 0x38 */
+	volatile u8	reserved9[3];
+	volatile u8	op0;		/* PSC + 0x3c */
+	volatile u8	reserved10[3];
+	volatile u8	sicr;		/* PSC + 0x40 */
+	volatile u8	reserved11[3];
+	volatile u8	ircr1;		/* PSC + 0x44 */
+	volatile u8	reserved12[3];
+	volatile u8	ircr2;		/* PSC + 0x44 */
+	volatile u8	reserved13[3];
+	volatile u8	irsdr;		/* PSC + 0x4c */
+	volatile u8	reserved14[3];
+	volatile u8	irmdr;		/* PSC + 0x50 */
+	volatile u8	reserved15[3];
+	volatile u8	irfdr;		/* PSC + 0x54 */
+	volatile u8	reserved16[3];
+	volatile u16	rfnum;		/* PSC + 0x58 */
+	volatile u16	reserved17;
+	volatile u16	tfnum;		/* PSC + 0x5c */
+	volatile u16	reserved18;
+	volatile u32	rfdata;		/* PSC + 0x60 */
+	volatile u16	rfstat;		/* PSC + 0x64 */
+	volatile u16	reserved20;
+	volatile u8	rfcntl;		/* PSC + 0x68 */
+	volatile u8	reserved21[5];
+	volatile u16	rfalarm;	/* PSC + 0x6e */
+	volatile u16	reserved22;
+	volatile u16	rfrptr;		/* PSC + 0x72 */
+	volatile u16	reserved23;
+	volatile u16	rfwptr;		/* PSC + 0x76 */
+	volatile u16	reserved24;
+	volatile u16	rflrfptr;	/* PSC + 0x7a */
+	volatile u16	reserved25;
+	volatile u16	rflwfptr;	/* PSC + 0x7e */
+	volatile u32	tfdata;		/* PSC + 0x80 */
+	volatile u16	tfstat;		/* PSC + 0x84 */
+	volatile u16	reserved26;
+	volatile u8	tfcntl;		/* PSC + 0x88 */
+	volatile u8	reserved27[5];
+	volatile u16	tfalarm;	/* PSC + 0x8e */
+	volatile u16	reserved28;
+	volatile u16	tfrptr;		/* PSC + 0x92 */
+	volatile u16	reserved29;
+	volatile u16	tfwptr;		/* PSC + 0x96 */
+	volatile u16	reserved30;
+	volatile u16	tflrfptr;	/* PSC + 0x9a */
+	volatile u16	reserved31;
+	volatile u16	tflwfptr;	/* PSC + 0x9e */
+};
+
+struct mpc5xxx_intr {
+	volatile u32	per_mask;	/* INTR + 0x00 */
+	volatile u32	per_pri1;	/* INTR + 0x04 */
+	volatile u32	per_pri2;	/* INTR + 0x08 */
+	volatile u32	per_pri3;	/* INTR + 0x0c */
+	volatile u32	ctrl;		/* INTR + 0x10 */
+	volatile u32	main_mask;	/* INTR + 0x14 */
+	volatile u32	main_pri1;	/* INTR + 0x18 */
+	volatile u32	main_pri2;	/* INTR + 0x1c */
+	volatile u32	reserved1;	/* INTR + 0x20 */
+	volatile u32	enc_status;	/* INTR + 0x24 */
+	volatile u32	crit_status;	/* INTR + 0x28 */
+	volatile u32	main_status;	/* INTR + 0x2c */
+	volatile u32	per_status;	/* INTR + 0x30 */
+	volatile u32	reserved2;	/* INTR + 0x34 */
+	volatile u32	per_error;	/* INTR + 0x38 */
+};
+
+struct mpc5xxx_gpio {
+	volatile u32 port_config;	/* GPIO + 0x00 */
+	volatile u32 simple_gpioe;	/* GPIO + 0x04 */
+	volatile u32 simple_ode;	/* GPIO + 0x08 */
+	volatile u32 simple_ddr;	/* GPIO + 0x0c */
+	volatile u32 simple_dvo;	/* GPIO + 0x10 */
+	volatile u32 simple_ival;	/* GPIO + 0x14 */
+	volatile u8 outo_gpioe;		/* GPIO + 0x18 */
+	volatile u8 reserved1[3];	/* GPIO + 0x19 */
+	volatile u8 outo_dvo;		/* GPIO + 0x1c */
+	volatile u8 reserved2[3];	/* GPIO + 0x1d */
+	volatile u8 sint_gpioe;		/* GPIO + 0x20 */
+	volatile u8 reserved3[3];	/* GPIO + 0x21 */
+	volatile u8 sint_ode;		/* GPIO + 0x24 */
+	volatile u8 reserved4[3];	/* GPIO + 0x25 */
+	volatile u8 sint_ddr;		/* GPIO + 0x28 */
+	volatile u8 reserved5[3];	/* GPIO + 0x29 */
+	volatile u8 sint_dvo;		/* GPIO + 0x2c */
+	volatile u8 reserved6[3];	/* GPIO + 0x2d */
+	volatile u8 sint_inten;		/* GPIO + 0x30 */
+	volatile u8 reserved7[3];	/* GPIO + 0x31 */
+	volatile u16 sint_itype;	/* GPIO + 0x34 */
+	volatile u16 reserved8;		/* GPIO + 0x36 */
+	volatile u8 gpio_control;	/* GPIO + 0x38 */
+	volatile u8 reserved9[3];	/* GPIO + 0x39 */
+	volatile u8 sint_istat;		/* GPIO + 0x3c */
+	volatile u8 sint_ival;		/* GPIO + 0x3d */
+	volatile u8 bus_errs;		/* GPIO + 0x3e */
+	volatile u8 reserved10;		/* GPIO + 0x3f */
+};
+
+struct mpc5xxx_sdma {
+	volatile u32 taskBar;		/* SDMA + 0x00 */
+	volatile u32 currentPointer;	/* SDMA + 0x04 */
+	volatile u32 endPointer;	/* SDMA + 0x08 */
+	volatile u32 variablePointer;	/* SDMA + 0x0c */
+
+	volatile u8 IntVect1;		/* SDMA + 0x10 */
+	volatile u8 IntVect2;		/* SDMA + 0x11 */
+	volatile u16 PtdCntrl;		/* SDMA + 0x12 */
+
+	volatile u32 IntPend;		/* SDMA + 0x14 */
+	volatile u32 IntMask;		/* SDMA + 0x18 */
+
+	volatile u16 tcr_0;		/* SDMA + 0x1c */
+	volatile u16 tcr_1;		/* SDMA + 0x1e */
+	volatile u16 tcr_2;		/* SDMA + 0x20 */
+	volatile u16 tcr_3;		/* SDMA + 0x22 */
+	volatile u16 tcr_4;		/* SDMA + 0x24 */
+	volatile u16 tcr_5;		/* SDMA + 0x26 */
+	volatile u16 tcr_6;		/* SDMA + 0x28 */
+	volatile u16 tcr_7;		/* SDMA + 0x2a */
+	volatile u16 tcr_8;		/* SDMA + 0x2c */
+	volatile u16 tcr_9;		/* SDMA + 0x2e */
+	volatile u16 tcr_a;		/* SDMA + 0x30 */
+	volatile u16 tcr_b;		/* SDMA + 0x32 */
+	volatile u16 tcr_c;		/* SDMA + 0x34 */
+	volatile u16 tcr_d;		/* SDMA + 0x36 */
+	volatile u16 tcr_e;		/* SDMA + 0x38 */
+	volatile u16 tcr_f;		/* SDMA + 0x3a */
+
+	volatile u8 IPR0;		/* SDMA + 0x3c */
+	volatile u8 IPR1;		/* SDMA + 0x3d */
+	volatile u8 IPR2;		/* SDMA + 0x3e */
+	volatile u8 IPR3;		/* SDMA + 0x3f */
+	volatile u8 IPR4;		/* SDMA + 0x40 */
+	volatile u8 IPR5;		/* SDMA + 0x41 */
+	volatile u8 IPR6;		/* SDMA + 0x42 */
+	volatile u8 IPR7;		/* SDMA + 0x43 */
+	volatile u8 IPR8;		/* SDMA + 0x44 */
+	volatile u8 IPR9;		/* SDMA + 0x45 */
+	volatile u8 IPR10;		/* SDMA + 0x46 */
+	volatile u8 IPR11;		/* SDMA + 0x47 */
+	volatile u8 IPR12;		/* SDMA + 0x48 */
+	volatile u8 IPR13;		/* SDMA + 0x49 */
+	volatile u8 IPR14;		/* SDMA + 0x4a */
+	volatile u8 IPR15;		/* SDMA + 0x4b */
+	volatile u8 IPR16;		/* SDMA + 0x4c */
+	volatile u8 IPR17;		/* SDMA + 0x4d */
+	volatile u8 IPR18;		/* SDMA + 0x4e */
+	volatile u8 IPR19;		/* SDMA + 0x4f */
+	volatile u8 IPR20;		/* SDMA + 0x50 */
+	volatile u8 IPR21;		/* SDMA + 0x51 */
+	volatile u8 IPR22;		/* SDMA + 0x52 */
+	volatile u8 IPR23;		/* SDMA + 0x53 */
+	volatile u8 IPR24;		/* SDMA + 0x54 */
+	volatile u8 IPR25;		/* SDMA + 0x55 */
+	volatile u8 IPR26;		/* SDMA + 0x56 */
+	volatile u8 IPR27;		/* SDMA + 0x57 */
+	volatile u8 IPR28;		/* SDMA + 0x58 */
+	volatile u8 IPR29;		/* SDMA + 0x59 */
+	volatile u8 IPR30;		/* SDMA + 0x5a */
+	volatile u8 IPR31;		/* SDMA + 0x5b */
+
+	volatile u32 res1;		/* SDMA + 0x5c */
+	volatile u32 res2;		/* SDMA + 0x60 */
+	volatile u32 res3;		/* SDMA + 0x64 */
+	volatile u32 MDEDebug;		/* SDMA + 0x68 */
+	volatile u32 ADSDebug;		/* SDMA + 0x6c */
+	volatile u32 Value1;		/* SDMA + 0x70 */
+	volatile u32 Value2;		/* SDMA + 0x74 */
+	volatile u32 Control;		/* SDMA + 0x78 */
+	volatile u32 Status;		/* SDMA + 0x7c */
+	volatile u32 EU00;		/* SDMA + 0x80 */
+	volatile u32 EU01;		/* SDMA + 0x84 */
+	volatile u32 EU02;		/* SDMA + 0x88 */
+	volatile u32 EU03;		/* SDMA + 0x8c */
+	volatile u32 EU04;		/* SDMA + 0x90 */
+	volatile u32 EU05;		/* SDMA + 0x94 */
+	volatile u32 EU06;		/* SDMA + 0x98 */
+	volatile u32 EU07;		/* SDMA + 0x9c */
+	volatile u32 EU10;		/* SDMA + 0xa0 */
+	volatile u32 EU11;		/* SDMA + 0xa4 */
+	volatile u32 EU12;		/* SDMA + 0xa8 */
+	volatile u32 EU13;		/* SDMA + 0xac */
+	volatile u32 EU14;		/* SDMA + 0xb0 */
+	volatile u32 EU15;		/* SDMA + 0xb4 */
+	volatile u32 EU16;		/* SDMA + 0xb8 */
+	volatile u32 EU17;		/* SDMA + 0xbc */
+	volatile u32 EU20;		/* SDMA + 0xc0 */
+	volatile u32 EU21;		/* SDMA + 0xc4 */
+	volatile u32 EU22;		/* SDMA + 0xc8 */
+	volatile u32 EU23;		/* SDMA + 0xcc */
+	volatile u32 EU24;		/* SDMA + 0xd0 */
+	volatile u32 EU25;		/* SDMA + 0xd4 */
+	volatile u32 EU26;		/* SDMA + 0xd8 */
+	volatile u32 EU27;		/* SDMA + 0xdc */
+	volatile u32 EU30;		/* SDMA + 0xe0 */
+	volatile u32 EU31;		/* SDMA + 0xe4 */
+	volatile u32 EU32;		/* SDMA + 0xe8 */
+	volatile u32 EU33;		/* SDMA + 0xec */
+	volatile u32 EU34;		/* SDMA + 0xf0 */
+	volatile u32 EU35;		/* SDMA + 0xf4 */
+	volatile u32 EU36;		/* SDMA + 0xf8 */
+	volatile u32 EU37;		/* SDMA + 0xfc */
+};
+
+/* function prototypes */
+void loadtask(int basetask, int tasks);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASMPPC_MPC5XXX_H */
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 0e0bde5b99..799a726e7d 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -175,6 +175,11 @@
 #define IM_IMMR		(IM_REGBASE+0x01a8)
 #define IM_SCCR		(IM_REGBASE+0x0c80)
 
+#elif defined(CONFIG_MPC5XXX)
+
+#define HID0_ICE_BITPOS	16
+#define HID0_DCE_BITPOS	17
+
 #endif
 
 #define curptr r2
diff --git a/include/video_ad7179.h b/include/video_ad7179.h
index 4510d39784..6a1ec86024 100644
--- a/include/video_ad7179.h
+++ b/include/video_ad7179.h
@@ -23,7 +23,7 @@
 #ifndef _VIDEO_AD7179_H_
 #define _VIDEO_AD7179_H_
 
-/* 
+/*
  * The video encoder data are board specific now!
  */