Merge branch '2021-02-14-remove-some-boards'

- Remove some boards that are behind on conversions and have had their
  removal acked or suggested by the relevant maintainers.

15 files changed, 0 insertions, 3256 deletions

diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
deleted file mode 100644
index f4f41da498..0000000000
--- a/include/configs/MPC8544DS.h
+++ /dev/null
@@ -1,408 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * mpc8544ds board configuration file
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PCI1		1	/* PCI controller 1 */
-#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
-#define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
-#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-
-#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
-
-#ifndef __ASSEMBLY__
-#include <linux/stringify.h>
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE			/* toggle L2 cache */
-#define CONFIG_BTB			/* toggle branch predition */
-
-/*
- * Only possible on E500 Version 2 or newer cores.
- */
-#define CONFIG_ENABLE_36BIT_PHYS	1
-
-#define CONFIG_SYS_CCSRBAR		0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	2
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
-
-/* Make sure required options are set */
-#ifndef CONFIG_SPD_EEPROM
-#error ("CONFIG_SPD_EEPROM is required")
-#endif
-
-/*
- * Memory map
- *
- * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
- *
- * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
- *
- * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
- *
- * 0xe000_0000	0xe00f_ffff	CCSR			1M non-cacheable
- * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
- *
- * Localbus cacheable
- *
- * 0xf000_0000	0xf3ff_ffff	SDRAM			64M Cacheable
- * 0xf401_0000	0xf401_3fff	L1 for stack		4K Cacheable TLB0
- *
- * Localbus non-cacheable
- *
- * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS (*)	1M non-cacheable
- * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M non-cacheable
- * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M non-cacheable
- *
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_BOOT_BLOCK		0xfc000000	/* boot TLB */
-
-#define CONFIG_SYS_FLASH_BASE		0xff800000	/* start of FLASH 8M */
-
-#define CONFIG_SYS_BR0_PRELIM		0xff801001
-#define CONFIG_SYS_BR1_PRELIM		0xfe801001
-
-#define CONFIG_SYS_OR0_PRELIM		0xff806e65
-#define CONFIG_SYS_OR1_PRELIM		0xff806e65
-
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_LBC_NONCACHE_BASE	0xf8000000
-
-#define CONFIG_SYS_BR2_PRELIM		0xf8201001	/* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/
-
-#define CONFIG_SYS_BR3_PRELIM		0xf8100801	/* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/
-
-#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
-#define PIXIS_BASE	0xf8100000	/* PIXIS registers */
-#define PIXIS_ID		0x0	/* Board ID at offset 0 */
-#define PIXIS_VER		0x1	/* Board version at offset 1 */
-#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
-#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
-#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch
-					 * register */
-#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
-#define PIXIS_VCTL		0x10	/* VELA Control Register */
-#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
-#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
-#define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
-#define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
-#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
-#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
-#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
-#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define PIXIS_VSPEED2		0x1d	/* VELA VSpeed 2 */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/
-#define PIXIS_VSPEED2_TSEC1SER	0x2
-#define PIXIS_VSPEED2_TSEC3SER	0x1
-#define PIXIS_VCFGEN1_TSEC1SER	0x20
-#define PIXIS_VCFGEN1_TSEC3SER	0x40
-#define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
-#define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
-
-#define CONFIG_SYS_INIT_RAM_LOCK      1
-#define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_SIZE       0x00004000      /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_SYS_PCIE_VIRT		0x80000000	/* 1G PCIE TLB */
-#define CONFIG_SYS_PCIE_PHYS		0x80000000	/* 1G PCIE TLB */
-#define CONFIG_SYS_PCI_VIRT		0xc0000000	/* 512M PCI TLB */
-#define CONFIG_SYS_PCI_PHYS		0xc0000000	/* 512M PCI TLB */
-
-#define CONFIG_SYS_PCI1_MEM_VIRT	0xc0000000
-#define CONFIG_SYS_PCI1_MEM_BUS	0xc0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	0xc0000000
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
-#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
-#define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 2, Slot 1, tgtid 1, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE2_MEM_BUS	0x80000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0x80000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xe1010000
-#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xe1010000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 1, Slot 2,tgtid 2, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME		"Slot 2"
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xe1020000
-#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xe1020000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 3, direct to uli, tgtid 3, Base address b000 */
-#define CONFIG_SYS_PCIE3_NAME		"ULI"
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x00100000	/* 1M */
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xb0100000	/* reuse mem LAW */
-#define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xb0100000	/* reuse mem LAW */
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00100000	/* 1M */
-#define CONFIG_SYS_PCIE3_MEM_VIRT2	0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_BUS2	0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_PHYS2	0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_SIZE2	0x00200000	/* 1M */
-
-#if defined(CONFIG_PCI)
-
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
-
-/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
-
-/* video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#endif
-
-
-#ifndef CONFIG_PCI_PNP
-	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
-	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
-	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
-#define CONFIG_SYS_SCSI_MAX_LUN	1
-#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif /* CONFIG_SCSI_AHCI */
-
-#endif	/* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
-#define CONFIG_TSEC1	1
-#define CONFIG_TSEC1_NAME	"eTSEC1"
-#define CONFIG_TSEC3	1
-#define CONFIG_TSEC3_NAME	"eTSEC3"
-
-#define CONFIG_PIXIS_SGMII_CMD
-#define CONFIG_FSL_SGMII_RISER	1
-#define SGMII_RISER_PHY_OFFSET	0x1c
-
-#define TSEC1_PHY_ADDR		0
-#define TSEC3_PHY_ADDR		1
-
-#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX		0
-#define TSEC3_PHYIDX		0
-
-#define CONFIG_ETHPRIME		"eTSEC1"
-#endif	/* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * USB
- */
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_PCI_EHCI_DEVICE			0
-#endif
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_IPADDR	192.168.1.251
-
-#define CONFIG_HOSTNAME	"8544ds_unknown"
-#define CONFIG_ROOTPATH	"/nfs/mpc85xx"
-#define CONFIG_BOOTFILE	"8544ds/uImage.uboot"
-#define CONFIG_UBOOTPATH	8544ds/u-boot.bin	/* TFTP server */
-
-#define CONFIG_SERVERIP	192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK	255.255.0.0
-
-#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
-
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-"netdev=eth0\0"						\
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
-"tftpflash=tftpboot $loadaddr $uboot; "			\
-	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" +$filesize; "	\
-	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
-		" +$filesize; "	\
-	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" $filesize; "	\
-	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
-		" +$filesize; "	\
-	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" $filesize\0"	\
-"consoledev=ttyS0\0"				\
-"ramdiskaddr=2000000\0"			\
-"ramdiskfile=8544ds/ramdisk.uboot\0"		\
-"fdtaddr=1e00000\0"				\
-"fdtfile=8544ds/mpc8544ds.dtb\0"		\
-"bdev=sda3\0"
-
-#define CONFIG_NFSBOOTCOMMAND		\
- "setenv bootargs root=/dev/nfs rw "	\
- "nfsroot=$serverip:$rootpath "		\
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $loadaddr $bootfile;"		\
- "tftp $fdtaddr $fdtfile;"		\
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND		\
- "setenv bootargs root=/dev/ram rw "	\
- "console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $ramdiskaddr $ramdiskfile;"	\
- "tftp $loadaddr $bootfile;"		\
- "tftp $fdtaddr $fdtfile;"		\
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND		\
- "setenv bootargs root=/dev/$bdev rw "	\
- "console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $loadaddr $bootfile;"		\
- "tftp $fdtaddr $fdtfile;"		\
- "bootm $loadaddr - $fdtaddr"
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
deleted file mode 100644
index 731d4a5a41..0000000000
--- a/include/configs/MPC8572DS.h
+++ /dev/null
@@ -1,600 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * mpc8572ds board configuration file
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#include "../board/freescale/common/ics307_clk.h"
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-#endif
-
-/* High Level Configuration Options */
-
-#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
-#define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
-#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk() /* ddrclk for MPC85xx */
-#define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE			/* toggle L2 cache */
-#define CONFIG_BTB			/* toggle branch predition */
-
-#define CONFIG_ENABLE_36BIT_PHYS	1
-
-/*
- * Config the L2 Cache as L2 SRAM
- */
-#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS		0xff8f80000ull
-#else
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS		CONFIG_SYS_INIT_L2_ADDR
-#endif
-#define CONFIG_SYS_L2_SIZE		(512 << 10)
-#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR		0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
-
-#if defined(CONFIG_NAND_SPL)
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	2
-
-/* I2C addresses of SPD EEPROMs */
-#define CONFIG_SYS_SPD_BUS_NUM		1	/* SPD EEPROMS locate on I2C bus 1 */
-#define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
-#define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 1 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD.  */
-#define CONFIG_SYS_SDRAM_SIZE		512		/* DDR is 512MB */
-#define CONFIG_SYS_DDR_CS0_BNDS		0x0000001F
-#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3		0x00020000
-#define CONFIG_SYS_DDR_TIMING_0		0x00260802
-#define CONFIG_SYS_DDR_TIMING_1		0x626b2634
-#define CONFIG_SYS_DDR_TIMING_2		0x062874cf
-#define CONFIG_SYS_DDR_MODE_1		0x00440462
-#define CONFIG_SYS_DDR_MODE_2		0x00000000
-#define CONFIG_SYS_DDR_INTERVAL		0x0c300100
-#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL		0x00800000
-#define CONFIG_SYS_DDR_OCD_CTRL		0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0xc3000008	/* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2		0x24400000
-
-#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
-#define CONFIG_SYS_DDR_SBE		0x00010000
-
-/*
- * Make sure required options are set
- */
-#ifndef CONFIG_SPD_EEPROM
-#error ("CONFIG_SPD_EEPROM is required")
-#endif
-
-/*
- * Memory map
- *
- * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
- * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
- * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
- * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
- *
- * Localbus cacheable (TBD)
- * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
- *
- * Localbus non-cacheable
- * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
- * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
- * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
- * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
- * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
- * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_FLASH_BR_PRELIM \
-	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
-#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
-
-#define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
-
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
-
-#undef CONFIG_SYS_RAMBOOT
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-
-#define CONFIG_HWCONFIG			/* enable hwconfig */
-#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
-#define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
-#ifdef CONFIG_PHYS_64BIT
-#define PIXIS_BASE_PHYS	0xfffdf0000ull
-#else
-#define PIXIS_BASE_PHYS	PIXIS_BASE
-#endif
-
-#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
-
-#define PIXIS_ID		0x0	/* Board ID at offset 0 */
-#define PIXIS_VER		0x1	/* Board version at offset 1 */
-#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
-#define PIXIS_CSR   		0x3	/* PIXIS General control/status register */
-#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
-#define PIXIS_PWR		0x5	/* PIXIS Power status register */
-#define PIXIS_AUX		0x6	/* Auxiliary 1 register */
-#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
-#define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
-#define PIXIS_VCTL		0x10	/* VELA Control Register */
-#define PIXIS_VSTAT		0x11	/* VELA Status Register */
-#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
-#define PIXIS_VCORE0	 	0x14	/* VELA VCORE0 Register */
-#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
-#define PIXIS_VBOOT_LBMAP	0xc0	/* VBOOT - CFG_LBMAP */
-#define PIXIS_VBOOT_LBMAP_NOR0	0x00	/* cfg_lbmap - boot from NOR 0 */
-#define PIXIS_VBOOT_LBMAP_PJET	0x01	/* cfg_lbmap - boot from projet */
-#define PIXIS_VBOOT_LBMAP_NAND	0x02	/* cfg_lbmap - boot from NAND */
-#define PIXIS_VBOOT_LBMAP_NOR1	0x03	/* cfg_lbmap - boot from NOR 1 */
-#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
-#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
-#define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
-#define PIXIS_VSYSCLK0		0x1C	/* VELA SYSCLK0 Register */
-#define PIXIS_VSYSCLK1		0x1D	/* VELA SYSCLK1 Register */
-#define PIXIS_VSYSCLK2		0x1E	/* VELA SYSCLK2 Register */
-#define PIXIS_VDDRCLK0		0x1F	/* VELA DDRCLK0 Register */
-#define PIXIS_VDDRCLK1		0x20	/* VELA DDRCLK1 Register */
-#define PIXIS_VDDRCLK2		0x21	/* VELA DDRCLK2 Register */
-#define PIXIS_VWATCH		0x24    /* Watchdog Register */
-#define PIXIS_LED		0x25    /* LED Register */
-
-#define PIXIS_SPD_SYSCLK_MASK		0x7		/* SYSCLK option */
-
-/* old pixis referenced names */
-#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
-#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK	0xc0
-#define PIXIS_VSPEED2_TSEC1SER	0x8
-#define PIXIS_VSPEED2_TSEC2SER	0x4
-#define PIXIS_VSPEED2_TSEC3SER	0x2
-#define PIXIS_VSPEED2_TSEC4SER	0x1
-#define PIXIS_VCFGEN1_TSEC1SER	0x20
-#define PIXIS_VCFGEN1_TSEC2SER	0x20
-#define PIXIS_VCFGEN1_TSEC3SER	0x20
-#define PIXIS_VCFGEN1_TSEC4SER	0x20
-#define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER \
-					| PIXIS_VSPEED2_TSEC2SER \
-					| PIXIS_VSPEED2_TSEC3SER \
-					| PIXIS_VSPEED2_TSEC4SER)
-#define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER \
-					| PIXIS_VCFGEN1_TSEC2SER \
-					| PIXIS_VCFGEN1_TSEC3SER \
-					| PIXIS_VCFGEN1_TSEC4SER)
-
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000	/* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
-
-#ifndef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE		0xffa00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
-#endif
-#else
-#define CONFIG_SYS_NAND_BASE		0xfff00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS	0xffff00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
-#endif
-#endif
-
-#define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
-				CONFIG_SYS_NAND_BASE + 0x40000, \
-				CONFIG_SYS_NAND_BASE + 0x80000,\
-				CONFIG_SYS_NAND_BASE + 0xC0000}
-#define CONFIG_SYS_MAX_NAND_DEVICE    4
-#define CONFIG_NAND_FSL_ELBC	1
-#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
-#define CONFIG_SYS_NAND_MAX_OOBFREE	5
-#define CONFIG_SYS_NAND_MAX_ECCPOS	56
-
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
-#define CONFIG_SYS_NAND_U_BOOT_START \
-		(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
-			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
-			       | BR_PS_8	       /* Port Size = 8 bit */ \
-			       | BR_MS_FCM	       /* MSEL = FCM */ \
-			       | BR_V)		       /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
-			       | OR_FCM_PGS	       /* Large Page*/ \
-			       | OR_FCM_CSCT \
-			       | OR_FCM_CST \
-			       | OR_FCM_CHT \
-			       | OR_FCM_SCY_1 \
-			       | OR_FCM_TRLX \
-			       | OR_FCM_EHTR)
-
-#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */
-#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
-			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
-			       | BR_PS_8	       /* Port Size = 8 bit */ \
-			       | BR_MS_FCM	       /* MSEL = FCM */ \
-			       | BR_V)		       /* valid */
-#define CONFIG_SYS_OR4_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
-			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
-			       | BR_PS_8	       /* Port Size = 8 bit */ \
-			       | BR_MS_FCM	       /* MSEL = FCM */ \
-			       | BR_V)		       /* valid */
-#define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
-			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
-			       | BR_PS_8	       /* Port Size = 8 bit */ \
-			       | BR_MS_FCM	       /* MSEL = FCM */ \
-			       | BR_V)		       /* valid */
-#define CONFIG_SYS_OR6_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM	1
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 3, direct to uli, tgtid 3, Base address 8000 */
-#define CONFIG_SYS_PCIE3_NAME		"ULI"
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
-#define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc00000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME		"Slot 2"
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
-#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-
-#if defined(CONFIG_PCI)
-
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE1_IO_VIRT
-
-/* video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#endif
-
-
-#ifndef CONFIG_PCI_PNP
-	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCIE3_IO_BUS
-	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCIE3_IO_BUS
-	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
-#define CONFIG_SYS_SCSI_MAX_LUN	1
-#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif /* SCSI */
-
-#endif	/* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
-#define CONFIG_TSEC1	1
-#define CONFIG_TSEC1_NAME	"eTSEC1"
-#define CONFIG_TSEC2	1
-#define CONFIG_TSEC2_NAME	"eTSEC2"
-#define CONFIG_TSEC3	1
-#define CONFIG_TSEC3_NAME	"eTSEC3"
-#define CONFIG_TSEC4	1
-#define CONFIG_TSEC4_NAME	"eTSEC4"
-
-#define CONFIG_PIXIS_SGMII_CMD
-#define CONFIG_FSL_SGMII_RISER	1
-#define SGMII_RISER_PHY_OFFSET	0x1c
-
-#ifdef CONFIG_FSL_SGMII_RISER
-#define CONFIG_SYS_TBIPA_VALUE		0x10 /* avoid conflict with eTSEC4 paddr */
-#endif
-
-#define TSEC1_PHY_ADDR		0
-#define TSEC2_PHY_ADDR		1
-#define TSEC3_PHY_ADDR		2
-#define TSEC4_PHY_ADDR		3
-
-#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX		0
-#define TSEC2_PHYIDX		0
-#define TSEC3_PHYIDX		0
-#define TSEC4_PHYIDX		0
-
-#define CONFIG_ETHPRIME		"eTSEC1"
-#endif	/* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * USB
- */
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_PCI_EHCI_DEVICE			0
-#endif
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#endif
-
-#define CONFIG_IPADDR		192.168.1.254
-
-#define CONFIG_HOSTNAME		"unknown"
-#define CONFIG_ROOTPATH		"/opt/nfsroot"
-#define CONFIG_BOOTFILE		"uImage"
-#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
-
-#define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_GATEWAYIP	192.168.1.1
-#define CONFIG_NETMASK		255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		1000000
-
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0"		\
-"netdev=eth0\0"						\
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"				\
-"tftpflash=tftpboot $loadaddr $uboot; "			\
-	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" +$filesize; "	\
-	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
-		" +$filesize; "	\
-	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" $filesize; "	\
-	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
-		" +$filesize; "	\
-	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" $filesize\0"	\
-"consoledev=ttyS0\0"				\
-"ramdiskaddr=2000000\0"			\
-"ramdiskfile=8572ds/ramdisk.uboot\0"		\
-"fdtaddr=1e00000\0"				\
-"fdtfile=8572ds/mpc8572ds.dtb\0"		\
-"bdev=sda3\0"
-
-#define CONFIG_HDBOOT				\
- "setenv bootargs root=/dev/$bdev rw "		\
- "console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $loadaddr $bootfile;"			\
- "tftp $fdtaddr $fdtfile;"			\
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND		\
- "setenv bootargs root=/dev/nfs rw "	\
- "nfsroot=$serverip:$rootpath "		\
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $loadaddr $bootfile;"		\
- "tftp $fdtaddr $fdtfile;"		\
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND		\
- "setenv bootargs root=/dev/ram rw "	\
- "console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $ramdiskaddr $ramdiskfile;"	\
- "tftp $loadaddr $bootfile;"		\
- "tftp $fdtaddr $fdtfile;"		\
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
deleted file mode 100644
index f444be0d86..0000000000
--- a/include/configs/MPC8610HPCD.h
+++ /dev/null
@@ -1,559 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * MPC8610HPCD board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/* High Level Configuration Options */
-#define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
-
-/* video */
-#define CONFIG_FSL_DIU_FB
-
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x2c000)
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#endif
-
-#ifdef RUN_DIAG
-#define CONFIG_SYS_DIAG_ADDR		0xff800000
-#endif
-
-/*
- * virtual address to be used for temporary mappings.  There
- * should be 128k free at this VA.
- */
-#define CONFIG_SYS_SCRATCH_VA	0xc0000000
-
-#define CONFIG_PCI1		1	/* PCI controller 1 */
-#define CONFIG_PCIE1		1	/* PCIe 1 connected to ULI bridge */
-#define CONFIG_PCIE2		1	/* PCIe 2 connected to slot */
-#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-
-#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
-
-#define CONFIG_BAT_RW		1	/* Use common BAT rw code */
-#define CONFIG_ALTIVEC		1
-
-/*
- * L2CR setup -- make sure this is right for your board!
- */
-#define CONFIG_SYS_L2
-#define L2_INIT		0
-#define L2_ENABLE	(L2CR_L2E |0x00100000 )
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
-#endif
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
-#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
-
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
-#define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR_PHYS_LOW
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM		/* Use SPD for DDR */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD.  */
-#define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
-
-#if 0 /* TODO */
-#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
-#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-#define CONFIG_SYS_DDR_TIMING_0	0x00260802
-#define CONFIG_SYS_DDR_TIMING_1	0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1		0x00480432
-#define CONFIG_SYS_DDR_MODE_2		0x00000000
-#define CONFIG_SYS_DDR_INTERVAL	0x06180100
-#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2	0x04400010
-
-#define CONFIG_SYS_DDR_ERR_INT_EN	0x00000000
-#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
-#define CONFIG_SYS_DDR_SBE		0x000f0000
-
-#endif
-
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-#define CONFIG_SYS_FLASH_BASE		0xf0000000 /* start of FLASH 128M */
-#define CONFIG_SYS_FLASH_BASE2		0xf8000000
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
-
-#define CONFIG_SYS_BR0_PRELIM		0xf8001001 /* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM		0xf8006e65 /* 128MB NOR Flash*/
-
-#define CONFIG_SYS_BR1_PRELIM		0xf0001001 /* port size 16bit */
-#define CONFIG_SYS_OR1_PRELIM		0xf8006e65 /* 128MB Promjet */
-#if 0 /* TODO */
-#define CONFIG_SYS_BR2_PRELIM		0xf0000000
-#define CONFIG_SYS_OR2_PRELIM		0xf0000000 /* 256MB NAND Flash - bank 1 */
-#endif
-#define CONFIG_SYS_BR3_PRELIM		0xe8000801 /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM		0xfff06ff7 /* 1MB PIXIS area*/
-
-#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
-#define PIXIS_BASE	0xe8000000	/* PIXIS registers */
-#define PIXIS_ID		0x0	/* Board ID at offset 0 */
-#define PIXIS_VER		0x1	/* Board version at offset 1 */
-#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
-#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
-#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch */
-#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
-#define PIXIS_BRDCFG0		0x8	/* PIXIS Board Configuration Register0*/
-#define PIXIS_VCTL		0x10	/* VELA Control Register */
-#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
-#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
-#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
-#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
-#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
-#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK	0xC0    /* Reset altbank mask */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
-
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef	CONFIG_SYS_RAMBOOT
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_SPD_EEPROM
-#define CONFIG_SYS_SDRAM_SIZE	256
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#ifndef CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR	0xe4000000	/* Initial RAM address */
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
-#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
-
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE	8192
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_VIRT	CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_IO_BUS	0x0000000
-#define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
-#define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
-#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
-
-/* controller 1, Base address 0xa000 */
-#define CONFIG_SYS_PCIE1_NAME		"ULI"
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/* 1M */
-
-/* controller 2, Base Address 0x9000 */
-#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
-#define CONFIG_SYS_PCIE2_MEM_BUS	0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000	/* reuse mem LAW */
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xe2000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00100000	/* 1M */
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#define CONFIG_ULI526X
-
-/************************************************************
- * USB support
- ************************************************************/
-#define CONFIG_PCI_OHCI		1
-#define CONFIG_USB_OHCI_NEW		1
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ohci_pci"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
-
-#if !defined(CONFIG_PCI_PNP)
-#define PCI_ENET0_IOADDR	0xe0000000
-#define PCI_ENET0_MEMADDR	0xe0000000
-#define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
-#endif
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
-#define CONFIG_SYS_SCSI_MAX_LUN	1
-#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
-#endif	/* CONFIG_PCI */
-
-/*
- * BAT0		2G	Cacheable, non-guarded
- * 0x0000_0000	2G	DDR
- */
-#define CONFIG_SYS_DBAT0L	(BATL_PP_RW)
-#define CONFIG_SYS_IBAT0L	(BATL_PP_RW)
-
-/*
- * BAT1		1G	Cache-inhibited, guarded
- * 0x8000_0000	256M	PCI-1 Memory
- * 0xa000_0000	256M	PCI-Express 1 Memory
- * 0x9000_0000	256M	PCI-Express 2 Memory
- */
-
-#define CONFIG_SYS_DBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
-
-/*
- * BAT2		16M	Cache-inhibited, guarded
- * 0xe100_0000	1M	PCI-1 I/O
- */
-
-#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
-
-/*
- * BAT3		4M	Cache-inhibited, guarded
- * 0xe000_0000	4M	CCSR
- */
-
-#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
-
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
-				       | BATL_PP_RW | BATL_CACHEINHIBIT \
-				       | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
-				       | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
-				       | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
-#endif
-
-/*
- * BAT4		32M	Cache-inhibited, guarded
- * 0xe200_0000	1M	PCI-Express 2 I/O
- * 0xe300_0000	1M	PCI-Express 1 I/O
- */
-
-#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
-
-/*
- * BAT5		128K	Cacheable, non-guarded
- * 0xe400_0000	128K	Init RAM for stack in the CPU DCache (no backing memory)
- */
-#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
-#define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
-
-/*
- * BAT6		256M	Cache-inhibited, guarded
- * 0xf000_0000	256M	FLASH
- */
-#define CONFIG_SYS_DBAT6L	(CONFIG_SYS_FLASH_BASE	 | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE	 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
-
-/* Map the last 1M of flash where we're running from reset */
-#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
-				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
-				 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
-
-/*
- * BAT7		4M	Cache-inhibited, guarded
- * 0xe800_0000	4M	PIXIS
- */
-#define CONFIG_SYS_DBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT7U	(PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT7U	CONFIG_SYS_DBAT7U
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_WATCHDOG			/* watchdog enabled */
-#define CONFIG_SYS_WATCHDOG_FREQ	5000	/* Feed interval, 5s */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(256 << 20)	/* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_IPADDR		192.168.1.100
-
-#define CONFIG_HOSTNAME		"unknown"
-#define CONFIG_ROOTPATH		"/opt/nfsroot"
-#define CONFIG_BOOTFILE		"uImage"
-#define CONFIG_UBOOTPATH	8610hpcd/u-boot.bin
-
-#define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_GATEWAYIP	192.168.1.1
-#define CONFIG_NETMASK		255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		0x10000000
-
-#if defined(CONFIG_PCI1)
-#define PCI_ENV \
- "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
-	"echo e;md ${a}e00 9\0" \
- "pci1regs=setenv a e0008; run pcireg\0" \
- "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
-	"pci d.w $b.0 56 1\0" \
- "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
-	"pci w.w $b.0 56 ffff\0"	\
- "pci1err=setenv a e0008; run pcierr\0"	\
- "pci1errc=setenv a e0008; run pcierrc\0"
-#else
-#define	PCI_ENV ""
-#endif
-
-#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
-#define PCIE_ENV \
- "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
-	"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
- "pcie1regs=setenv a e000a; run pciereg\0"	\
- "pcie2regs=setenv a e0009; run pciereg\0"	\
- "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
-	"pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;"	\
-	"pci d $b.0 130 1\0" \
- "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
-	"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
-	"pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0"		\
- "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"	\
- "pcie1err=setenv a e000a; run pcieerr\0"	\
- "pcie2err=setenv a e0009; run pcieerr\0"	\
- "pcie1errc=setenv a e000a; run pcieerrc\0"	\
- "pcie2errc=setenv a e0009; run pcieerrc\0"
-#else
-#define	PCIE_ENV ""
-#endif
-
-#define DMA_ENV \
- "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
-	"mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
- "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
-	"mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
- "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
-	"mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
- "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
-	"mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
-
-#ifdef ENV_DEBUG
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-"netdev=eth0\0"							\
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
-"tftpflash=tftpboot $loadaddr $uboot; "				\
-	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" +$filesize; "	\
-	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
-		" +$filesize; "	\
-	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" $filesize; "	\
-	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
-		" +$filesize; "	\
-	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" $filesize\0"	\
-"consoledev=ttyS0\0"						\
-"ramdiskaddr=0x18000000\0"					\
-"ramdiskfile=8610hpcd/ramdisk.uboot\0"				\
-"fdtaddr=0x17c00000\0"						\
-"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"				\
-"bdev=sda3\0"					\
-"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
-"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
-"maxcpus=1"	\
-"eoi=mw e00400b0 0\0"						\
-"iack=md e00400a0 1\0"						\
-"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
-	"md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
-	"md ${a}f00 5\0" \
-"ddr1regs=setenv a e0002; run ddrreg\0" \
-"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
-	"md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
-	"md ${a}e60 1; md ${a}ef0 1d\0" \
-"guregs=setenv a e00e0; run gureg\0" \
-"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
-"mcmregs=setenv a e0001; run mcmreg\0" \
-"diuregs=md e002c000 1d\0" \
-"dium=mw e002c01c\0" \
-"diuerr=md e002c014 1\0" \
-"pmregs=md e00e1000 2b\0" \
-"lawregs=md e0000c08 4b\0" \
-"lbcregs=md e0005000 36\0" \
-"dma0regs=md e0021100 12\0" \
-"dma1regs=md e0021180 12\0" \
-"dma2regs=md e0021200 12\0" \
-"dma3regs=md e0021280 12\0" \
- PCI_ENV \
- PCIE_ENV \
- DMA_ENV
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-	"netdev=eth0\0"						\
-	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
-	"consoledev=ttyS0\0"					\
-	"ramdiskaddr=0x18000000\0"				\
-	"ramdiskfile=8610hpcd/ramdisk.uboot\0"			\
-	"fdtaddr=0x17c00000\0"					\
-	"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"			\
-	"bdev=sda3\0"
-#endif
-
-#define CONFIG_NFSBOOTCOMMAND					\
- "setenv bootargs root=/dev/nfs rw "				\
-	"nfsroot=$serverip:$rootpath "				\
-	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-	"console=$consoledev,$baudrate $othbootargs;"		\
- "tftp $loadaddr $bootfile;"					\
- "tftp $fdtaddr $fdtfile;"					\
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw "				\
-	"console=$consoledev,$baudrate $othbootargs;"		\
- "tftp $ramdiskaddr $ramdiskfile;"				\
- "tftp $loadaddr $bootfile;"					\
- "tftp $fdtaddr $fdtfile;"					\
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND		\
- "setenv bootargs root=/dev/$bdev rw "	\
-	"console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $loadaddr $bootfile;"		\
- "tftp $fdtaddr $fdtfile;"		\
- "bootm $loadaddr - $fdtaddr"
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
deleted file mode 100644
index e6e1e7943c..0000000000
--- a/include/configs/MPC8641HPCN.h
+++ /dev/null
@@ -1,632 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2006, 2010-2011 Freescale Semiconductor.
- *
- * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
- */
-
-/*
- * MPC8641HPCN board configuration file
- *
- * Make sure you change the MAC address and other network params first,
- * search for CONFIG_SERVERIP, etc. in this file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/* High Level Configuration Options */
-#define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
-
-/*
- * default CCSRBAR is at 0xff700000
- * assume U-Boot is less than 0.5MB
- */
-
-#ifdef RUN_DIAG
-#define CONFIG_SYS_DIAG_ADDR	     CONFIG_SYS_FLASH_BASE
-#endif
-
-/*
- * virtual address to be used for temporary mappings.  There
- * should be 128k free at this VA.
- */
-#define CONFIG_SYS_SCRATCH_VA	0xe0000000
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-
-#define CONFIG_PCIE1		1	/* PCIE controller 1 (ULI bridge) */
-#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot) */
-#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-
-#define CONFIG_BAT_RW		1	/* Use common BAT rw code */
-
-#define CONFIG_ALTIVEC		1
-
-/*
- * L2CR setup -- make sure this is right for your board!
- */
-#define CONFIG_SYS_L2
-#define L2_INIT		0
-#define L2_ENABLE	(L2CR_L2E)
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifndef __ASSEMBLY__
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
-#endif
-
-/*
- * With the exception of PCI Memory and Rapid IO, most devices will simply
- * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
- * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
- */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
-#else
-#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
-#endif
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
-#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
-
-/* Physical addresses */
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	CONFIG_SYS_PHYS_ADDR_HIGH
-#define CONFIG_SYS_CCSRBAR_PHYS \
-	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
-			    CONFIG_SYS_CCSRBAR_PHYS_HIGH)
-
-#define CONFIG_HWCONFIG	/* use hwconfig to control memory interleaving */
-
-/*
- * DDR Setup
- */
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	2
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/*
- * I2C addresses of SPD EEPROMs
- */
-#define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
-#define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 0 DIMM 1 */
-#define SPD_EEPROM_ADDRESS3	0x53	/* CTLR 1 DIMM 0 */
-#define SPD_EEPROM_ADDRESS4	0x54	/* CTLR 1 DIMM 1 */
-
-/*
- * These are used when DDR doesn't use SPD.
- */
-#define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
-#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
-#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102      /* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-#define CONFIG_SYS_DDR_TIMING_0	0x00260802
-#define CONFIG_SYS_DDR_TIMING_1	0x39357322
-#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1		0x00480432
-#define CONFIG_SYS_DDR_MODE_2		0x00000000
-#define CONFIG_SYS_DDR_INTERVAL	0x06090100
-#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2	0x04400000
-
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-#define CONFIG_SYS_FLASH_BASE		0xef800000     /* start of FLASH 8M */
-#define CONFIG_SYS_FLASH_BASE_PHYS_LOW	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_FLASH_BASE_PHYS \
-	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
-			    CONFIG_SYS_PHYS_ADDR_HIGH)
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_SYS_BR0_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
-				 | 0x00001001)	/* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM	0xff806ff7	/* 8MB Boot Flash area*/
-
-#define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(CF_BASE_PHYS)		\
-				 | 0x00001001)	/* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM	0xffffeff7	/* 32k Compact Flash */
-
-#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS)	\
-				 | 0x00000801) /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32k PIXIS area*/
-
-/*
- * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
- * The PIXIS and CF by themselves aren't large enough to take up the 128k
- * required for the smallest BAT mapping, so there's a 64k hole.
- */
-#define CONFIG_SYS_LBC_BASE		0xffde0000
-#define CONFIG_SYS_LBC_BASE_PHYS_LOW	CONFIG_SYS_LBC_BASE
-
-#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
-#define PIXIS_BASE		(CONFIG_SYS_LBC_BASE + 0x00010000)
-#define PIXIS_BASE_PHYS_LOW	(CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
-#define PIXIS_BASE_PHYS		PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
-						    CONFIG_SYS_PHYS_ADDR_HIGH)
-#define PIXIS_SIZE		0x00008000	/* 32k */
-#define PIXIS_ID		0x0	/* Board ID at offset 0 */
-#define PIXIS_VER		0x1	/* Board version at offset 1 */
-#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
-#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
-#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch register */
-#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
-#define PIXIS_VCTL		0x10	/* VELA Control Register */
-#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
-#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
-#define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
-#define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
-#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
-#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
-#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
-#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40	/* Reset altbank mask*/
-
-/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
-#define CF_BASE			(PIXIS_BASE + PIXIS_SIZE)
-#define CF_BASE_PHYS		(PIXIS_BASE_PHYS + PIXIS_SIZE)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
-
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
-#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef	CONFIG_SYS_RAMBOOT
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_SPD_EEPROM
-#define CONFIG_SYS_SDRAM_SIZE	256
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#ifndef CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	 /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
-
-/*
- * RapidIO MMU
- */
-#define CONFIG_SYS_SRIO1_MEM_BASE	0x80000000	/* base address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	0x00000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
-#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	CONFIG_SYS_SRIO1_MEM_BASE
-#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
-#endif
-#define CONFIG_SYS_SRIO1_MEM_PHYS \
-	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
-			    CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
-#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-
-#define CONFIG_SYS_PCIE1_NAME		"ULI"
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	0x00000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x0000000c
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS	CONFIG_SYS_PCIE1_MEM_VIRT
-#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	CONFIG_SYS_PCIE1_MEM_VIRT
-#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x00000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_PHYS \
-	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
-			    CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
-#define CONFIG_SYS_PCIE1_IO_PHYS_LOW	CONFIG_SYS_PCIE1_IO_VIRT
-#define CONFIG_SYS_PCIE1_IO_PHYS \
-	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
-			    CONFIG_SYS_PHYS_ADDR_HIGH)
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64K */
-
-#ifdef CONFIG_PHYS_64BIT
-/*
- * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
- * This will increase the amount of PCI address space available for
- * for mapping RAM.
- */
-#define CONFIG_SYS_PCIE2_MEM_BUS	CONFIG_SYS_PCIE1_MEM_BUS
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS	(CONFIG_SYS_PCIE1_MEM_BUS \
-					 + CONFIG_SYS_PCIE1_MEM_SIZE)
-#endif
-#define CONFIG_SYS_PCIE2_MEM_VIRT 	(CONFIG_SYS_PCIE1_MEM_VIRT \
-					 + CONFIG_SYS_PCIE1_MEM_SIZE)
-#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW	(CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
-					 + CONFIG_SYS_PCIE1_MEM_SIZE)
-#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH	CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
-#define CONFIG_SYS_PCIE2_MEM_PHYS	(CONFIG_SYS_PCIE1_MEM_PHYS \
-					 + CONFIG_SYS_PCIE1_MEM_SIZE)
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_VIRT 	(CONFIG_SYS_PCIE1_IO_VIRT \
-					 + CONFIG_SYS_PCIE1_IO_SIZE)
-#define CONFIG_SYS_PCIE2_IO_PHYS_LOW	(CONFIG_SYS_PCIE1_IO_PHYS_LOW \
-					 + CONFIG_SYS_PCIE1_IO_SIZE)
-#define CONFIG_SYS_PCIE2_IO_PHYS	(CONFIG_SYS_PCIE1_IO_PHYS \
-					 + CONFIG_SYS_PCIE1_IO_SIZE)
-#define CONFIG_SYS_PCIE2_IO_SIZE	CONFIG_SYS_PCIE1_IO_SIZE
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-
-/************************************************************
- * USB support
- ************************************************************/
-#define CONFIG_PCI_OHCI			1
-#define CONFIG_USB_OHCI_NEW		1
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
-
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
-
-/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCIE1_IO_VIRT*/
-
-/* video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
-#define CONFIG_SYS_SCSI_MAX_LUN	1
-#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
-#endif	/* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_TSEC1		1
-#define CONFIG_TSEC1_NAME	"eTSEC1"
-#define CONFIG_TSEC2		1
-#define CONFIG_TSEC2_NAME	"eTSEC2"
-#define CONFIG_TSEC3		1
-#define CONFIG_TSEC3_NAME	"eTSEC3"
-#define CONFIG_TSEC4		1
-#define CONFIG_TSEC4_NAME	"eTSEC4"
-
-#define TSEC1_PHY_ADDR		0
-#define TSEC2_PHY_ADDR		1
-#define TSEC3_PHY_ADDR		2
-#define TSEC4_PHY_ADDR		3
-#define TSEC1_PHYIDX		0
-#define TSEC2_PHYIDX		0
-#define TSEC3_PHYIDX		0
-#define TSEC4_PHYIDX		0
-#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-
-#define CONFIG_ETHPRIME		"eTSEC1"
-
-#endif	/* CONFIG_TSEC_ENET */
-
-#ifdef CONFIG_PHYS_64BIT
-#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
-#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
-
-/* Put physical address into the BAT format */
-#define BAT_PHYS_ADDR(low, high) \
-	(low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
-/* Convert high/low pairs to actual 64-bit value */
-#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
-#else
-/* 32-bit systems just ignore the "high" bits */
-#define BAT_PHYS_ADDR(low, high)        (low)
-#define PAIRED_PHYS_TO_PHYS(low, high)  (low)
-#endif
-
-/*
- * BAT0		DDR
- */
-#define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
-
-/*
- * BAT1		LBC (PIXIS/CF)
- */
-#define CONFIG_SYS_DBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
-					       CONFIG_SYS_PHYS_ADDR_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
-				 BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_LBC_BASE | BATU_BL_128K \
-				 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
-					       CONFIG_SYS_PHYS_ADDR_HIGH) \
-				 | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
-
-/* if CONFIG_PCI:
- * BAT2		PCIE1 and PCIE1 MEM
- * if CONFIG_RIO
- * BAT2		Rapidio Memory
- */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
-					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT \
-				 | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
-				 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
-					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
-#else /* CONFIG_RIO */
-#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
-					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
-				 BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
-				 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
-					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
-#endif
-
-/*
- * BAT3		CCSR Space
- */
-#define CONFIG_SYS_DBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
-					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT \
-				 | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
-				 | BATU_VP)
-#define CONFIG_SYS_IBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
-					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
-
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
-				       | BATL_PP_RW | BATL_CACHEINHIBIT \
-				       | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
-				       | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
-				       | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
-#endif
-
-/*
- * BAT4		PCIE1_IO and PCIE2_IO
- */
-#define CONFIG_SYS_DBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
-					       CONFIG_SYS_PHYS_ADDR_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT \
-				 | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
-				 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
-					       CONFIG_SYS_PHYS_ADDR_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
-
-/*
- * BAT5		Init RAM for stack in the CPU DCache (no backing memory)
- */
-#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
-#define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
-
-/*
- * BAT6		FLASH
- */
-#define CONFIG_SYS_DBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
-					       CONFIG_SYS_PHYS_ADDR_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT \
-				 | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
-				 | BATU_VP)
-#define CONFIG_SYS_IBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
-					       CONFIG_SYS_PHYS_ADDR_HIGH) \
-				 | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
-
-/* Map the last 1M of flash where we're running from reset */
-#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
-				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
-				 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
-
-/*
- * BAT7		FREE - used later for tmp mappings
- */
-#define CONFIG_SYS_DBAT7L 0x00000000
-#define CONFIG_SYS_DBAT7U 0x00000000
-#define CONFIG_SYS_IBAT7L 0x00000000
-#define CONFIG_SYS_IBAT7U 0x00000000
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(256 << 20)	/* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-    #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_HAS_ETH0		1
-#define CONFIG_HAS_ETH1		1
-#define CONFIG_HAS_ETH2		1
-#define CONFIG_HAS_ETH3		1
-
-#define CONFIG_IPADDR		192.168.1.100
-
-#define CONFIG_HOSTNAME		"unknown"
-#define CONFIG_ROOTPATH		"/opt/nfsroot"
-#define CONFIG_BOOTFILE		"uImage"
-#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
-
-#define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_GATEWAYIP	192.168.1.1
-#define CONFIG_NETMASK		255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		0x10000000
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
-	"tftpflash=tftpboot $loadaddr $uboot; "				\
-		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" +$filesize; "	\
-		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
-			" +$filesize; "	\
-		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" $filesize; "	\
-		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
-			" +$filesize; "	\
-		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" $filesize\0"	\
-	"consoledev=ttyS0\0"						\
-	"ramdiskaddr=0x18000000\0"						\
-	"ramdiskfile=your.ramdisk.u-boot\0"				\
-	"fdtaddr=0x17c00000\0"						\
-	"fdtfile=mpc8641_hpcn.dtb\0"					\
-	"en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"			\
-	"dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
-	"maxcpus=2"
-
-#define CONFIG_NFSBOOTCOMMAND						\
-	"setenv bootargs root=/dev/nfs rw "				\
-	      "nfsroot=$serverip:$rootpath "				\
-	      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-	      "console=$consoledev,$baudrate $othbootargs;"		\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND						\
-	"setenv bootargs root=/dev/ram rw "				\
-	      "console=$consoledev,$baudrate $othbootargs;"		\
-	"tftp $ramdiskaddr $ramdiskfile;"				\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
deleted file mode 100644
index 026ffbeb6c..0000000000
--- a/include/configs/MigoR.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas Solutions Migo-R board
- *
- * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#ifndef __MIGO_R_H
-#define __MIGO_R_H
-
-#define CONFIG_CPU_SH7722	1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* SMC9111 */
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE    (0xB0000000)
-
-/* MEMORY */
-#define MIGO_R_SDRAM_BASE	(0x8C000000)
-#define MIGO_R_FLASH_BASE_1	(0xA0000000)
-#define MIGO_R_FLASH_BANK_SIZE	(64 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE		256		/* Buffer size for Console output */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
-
-/* SCIF */
-#define CONFIG_CONS_SCIF0	1
-
-/* Enable alternate, more extensive, memory test */
-/* Scratch address used by the alternate memory test */
-
-/* Enable temporary baudrate change while serial download */
-#undef  CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_SDRAM_BASE	(MIGO_R_SDRAM_BASE)
-/* maybe more, but if so u-boot doesn't know about it... */
-#define CONFIG_SYS_SDRAM_SIZE	(64 * 1024 * 1024)
-/* default load address for scripts ?!? */
-#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
-
-/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
-#define CONFIG_SYS_MONITOR_BASE	(MIGO_R_FLASH_BASE_1)
-/* Monitor size */
-#define CONFIG_SYS_MONITOR_LEN	(128 * 1024)
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
-
-/* FLASH */
-#undef  CONFIG_SYS_FLASH_QUIET_TEST
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-/* Physical start address of Flash memory */
-#define CONFIG_SYS_FLASH_BASE	(MIGO_R_FLASH_BASE_1)
-/* Max number of sectors on each Flash chip */
-#define CONFIG_SYS_MAX_FLASH_SECT	512
-
-/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
-
-/* Timeout for Flash erase operations (in ms) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
-/* Timeout for Flash write operations (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
-/* Timeout for Flash set sector lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
-/* Timeout for Flash clear lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
-
-/* Use hardware flash sectors protection instead of U-Boot software protection */
-#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
-
-/* ENV setting */
-/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ	33333333
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-#endif	/* __MIGO_R_H */
diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h
deleted file mode 100644
index bcd55bb868..0000000000
--- a/include/configs/apx4devkit.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Bluegiga Technologies Oy
- *
- * Authors:
- * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
- * Lauri Hintsala <lauri.hintsala@bluegiga.com>
- *
- * Based on m28evk.h:
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- */
-#ifndef __CONFIGS_APX4DEVKIT_H__
-#define __CONFIGS_APX4DEVKIT_H__
-
-/* System configurations */
-#define CONFIG_MACH_TYPE	MACH_TYPE_APX4DEVKIT
-
-/* Memory configuration */
-#define PHYS_SDRAM_1			0x40000000	/* Base address */
-#define PHYS_SDRAM_1_SIZE		0x20000000	/* Max 512 MB RAM */
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-
-/* Environment is in NAND */
-#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_ENV_RANGE		(384 * 1024)
-#endif
-
-/* UBI and NAND partitioning */
-
-/* FEC Ethernet on SoC */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_FEC_MXC
-#define CONFIG_ETHPRIME			"FEC"
-#define CONFIG_FEC_MXC_PHYADDR		0
-#define IMX_FEC_BASE			MXS_ENET0_BASE
-#endif
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_EHCI_MXS_PORT1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
-#endif
-
-/* Boot Linux */
-#define CONFIG_BOOTFILE			"uImage"
-#define CONFIG_BOOTCOMMAND		"run bootcmd_nand"
-#define CONFIG_LOADADDR			0x41000000
-#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
-#define CONFIG_SERIAL_TAG
-#define CONFIG_REVISION_TAG
-
-/* Extra Environments */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
-	"verify=no\0" \
-	"bootcmd=run bootcmd_nand\0" \
-	"kernelargs=console=tty0 console=ttyAMA0,115200 consoleblank=0\0" \
-	"bootargs_nand=" \
-		"setenv bootargs ${kernelargs} ubi.mtd=3,2048 " \
-		"root=ubi0:rootfs rootfstype=ubifs ${mtdparts} rw\0" \
-	"bootcmd_nand=" \
-		"run bootargs_nand && ubi part root 2048 && " \
-		"ubifsmount ubi:rootfs && ubifsload 41000000 boot/uImage && " \
-		"bootm 41000000\0" \
-	"bootargs_mmc=" \
-		"setenv bootargs ${kernelargs} " \
-		"root=/dev/mmcblk0p2 rootwait ${mtdparts} rw\0" \
-	"bootcmd_mmc=" \
-		"run bootargs_mmc && mmc rescan && " \
-		"ext2load mmc 0:2 41000000 boot/uImage && bootm 41000000\0" \
-""
-
-/* The rest of the configuration is shared */
-#include <configs/mxs.h>
-
-#endif /* __CONFIGS_APX4DEVKIT_H__ */
diff --git a/include/configs/db-88f6281-bp.h b/include/configs/db-88f6281-bp.h
deleted file mode 100644
index 06a7091be2..0000000000
--- a/include/configs/db-88f6281-bp.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-
-#ifndef _CONFIG_DB_88F6281_BP_H
-#define _CONFIG_DB_88F6281_BP_H
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
-#define CONFIG_KW88F6281	1	/* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
-#define CONFIG_SYS_TCLK		166666667
-#define CONFIG_SYS_KWD_CONFIG	$(CONFIG_BOARDDIR)/kwbimage.cfg
-
-/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE	0x00000000
-
-#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
-#define CONFIG_KIRKWOOD_PCIE_INIT	/* Enable PCIE Port0 */
-#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
-#define CONFIG_KIRKWOOD_GPIO	1
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
-
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-
-/*
- *  Environment variables configurations
- */
-#define CONFIG_ENV_SPI_BUS		0
-#define CONFIG_ENV_SPI_CS		0
-#define CONFIG_ENV_SPI_MAX_HZ		20000000	/* 20Mhz */
-#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
-
-/*
- * U-Boot bootcode configuration
- */
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for monitor */
-#define CONFIG_SYS_MALLOC_LEN		  (4 << 20)	/* Reserve 4.0 MB for malloc */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
-
-/* size in bytes reserved for initial data */
-
-#include <asm/arch/config.h>
-/* There is no PHY directly connected so don't ask it for link status */
-#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-/*
- * Other required minimal configurations
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
-
-/*
- * SDIO/MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MVEBU_MMC
-#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
-#endif /* CONFIG_CMD_MMC */
-
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
-
-#define CONFIG_SYS_LOAD_ADDR  0x1000000      /* default location for tftp and bootm */
-
-#endif /* _CONFIG_DB_88F6281_BP_H */
diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h
deleted file mode 100644
index 3e0ad48dda..0000000000
--- a/include/configs/ls2080a_emu.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor
- */
-
-#ifndef __LS2_EMU_H
-#define __LS2_EMU_H
-
-#include "ls2080a_common.h"
-
-#define CONFIG_SYS_CLK_FREQ	100000000
-#define CONFIG_DDR_CLK_FREQ	133333333
-
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR_EMU		/* Support emulator */
-#define SPD_EEPROM_ADDRESS1	0x51
-#define SPD_EEPROM_ADDRESS2	0x52
-#define SPD_EEPROM_ADDRESS3	0x53
-#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_SPD_BUS_NUM	1	/* SPD on I2C bus 1 */
-#define CONFIG_DIMM_SLOTS_PER_CTLR		1
-#define CONFIG_CHIP_SELECTS_PER_CTRL		4
-#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
-#endif
-
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
-/*
- * NOR Flash Timing Params
- */
-#define CONFIG_SYS_NOR0_CSPR					\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
-	CSPR_PORT_SIZE_16					| \
-	CSPR_MSEL_NOR						| \
-	CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY				\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
-	CSPR_PORT_SIZE_16					| \
-	CSPR_MSEL_NOR						| \
-	CSPR_V)
-#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
-				FTIM0_NOR_TEADC(0x1) | \
-				FTIM0_NOR_TEAHC(0x1))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
-				FTIM1_NOR_TRAD_NOR(0x1))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
-				FTIM2_NOR_TCH(0x0) | \
-				FTIM2_NOR_TWP(0x1))
-#define CONFIG_SYS_NOR_FTIM3	0x04000000
-#define CONFIG_SYS_IFC_CCR	0x01000000
-
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-
-/* Debug Server firmware */
-#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580C00000ULL
-
-/*
- * This trick allows users to load MC images into DDR directly without
- * copying from NOR flash. It dramatically improves speed.
- */
-#define CONFIG_SYS_LS_MC_FW_IN_DDR
-#define CONFIG_SYS_LS_MC_DPL_IN_DDR
-#define CONFIG_SYS_LS_MC_DPC_IN_DDR
-
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
-
-/* Store environment at top of flash */
-
-#endif /* __LS2_EMU_H */
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
deleted file mode 100644
index ab46df7600..0000000000
--- a/include/configs/ls2080a_simu.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014 Freescale Semiconductor
- */
-
-#ifndef __LS2_SIMU_H
-#define __LS2_SIMU_H
-
-#include "ls2080a_common.h"
-
-#define CONFIG_SYS_CLK_FREQ	100000000
-#define CONFIG_DDR_CLK_FREQ	133333333
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR		1
-#define CONFIG_CHIP_SELECTS_PER_CTRL		4
-#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
-#endif
-
-/* SMSC 91C111 ethernet configuration */
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE	(0x2210000)
-
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
-
-#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#endif
-
-/*
- * NOR Flash Timing Params
- */
-#define CONFIG_SYS_NOR0_CSPR					\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
-	CSPR_PORT_SIZE_16					| \
-	CSPR_MSEL_NOR						| \
-	CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY				\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
-	CSPR_PORT_SIZE_16					| \
-	CSPR_MSEL_NOR						| \
-	CSPR_V)
-#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
-				FTIM0_NOR_TEADC(0x1) | \
-				FTIM0_NOR_TEAHC(0x1))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
-				FTIM1_NOR_TRAD_NOR(0x1))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
-				FTIM2_NOR_TCH(0x0) | \
-				FTIM2_NOR_TWP(0x1))
-#define CONFIG_SYS_NOR_FTIM3	0x04000000
-#define CONFIG_SYS_IFC_CCR	0x01000000
-
-#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#endif
-
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_MAX_ECCPOS	256
-#define CONFIG_SYS_NAND_MAX_OOBFREE	2
-
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
-				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
-				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
-				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
-
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
-				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
-				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
-				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
-				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
-				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
-				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
-					FTIM0_NAND_TWP(0x18)   | \
-					FTIM0_NAND_TWCHT(0x07) | \
-					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
-					FTIM1_NAND_TWBE(0x39)  | \
-					FTIM1_NAND_TRR(0x0e)   | \
-					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
-					FTIM2_NAND_TREH(0x0a) | \
-					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
-
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
-
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
-
-/*  MMC  */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
-/* Debug Server firmware */
-#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580C00000ULL
-
-/* MC firmware */
-#define CONFIG_SYS_LS_MC_DPL_IN_NOR
-#define CONFIG_SYS_LS_MC_DPL_ADDR	0x5806C0000ULL
-
-#define CONFIG_SYS_LS_MC_DPC_IN_NOR
-#define CONFIG_SYS_LS_MC_DPC_ADDR	0x5806F8000ULL
-
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
-
-/* Store environment at top of flash */
-
-#endif /* __LS2_SIMU_H */
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
deleted file mode 100644
index d2dcc8179b..0000000000
--- a/include/configs/mx35pdk.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010, Stefano Babic <sbabic@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * Configuration for the MX35pdk Freescale board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
- /* High Level Configuration Options */
-#define CONFIG_MX35
-
-#define CONFIG_SYS_FSL_CLK
-
-/* Set TEXT at the beginning of the NOR flash */
-
-#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
-
-/*
- * PMIC Configs
- */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_FSL
-#define CONFIG_POWER_FSL_MC13892
-#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x08
-#define CONFIG_RTC_MC13XXX
-
-/*
- * MFD MC9SDZ60
- */
-#define CONFIG_FSL_MC9SDZ60
-#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR	0x69
-
-/*
- * UART (console)
- */
-#define CONFIG_MXC_UART_BASE	UART1_BASE
-
-/*
- * Command definition
- */
-
-#define CONFIG_NET_RETRY_COUNT	100
-
-
-#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
-
-/*
- * Ethernet on the debug board (SMC911)
- */
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETHPRIME
-
-/*
- * Ethernet on SOC (FEC)
- */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE	FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR	0x1F
-
-#define CONFIG_ARP_TIMEOUT	200UL
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
-
-/*
- * Physical Memory Map
- */
-#define PHYS_SDRAM_1		CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
-#define PHYS_SDRAM_2		CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE	(128 * 1024 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE		CSD0_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR + 0x10000)
-#define CONFIG_SYS_INIT_RAM_SIZE		(IRAM_SIZE / 2)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					CONFIG_SYS_GBL_DATA_OFFSET)
-
-/*
- * MTD Command for mtdparts
- */
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE		CS0_BASE_ADDR
-#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512	/* max number of sectors on one chip */
-/* Monitor at beginning of flash */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
-
-/* Address and size of Redundant Environment Sector	*/
-
-/*
- * CFI FLASH driver setup
- */
-
-/* A non-standard buffered write algorithm */
-#define CONFIG_FLASH_SPANSION_S29WS_N
-
-/*
- * NAND FLASH driver setup
- */
-#define CONFIG_MXC_NAND_REGS_BASE	(NFC_BASE_ADDR)
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		(NFC_BASE_ADDR)
-#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_LARGEPAGE
-
-/* EHCI driver */
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_MXC
-#define CONFIG_MXC_USB_PORT	0
-#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERFACE_DIFF_UNI | \
-				 MXC_EHCI_POWER_PINS_ENABLED | \
-				 MXC_EHCI_OC_PIN_ACTIVE_LOW)
-#define CONFIG_MXC_USB_PORTSC	(MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
-
-/* mmc driver */
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
-#define CONFIG_SYS_FSL_ESDHC_NUM	1
-
-/*
- * Default environment and default scripts
- * to update uboot and load kernel
- */
-
-#define CONFIG_HOSTNAME "mx35pdk"
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth1\0"							\
-	"ethprime=smc911x\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip_sta=setenv bootargs ${bootargs} "			\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
-	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
-		"else run addip_sta;fi\0"				\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
-	"addtty=setenv bootargs ${bootargs}"				\
-		" console=ttymxc0,${baudrate}\0"			\
-	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
-	"loadaddr=80800000\0"						\
-	"kernel_addr_r=80800000\0"					\
-	"hostname=" CONFIG_HOSTNAME "\0"			\
-	"bootfile=" CONFIG_HOSTNAME "/uImage\0"		\
-	"ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0"	\
-	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
-		"bootm ${kernel_addr}\0"				\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
-		"run nfsargs addip addtty addmtd addmisc;"		\
-		"bootm ${kernel_addr_r}\0"				\
-	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
-		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
-	"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"		\
-	"load=tftp ${loadaddr} ${u-boot}\0"				\
-	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0"		\
-	"update=protect off ${uboot_addr} +80000;"			\
-		"erase ${uboot_addr} +80000;"				\
-		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
-	"upd=if run load;then echo Updating u-boot;if run update;"	\
-		"then echo U-Boot updated;"				\
-			"else echo Error updating u-boot !;"		\
-			"echo Board without bootloader !!;"		\
-		"fi;"							\
-		"else echo U-Boot not downloaded..exiting;fi\0"		\
-	"bootcmd=run net_nfs\0"
-
-#endif				/* __CONFIG_H */
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
deleted file mode 100644
index 0455b1c2ec..0000000000
--- a/include/configs/r7780mp.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas R7780MP board
- *
- * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
- */
-
-#ifndef __R7780RP_H
-#define __R7780RP_H
-
-#define CONFIG_CPU_SH7780	1
-#define CONFIG_R7780MP		1
-#define CONFIG_SYS_R7780MP_OLD_FLASH	1
-#define __LITTLE_ENDIAN__ 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_CONS_SCIF0	1
-
-#define CONFIG_SYS_SDRAM_BASE		(0x08000000)
-#define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE		256
-
-/* Flash board support */
-#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
-#ifdef CONFIG_SYS_R7780MP_OLD_FLASH
-/* NOR Flash (S29PL127J60TFI130) */
-# define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
-# define CONFIG_SYS_MAX_FLASH_BANKS	(2)
-# define CONFIG_SYS_MAX_FLASH_SECT	270
-# define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
-				CONFIG_SYS_FLASH_BASE + 0x100000,\
-				CONFIG_SYS_FLASH_BASE + 0x400000,\
-				CONFIG_SYS_FLASH_BASE + 0x700000, }
-#else /* CONFIG_SYS_R7780MP_OLD_FLASH */
-/* NOR Flash (Spantion S29GL256P) */
-# define CONFIG_SYS_MAX_FLASH_BANKS	(1)
-# define CONFIG_SYS_MAX_FLASH_SECT		256
-# define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
-
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
-/* Address of u-boot image in Flash */
-#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN		(1204 * 1024)
-
-#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
-#define CONFIG_SYS_RX_ETH_BUFFER	(8)
-
-#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
-#undef  CONFIG_SYS_FLASH_QUIET_TEST
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ	33333333
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-/* PCI Controller */
-#if defined(CONFIG_CMD_PCI)
-#define CONFIG_SH4_PCI
-#define CONFIG_SH7780_PCI
-#define CONFIG_SH7780_PCI_LSR	0x07f00001
-#define CONFIG_SH7780_PCI_LAR	CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_SH7780_PCI_BAR	CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_PCI_SCAN_SHOW	1
-#define __mem_pci
-
-#define CONFIG_PCI_MEM_BUS	0xFD000000	/* Memory space base addr */
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x01000000	/* Size of Memory window */
-
-#define CONFIG_PCI_IO_BUS	0xFE200000	/* IO space base address */
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x00200000	/* Size of IO window */
-#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_BUS  CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
-#endif /* CONFIG_CMD_PCI */
-
-#if defined(CONFIG_CMD_NET)
-/* AX88796L Support(NE2000 base chip) */
-#define CONFIG_DRIVER_AX88796L
-#define CONFIG_DRIVER_NE2000_BASE	0xA4100000
-#endif
-
-/* Compact flash Support */
-#if defined(CONFIG_IDE)
-#define CONFIG_IDE_RESET        1
-#define CONFIG_SYS_PIO_MODE            1
-#define CONFIG_SYS_IDE_MAXBUS          1   /* IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE       1
-#define CONFIG_SYS_ATA_BASE_ADDR       0xb4000000
-#define CONFIG_SYS_ATA_STRIDE          2               /* 1bit shift */
-#define CONFIG_SYS_ATA_DATA_OFFSET     0x1000          /* data reg offset */
-#define CONFIG_SYS_ATA_REG_OFFSET      0x1000          /* reg offset */
-#define CONFIG_SYS_ATA_ALT_OFFSET      0x800           /* alternate register offset */
-#define CONFIG_IDE_SWAP_IO
-#endif /* CONFIG_IDE */
-
-#endif /* __R7780RP_H */
diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h
deleted file mode 100644
index aeb54032d1..0000000000
--- a/include/configs/sh7752evb.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the sh7752evb board
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#ifndef __SH7752EVB_H
-#define __SH7752EVB_H
-
-#define CONFIG_CPU_SH7752	1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* MEMORY */
-#define SH7752EVB_SDRAM_BASE		(0x40000000)
-#define SH7752EVB_SDRAM_SIZE		(512 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE		256
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF2	1
-
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_SDRAM_BASE		(SH7752EVB_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE		(SH7752EVB_SDRAM_SIZE)
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
-					 128 * 1024 * 1024)
-
-#define CONFIG_SYS_MONITOR_BASE		0x00000000
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
-
-/* Ether */
-#define CONFIG_SH_ETHER_USE_PORT	0
-#define CONFIG_SH_ETHER_PHY_ADDR	18
-#define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
-#define CONFIG_SH_ETHER_USE_GETHER	1
-#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
-
-#define SH7752EVB_ETHERNET_MAC_BASE_SPI	0x00090000
-#define SH7752EVB_SPI_SECTOR_SIZE	(64 * 1024)
-#define SH7752EVB_ETHERNET_MAC_BASE	SH7752EVB_ETHERNET_MAC_BASE_SPI
-#define SH7752EVB_ETHERNET_MAC_SIZE	17
-#define SH7752EVB_ETHERNET_NUM_CH	2
-
-/* SPI */
-#define CONFIG_SH_SPI_BASE		0xfe002000
-
-/* MMCIF */
-#define CONFIG_SH_MMCIF_ADDR		0xffcb0000
-#define CONFIG_SH_MMCIF_CLK		48000000
-
-/* ENV setting */
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-		"netboot=bootp; bootm\0"
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ	48000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#endif	/* __SH7752EVB_H */
diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h
deleted file mode 100644
index 736b379ab7..0000000000
--- a/include/configs/sh7753evb.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the sh7753evb board
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#ifndef __SH7753EVB_H
-#define __SH7753EVB_H
-
-#define CONFIG_CPU_SH7753	1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* MEMORY */
-#define SH7753EVB_SDRAM_BASE		(0x40000000)
-#define SH7753EVB_SDRAM_SIZE		(512 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE		256
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF2	1
-
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_SDRAM_BASE		(SH7753EVB_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE		(SH7753EVB_SDRAM_SIZE)
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
-					 128 * 1024 * 1024)
-
-#define CONFIG_SYS_MONITOR_BASE		0x00000000
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
-
-/* Ether */
-#define CONFIG_SH_ETHER_USE_PORT	0
-#define CONFIG_SH_ETHER_PHY_ADDR	18
-#define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
-#define CONFIG_SH_ETHER_USE_GETHER	1
-#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
-
-#define SH7753EVB_ETHERNET_MAC_BASE_SPI	0x00090000
-#define SH7753EVB_SPI_SECTOR_SIZE	(64 * 1024)
-#define SH7753EVB_ETHERNET_MAC_BASE	SH7753EVB_ETHERNET_MAC_BASE_SPI
-#define SH7753EVB_ETHERNET_MAC_SIZE	17
-#define SH7753EVB_ETHERNET_NUM_CH	2
-
-/* SPI */
-#define CONFIG_SH_SPI_BASE		0xfe002000
-
-/* MMCIF */
-#define CONFIG_SH_MMCIF_ADDR		0xffcb0000
-#define CONFIG_SH_MMCIF_CLK		48000000
-
-/* ENV setting */
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-		"netboot=bootp; bootm\0"
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ	48000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#endif	/* __SH7753EVB_H */
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
deleted file mode 100644
index 7067ad13bd..0000000000
--- a/include/configs/sh7757lcr.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the sh7757lcr board
- *
- * Copyright (C) 2011 Renesas Solutions Corp.
- */
-
-#ifndef __SH7757LCR_H
-#define __SH7757LCR_H
-
-#define CONFIG_CPU_SH7757	1
-#define CONFIG_SH7757LCR_DDR_ECC	1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* MEMORY */
-#define SH7757LCR_SDRAM_BASE		(0x80000000)
-#define SH7757LCR_SDRAM_SIZE		(240 * 1024 * 1024)
-#define SH7757LCR_SDRAM_ECC_SETTING	0x0f000000	/* 240MByte */
-#define SH7757LCR_SDRAM_DVC_SIZE	(16 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE		256
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF2	1
-
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_SDRAM_BASE		(SH7757LCR_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE		(SH7757LCR_SDRAM_SIZE)
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
-					 (128 + 16) * 1024 * 1024)
-
-#define CONFIG_SYS_MONITOR_BASE		0x00000000
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
-
-/* Ether */
-#define CONFIG_SH_ETHER_USE_PORT	0
-#define CONFIG_SH_ETHER_PHY_ADDR	1
-#define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
-#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-
-#define SH7757LCR_ETHERNET_MAC_BASE_SPI	0x000b0000
-#define SH7757LCR_SPI_SECTOR_SIZE	(64 * 1024)
-#define SH7757LCR_ETHERNET_MAC_BASE	SH7757LCR_ETHERNET_MAC_BASE_SPI
-#define SH7757LCR_ETHERNET_MAC_SIZE	17
-#define SH7757LCR_ETHERNET_NUM_CH	2
-
-/* Gigabit Ether */
-#define SH7757LCR_GIGA_ETHERNET_NUM_CH	2
-
-/* SPI */
-#define CONFIG_SH_SPI_BASE		0xfe002000
-
-/* MMCIF */
-#define CONFIG_SH_MMCIF_ADDR		0xffcb0000
-#define CONFIG_SH_MMCIF_CLK		48000000
-
-/* SH7757 board */
-#define SH7757LCR_SDRAM_PHYS_TOP	0x40000000
-#define SH7757LCR_GRA_OFFSET		0x1f000000
-#define SH7757LCR_PCIEBRG_ADDR_B0	0x000a0000
-#define SH7757LCR_PCIEBRG_SIZE_B0	(64 * 1024)
-#define SH7757LCR_PCIEBRG_ADDR		0x00090000
-#define SH7757LCR_PCIEBRG_SIZE		(96 * 1024)
-
-/* ENV setting */
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-		"netboot=bootp; bootm\0"
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ	48000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#endif	/* __SH7757LCR_H */
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
deleted file mode 100644
index 5e27f3b8f1..0000000000
--- a/include/configs/sh7763rdp.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas SH7763RDP board
- *
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
- */
-
-#ifndef __SH7763RDP_H
-#define __SH7763RDP_H
-
-#define CONFIG_CPU_SH7763	1
-#define __LITTLE_ENDIAN		1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* SCIF */
-#define CONFIG_CONS_SCIF2		1
-
-#define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate
-												settings for this board */
-
-/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
-#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
-
-/* Flash(NOR) */
-#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
-#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
-#define CONFIG_SYS_MAX_FLASH_BANKS (1)
-#define CONFIG_SYS_MAX_FLASH_SECT  (520)
-
-/* U-Boot setting */
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
-#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
-
-#undef  CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
-/* Timeout for Flash erase operations (in ms) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
-/* Timeout for Flash write operations (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
-/* Timeout for Flash set sector lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
-/* Timeout for Flash clear lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
-/* Use hardware flash sectors protection instead of U-Boot software protection */
-#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
-/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
-
-/* Clock */
-#define CONFIG_SYS_CLK_FREQ	66666666
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-/* Ether */
-#define CONFIG_SH_ETHER_USE_PORT (1)
-#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
-#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-
-#endif /* __SH7763RDP_H */