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authorMarek Vasut <marex@denx.de>2018-05-08 18:44:00 +0200
committerMarek Vasut <marex@denx.de>2019-03-09 17:59:14 +0100
commit60082d3b3ff17fc0c5ae6c1cdd176219554ed61f (patch)
treed4085455e28b64b25bc542cf3acf6707d7661d11 /include
parent7544ad0303013e625c9500a4d87d4e5bfe369ee4 (diff)
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ARM: socfpga: Drop CONFIG_SYS_NAND_BAD_BLOCK_POS
This is not used anywhere, so drop it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/socfpga_common.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index c9cbf8f5e3..f182e9e71b 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -280,7 +280,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
/* SPL NAND boot support */
#ifdef CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#endif